Lines Matching +full:0 +full:xfee00000
3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver
24 #define PHYREG6 0x14
29 #define PHYREG7 0x18
33 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0)
34 #define PHYREG7_RX_RTERM_SHIFT 0
37 #define PHYREG8 0x1C
40 #define PHYREG10 0x24
41 #define PHYREG10_SSC_PCM_MASK GENMASK(3, 0)
44 #define PHYREG11 0x28
45 #define PHYREG11_SU_TRIM_0_7 0xF0
47 #define PHYREG12 0x2C
50 #define PHYREG13 0x30
52 #define PHYREG13_RESISTER_SHIFT 0x4
56 #define PHYREG14 0x34
57 #define PHYREG14_CKRCV_AMP1 BIT(0)
59 #define PHYREG15 0x38
60 #define PHYREG15_CTLE_EN BIT(0)
65 #define PHYREG16 0x3C
66 #define PHYREG16_SSC_CNT_VALUE 0x5f
68 #define PHYREG17 0x40
70 #define PHYREG18 0x44
71 #define PHYREG18_PLL_LOOP 0x32
73 #define PHYREG21 0x50
74 #define PHYREG21_RX_SQUELCH_VAL 0x0D
76 #define PHYREG27 0x6C
77 #define PHYREG27_RX_TRIM_RK3588 0x4C
79 #define PHYREG30 0x74
81 #define PHYREG32 0x7C
85 #define PHYREG32_SSC_UPWARD 0
91 #define PHYREG33 0x80
248 return 0; in rockchip_combphy_init()
263 return 0; in rockchip_combphy_exit()
281 if (priv->type != PHY_NONE && priv->type != args->args[0]) in rockchip_combphy_xlate()
283 args->args[0], priv->type); in rockchip_combphy_xlate()
285 priv->type = args->args[0]; in rockchip_combphy_xlate()
299 for (i = 0; i < priv->num_clks; i++) { in rockchip_combphy_parse_dt()
334 return 0; in rockchip_combphy_parse_dt()
356 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); in rockchip_combphy_probe()
364 for (id = 0; id < phy_cfg->num_phys; id++) { in rockchip_combphy_probe()
423 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3562_combphy_cfg()
458 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ in rk3562_combphy_cfg()
478 writel(0x4, priv->mmio + PHYREG12); in rk3562_combphy_cfg()
484 writel(0x32, priv->mmio + PHYREG18); in rk3562_combphy_cfg()
485 writel(0xf0, priv->mmio + PHYREG11); in rk3562_combphy_cfg()
512 return 0; in rk3562_combphy_cfg()
517 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
518 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
519 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
520 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
521 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
522 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
523 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
524 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
525 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
526 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
527 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
528 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
529 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
530 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
531 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
532 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
533 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
534 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
535 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
541 0xff750000
572 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3568_combphy_cfg()
606 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3568_combphy_cfg()
644 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3568_combphy_cfg()
706 return 0; in rk3568_combphy_cfg()
711 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
712 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
713 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 },
714 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 },
715 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
716 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
717 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
718 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
719 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
720 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
721 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
722 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
723 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
724 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
725 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
726 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 },
727 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 },
728 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
729 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
730 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
731 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
732 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
733 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 },
734 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 },
735 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 },
736 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 },
738 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 },
739 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 },
745 0xfe820000,
746 0xfe830000,
747 0xfe840000,
776 /* Enable adaptive CTLE for USB3.0 Rx */ in rk3576_combphy_cfg()
835 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz */ in rk3576_combphy_cfg()
848 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
852 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
856 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
857 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
858 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
872 writel(0xc0, priv->mmio + PHYREG30); in rk3576_combphy_cfg()
880 writel(0x4c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
884 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
890 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
891 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
892 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
893 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
920 writel(0x0c, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
924 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
930 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
931 writel(0x43, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
932 writel(0x88, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
933 writel(0x56, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
944 writel(0x00, priv->mmio + PHYREG17); in rk3576_combphy_cfg()
948 writel(0x00, priv->mmio + PHYREG27); in rk3576_combphy_cfg()
952 * su_trim[7:0], PLL KVCO adjust bits[2:0] to min in rk3576_combphy_cfg()
957 writel(0x90, priv->mmio + PHYREG11); in rk3576_combphy_cfg()
958 writel(0x02, priv->mmio + PHYREG12); in rk3576_combphy_cfg()
959 writel(0x08, priv->mmio + PHYREG13); in rk3576_combphy_cfg()
960 writel(0x57, priv->mmio + PHYREG14); in rk3576_combphy_cfg()
961 writel(0x40, priv->mmio + PHYREG15); in rk3576_combphy_cfg()
970 return 0; in rk3576_combphy_cfg()
975 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
976 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
977 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
978 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
979 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
980 .pipe_clk_24m = { 0x0004, 14, 13, 0x00, 0x00 },
981 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
982 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
983 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 },
984 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 },
985 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
986 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
987 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
988 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
989 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
990 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
991 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
992 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
993 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
994 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
995 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
996 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
997 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
999 .pipe_con0_for_sata = { 0x001C, 2, 0, 0x00, 0x2 },
1000 .pipe_con1_for_sata = { 0x0020, 2, 0, 0x00, 0x2 },
1006 0x2b050000,
1007 0x2b060000
1040 /* Enable adaptive CTLE for USB3.0 Rx. */ in rk3588_combphy_cfg()
1072 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) in rk3588_combphy_cfg()
1097 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ in rk3588_combphy_cfg()
1156 return 0; in rk3588_combphy_cfg()
1161 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 },
1162 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 },
1163 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 },
1164 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 },
1165 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 },
1166 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 },
1167 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 },
1168 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 },
1169 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 },
1170 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 },
1171 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 },
1172 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 },
1173 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 },
1174 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 },
1175 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 },
1176 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 },
1177 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0129 },
1178 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0000 },
1179 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c1 },
1180 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x0407 },
1182 .pipe_con0_for_sata = { 0x0000, 11, 5, 0x00, 0x22 },
1183 .pipe_con1_for_sata = { 0x0000, 2, 0, 0x00, 0x2 },
1184 .pipe_pcie1l0_sel = { 0x0100, 0, 0, 0x01, 0x0 },
1185 .pipe_pcie1l1_sel = { 0x0100, 1, 1, 0x01, 0x0 },
1191 0xfee00000,
1192 0xfee10000,
1193 0xfee20000,