1 // SPDX-License-Identifier: GPL-2.0+
7 #include <linux/clk-provider.h>
101 	const struct qcom_uniphy_pcie_data *data = phy->data;  in qcom_uniphy_pcie_init()
103 	void __iomem *base = phy->base;  in qcom_uniphy_pcie_init()
106 	for (lane = 0; lane < phy->lanes; lane++) {  in qcom_uniphy_pcie_init()
107 		init_seq = data->init_seq;  in qcom_uniphy_pcie_init()
109 		for (i = 0; i < data->init_seq_num; i++)  in qcom_uniphy_pcie_init()
112 		base += data->lane_offset;  in qcom_uniphy_pcie_init()
120 	clk_bulk_disable_unprepare(phy->num_clks, phy->clks);  in qcom_uniphy_pcie_power_off()
122 	return reset_control_assert(phy->resets);  in qcom_uniphy_pcie_power_off()
130 	ret = reset_control_assert(phy->resets);  in qcom_uniphy_pcie_power_on()
132 		dev_err(phy->dev, "reset assert failed (%d)\n", ret);  in qcom_uniphy_pcie_power_on()
138 	ret = reset_control_deassert(phy->resets);  in qcom_uniphy_pcie_power_on()
140 		dev_err(phy->dev, "reset deassert failed (%d)\n", ret);  in qcom_uniphy_pcie_power_on()
146 	ret = clk_bulk_prepare_enable(phy->num_clks, phy->clks);  in qcom_uniphy_pcie_power_on()
148 		dev_err(phy->dev, "clk prepare and enable failed %d\n", ret);  in qcom_uniphy_pcie_power_on()
164 	phy->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res);  in qcom_uniphy_pcie_get_resources()
165 	if (IS_ERR(phy->base))  in qcom_uniphy_pcie_get_resources()
166 		return PTR_ERR(phy->base);  in qcom_uniphy_pcie_get_resources()
168 	phy->num_clks = devm_clk_bulk_get_all(phy->dev, &phy->clks);  in qcom_uniphy_pcie_get_resources()
169 	if (phy->num_clks < 0)  in qcom_uniphy_pcie_get_resources()
170 		return phy->num_clks;  in qcom_uniphy_pcie_get_resources()
172 	phy->resets = devm_reset_control_array_get_exclusive(phy->dev);  in qcom_uniphy_pcie_get_resources()
173 	if (IS_ERR(phy->resets))  in qcom_uniphy_pcie_get_resources()
174 		return PTR_ERR(phy->resets);  in qcom_uniphy_pcie_get_resources()
182  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
183  * controls it. The <s>_pipe_clk coming out of the GCC is requested
185  * We register the <s>_pipe_clksrc here. The gcc driver takes care
189  *         +---------------+
190  *         |   PHY block   |<<---------------------------------------+
192  *         |   +-------+   |                   +-----+               |
193  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
194  *    clk  |   +-------+   |                   +-----+
195  *         +---------------+
199 	const struct qcom_uniphy_pcie_data *data = phy->data;  in phy_pipe_clk_register()
204 	hw = devm_clk_hw_register_fixed_rate(phy->dev, name, NULL, 0,  in phy_pipe_clk_register()
205 					     data->pipe_clk_rate);  in phy_pipe_clk_register()
207 		return dev_err_probe(phy->dev, PTR_ERR(hw),  in phy_pipe_clk_register()
210 	return devm_of_clk_add_hw_provider(phy->dev, of_clk_hw_simple_get, hw);  in phy_pipe_clk_register()
215 		.compatible = "qcom,ipq5332-uniphy-pcie-phy",
232 	struct device *dev = &pdev->dev;  in qcom_uniphy_pcie_probe()
237 	phy = devm_kzalloc(&pdev->dev, sizeof(*phy), GFP_KERNEL);  in qcom_uniphy_pcie_probe()
239 		return -ENOMEM;  in qcom_uniphy_pcie_probe()
242 	phy->dev = &pdev->dev;  in qcom_uniphy_pcie_probe()
244 	phy->data = of_device_get_match_data(dev);  in qcom_uniphy_pcie_probe()
245 	if (!phy->data)  in qcom_uniphy_pcie_probe()
246 		return -EINVAL;  in qcom_uniphy_pcie_probe()
248 	ret = of_property_read_u32(dev_of_node(dev), "num-lanes", &phy->lanes);  in qcom_uniphy_pcie_probe()
250 		return dev_err_probe(dev, ret, "Couldn't read num-lanes\n");  in qcom_uniphy_pcie_probe()
254 		return dev_err_probe(&pdev->dev, ret,  in qcom_uniphy_pcie_probe()
257 	generic_phy = devm_phy_create(phy->dev, NULL, &pcie_ops);  in qcom_uniphy_pcie_probe()
263 	ret = phy_pipe_clk_register(phy, generic_phy->id);  in qcom_uniphy_pcie_probe()
265 		dev_err(&pdev->dev, "failed to register phy pipe clk\n");  in qcom_uniphy_pcie_probe()
267 	phy_provider = devm_of_phy_provider_register(phy->dev,  in qcom_uniphy_pcie_probe()
278 		.name	= "qcom-uniphy-pcie",