Lines Matching +full:sar2130p +full:- +full:gcc
1 // SPDX-License-Identifier: GPL-2.0
7 #include <linux/clk-provider.h>
25 #include <dt-bindings/phy/phy-qcom-qmp.h>
27 #include "phy-qcom-qmp-common.h"
29 #include "phy-qcom-qmp.h"
30 #include "phy-qcom-qmp-pcs-misc-v3.h"
31 #include "phy-qcom-qmp-pcs-pcie-v4.h"
32 #include "phy-qcom-qmp-pcs-pcie-v4_20.h"
33 #include "phy-qcom-qmp-pcs-pcie-v5.h"
34 #include "phy-qcom-qmp-pcs-pcie-v5_20.h"
35 #include "phy-qcom-qmp-pcs-pcie-v6.h"
36 #include "phy-qcom-qmp-pcs-pcie-v6_20.h"
37 #include "phy-qcom-qmp-pcs-pcie-v6_30.h"
38 #include "phy-qcom-qmp-pcs-v6_30.h"
39 #include "phy-qcom-qmp-pcie-qhp.h"
43 /* set of registers with offsets different per-PHY */
2987 /* struct qmp_phy_cfg - per-PHY initialization config */
2993 /* Main init sequence for PHY blocks - serdes, tx, rx, pcs */
3099 "vdda-phy", "vdda-pll",
3103 "vdda-phy", "vdda-pll", "vdda-qref",
4262 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_port_b()
4263 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_init_port_b()
4266 serdes = qmp->port_b + offs->serdes; in qmp_pcie_init_port_b()
4267 tx3 = qmp->port_b + offs->tx; in qmp_pcie_init_port_b()
4268 rx3 = qmp->port_b + offs->rx; in qmp_pcie_init_port_b()
4269 tx4 = qmp->port_b + offs->tx2; in qmp_pcie_init_port_b()
4270 rx4 = qmp->port_b + offs->rx2; in qmp_pcie_init_port_b()
4271 pcs = qmp->port_b + offs->pcs; in qmp_pcie_init_port_b()
4272 pcs_misc = qmp->port_b + offs->pcs_misc; in qmp_pcie_init_port_b()
4273 ln_shrd = qmp->port_b + offs->ln_shrd; in qmp_pcie_init_port_b()
4275 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_port_b()
4276 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, cfg->serdes_4ln_num); in qmp_pcie_init_port_b()
4278 qmp_configure_lane(qmp->dev, tx3, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_port_b()
4279 qmp_configure_lane(qmp->dev, rx3, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_port_b()
4281 qmp_configure_lane(qmp->dev, tx4, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_port_b()
4282 qmp_configure_lane(qmp->dev, rx4, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_port_b()
4284 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_port_b()
4285 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_port_b()
4287 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_port_b()
4292 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init_registers()
4293 void __iomem *serdes = qmp->serdes; in qmp_pcie_init_registers()
4294 void __iomem *tx = qmp->tx; in qmp_pcie_init_registers()
4295 void __iomem *rx = qmp->rx; in qmp_pcie_init_registers()
4296 void __iomem *tx2 = qmp->tx2; in qmp_pcie_init_registers()
4297 void __iomem *rx2 = qmp->rx2; in qmp_pcie_init_registers()
4298 void __iomem *pcs = qmp->pcs; in qmp_pcie_init_registers()
4299 void __iomem *pcs_misc = qmp->pcs_misc; in qmp_pcie_init_registers()
4300 void __iomem *pcs_lane1 = qmp->pcs_lane1; in qmp_pcie_init_registers()
4301 void __iomem *ln_shrd = qmp->ln_shrd; in qmp_pcie_init_registers()
4306 qmp_configure(qmp->dev, serdes, tbls->serdes, tbls->serdes_num); in qmp_pcie_init_registers()
4312 qmp_configure(qmp->dev, qmp->txz, tbls->txz, tbls->txz_num); in qmp_pcie_init_registers()
4313 qmp_configure(qmp->dev, qmp->rxz, tbls->rxz, tbls->rxz_num); in qmp_pcie_init_registers()
4315 qmp_configure_lane(qmp->dev, tx, tbls->tx, tbls->tx_num, 1); in qmp_pcie_init_registers()
4316 qmp_configure_lane(qmp->dev, rx, tbls->rx, tbls->rx_num, 1); in qmp_pcie_init_registers()
4318 if (cfg->lanes >= 2) { in qmp_pcie_init_registers()
4319 qmp_configure_lane(qmp->dev, tx2, tbls->tx, tbls->tx_num, 2); in qmp_pcie_init_registers()
4320 qmp_configure_lane(qmp->dev, rx2, tbls->rx, tbls->rx_num, 2); in qmp_pcie_init_registers()
4323 qmp_configure(qmp->dev, pcs, tbls->pcs, tbls->pcs_num); in qmp_pcie_init_registers()
4324 qmp_configure(qmp->dev, pcs_misc, tbls->pcs_misc, tbls->pcs_misc_num); in qmp_pcie_init_registers()
4325 qmp_configure(qmp->dev, pcs_lane1, tbls->pcs_lane1, tbls->pcs_lane1_num); in qmp_pcie_init_registers()
4327 if (cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_init_registers()
4328 qmp_configure(qmp->dev, serdes, cfg->serdes_4ln_tbl, in qmp_pcie_init_registers()
4329 cfg->serdes_4ln_num); in qmp_pcie_init_registers()
4333 qmp_configure(qmp->dev, ln_shrd, tbls->ln_shrd, tbls->ln_shrd_num); in qmp_pcie_init_registers()
4339 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_init()
4342 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
4344 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); in qmp_pcie_init()
4348 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4350 dev_err(qmp->dev, "reset assert failed\n"); in qmp_pcie_init()
4354 ret = reset_control_assert(qmp->nocsr_reset); in qmp_pcie_init()
4356 dev_err(qmp->dev, "no-csr reset assert failed\n"); in qmp_pcie_init()
4362 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4364 dev_err(qmp->dev, "reset deassert failed\n"); in qmp_pcie_init()
4368 ret = clk_bulk_prepare_enable(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_init()
4375 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_init()
4377 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_init()
4385 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_exit()
4387 reset_control_bulk_assert(cfg->num_resets, qmp->resets); in qmp_pcie_exit()
4389 clk_bulk_disable_unprepare(ARRAY_SIZE(qmp_pciephy_clk_l), qmp->clks); in qmp_pcie_exit()
4391 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); in qmp_pcie_exit()
4399 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_on()
4401 void __iomem *pcs = qmp->pcs; in qmp_pcie_power_on()
4406 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_on()
4407 cfg->pwrdn_ctrl); in qmp_pcie_power_on()
4409 if (qmp->mode == PHY_MODE_PCIE_RC) in qmp_pcie_power_on()
4410 mode_tbls = cfg->tbls_rc; in qmp_pcie_power_on()
4412 mode_tbls = cfg->tbls_ep; in qmp_pcie_power_on()
4414 qmp_pcie_init_registers(qmp, &cfg->tbls); in qmp_pcie_power_on()
4417 ret = clk_bulk_prepare_enable(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
4421 ret = reset_control_deassert(qmp->nocsr_reset); in qmp_pcie_power_on()
4423 dev_err(qmp->dev, "no-csr reset deassert failed\n"); in qmp_pcie_power_on()
4428 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_on()
4430 /* start SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_on()
4431 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); in qmp_pcie_power_on()
4433 if (!cfg->skip_start_delay) in qmp_pcie_power_on()
4436 status = pcs + cfg->regs[QPHY_PCS_STATUS]; in qmp_pcie_power_on()
4437 mask = cfg->phy_status; in qmp_pcie_power_on()
4441 dev_err(qmp->dev, "phy initialization timed-out\n"); in qmp_pcie_power_on()
4448 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_on()
4456 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_power_off()
4458 clk_bulk_disable_unprepare(qmp->num_pipe_clks, qmp->pipe_clks); in qmp_pcie_power_off()
4461 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); in qmp_pcie_power_off()
4463 /* stop SerDes and Phy-Coding-Sublayer */ in qmp_pcie_power_off()
4464 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], in qmp_pcie_power_off()
4468 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], in qmp_pcie_power_off()
4469 cfg->pwrdn_ctrl); in qmp_pcie_power_off()
4507 qmp->mode = submode; in qmp_pcie_set_mode()
4510 dev_err(&phy->dev, "Unsupported submode %d\n", submode); in qmp_pcie_set_mode()
4511 return -EINVAL; in qmp_pcie_set_mode()
4526 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_vreg_init()
4527 struct device *dev = qmp->dev; in qmp_pcie_vreg_init()
4528 int num = cfg->num_vregs; in qmp_pcie_vreg_init()
4531 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); in qmp_pcie_vreg_init()
4532 if (!qmp->vregs) in qmp_pcie_vreg_init()
4533 return -ENOMEM; in qmp_pcie_vreg_init()
4536 qmp->vregs[i].supply = cfg->vreg_list[i]; in qmp_pcie_vreg_init()
4538 return devm_regulator_bulk_get(dev, num, qmp->vregs); in qmp_pcie_vreg_init()
4543 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_reset_init()
4544 struct device *dev = qmp->dev; in qmp_pcie_reset_init()
4548 qmp->resets = devm_kcalloc(dev, cfg->num_resets, in qmp_pcie_reset_init()
4549 sizeof(*qmp->resets), GFP_KERNEL); in qmp_pcie_reset_init()
4550 if (!qmp->resets) in qmp_pcie_reset_init()
4551 return -ENOMEM; in qmp_pcie_reset_init()
4553 for (i = 0; i < cfg->num_resets; i++) in qmp_pcie_reset_init()
4554 qmp->resets[i].id = cfg->reset_list[i]; in qmp_pcie_reset_init()
4556 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); in qmp_pcie_reset_init()
4560 if (cfg->has_nocsr_reset) { in qmp_pcie_reset_init()
4561 qmp->nocsr_reset = devm_reset_control_get_exclusive(dev, "phy_nocsr"); in qmp_pcie_reset_init()
4562 if (IS_ERR(qmp->nocsr_reset)) in qmp_pcie_reset_init()
4563 return dev_err_probe(dev, PTR_ERR(qmp->nocsr_reset), in qmp_pcie_reset_init()
4564 "failed to get no-csr reset\n"); in qmp_pcie_reset_init()
4572 struct device *dev = qmp->dev; in qmp_pcie_clk_init()
4576 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); in qmp_pcie_clk_init()
4577 if (!qmp->clks) in qmp_pcie_clk_init()
4578 return -ENOMEM; in qmp_pcie_clk_init()
4581 qmp->clks[i].id = qmp_pciephy_clk_l[i]; in qmp_pcie_clk_init()
4583 return devm_clk_bulk_get_optional(dev, num, qmp->clks); in qmp_pcie_clk_init()
4594 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
4595 * controls it. The <s>_pipe_clk coming out of the GCC is requested
4597 * We register the <s>_pipe_clksrc here. The gcc driver takes care
4601 * +---------------+
4602 * | PHY block |<<---------------------------------------+
4604 * | +-------+ | +-----+ |
4605 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
4606 * clk | +-------+ | +-----+
4607 * +---------------+
4611 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; in phy_pipe_clk_register()
4615 ret = of_property_read_string_index(np, "clock-output-names", 0, &init.name); in phy_pipe_clk_register()
4617 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); in phy_pipe_clk_register()
4624 * Controllers using QMP PHY-s use 125MHz pipe clock interface in phy_pipe_clk_register()
4627 if (qmp->cfg->pipe_clock_rate) in phy_pipe_clk_register()
4628 fixed->fixed_rate = qmp->cfg->pipe_clock_rate; in phy_pipe_clk_register()
4630 fixed->fixed_rate = 125000000; in phy_pipe_clk_register()
4632 fixed->hw.init = &init; in phy_pipe_clk_register()
4634 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_pipe_clk_register()
4640 * The <s>_phy_aux_clksrc generated by PHY goes to the GCC that gate
4641 * controls it. The <s>_phy_aux_clk coming out of the GCC is requested
4643 * We register the <s>_phy_aux_clksrc here. The gcc driver takes care
4647 * +---------------+
4648 * | PHY block |<<---------------------------------------------+
4650 * | +-------+ | +-----+ |
4651 * I/P---^-->| PLL |---^--->phy_aux_clksrc--->| GCC |--->phy_aux_clk---+
4652 * clk | +-------+ | +-----+
4653 * +---------------+
4657 struct clk_fixed_rate *fixed = &qmp->aux_clk_fixed; in phy_aux_clk_register()
4661 snprintf(name, sizeof(name), "%s::phy_aux_clk", dev_name(qmp->dev)); in phy_aux_clk_register()
4666 fixed->fixed_rate = qmp->cfg->aux_clock_rate; in phy_aux_clk_register()
4667 fixed->hw.init = &init; in phy_aux_clk_register()
4669 return devm_clk_hw_register(qmp->dev, &fixed->hw); in phy_aux_clk_register()
4677 if (!clkspec->args_count) in qmp_pcie_clk_hw_get()
4678 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4680 switch (clkspec->args[0]) { in qmp_pcie_clk_hw_get()
4682 return &qmp->pipe_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4684 return &qmp->aux_clk_fixed.hw; in qmp_pcie_clk_hw_get()
4687 return ERR_PTR(-EINVAL); in qmp_pcie_clk_hw_get()
4698 if (qmp->cfg->aux_clock_rate) { in qmp_pcie_register_clocks()
4707 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &qmp->pipe_clk_fixed.hw); in qmp_pcie_register_clocks()
4716 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); in qmp_pcie_register_clocks()
4721 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt_legacy()
4722 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt_legacy()
4723 struct device *dev = qmp->dev; in qmp_pcie_parse_dt_legacy()
4726 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); in qmp_pcie_parse_dt_legacy()
4727 if (IS_ERR(qmp->serdes)) in qmp_pcie_parse_dt_legacy()
4728 return PTR_ERR(qmp->serdes); in qmp_pcie_parse_dt_legacy()
4732 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. in qmp_pcie_parse_dt_legacy()
4733 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 in qmp_pcie_parse_dt_legacy()
4734 * For single lane PHYs: pcs_misc (optional) -> 3. in qmp_pcie_parse_dt_legacy()
4736 qmp->tx = devm_of_iomap(dev, np, 0, NULL); in qmp_pcie_parse_dt_legacy()
4737 if (IS_ERR(qmp->tx)) in qmp_pcie_parse_dt_legacy()
4738 return PTR_ERR(qmp->tx); in qmp_pcie_parse_dt_legacy()
4740 if (of_device_is_compatible(dev->of_node, "qcom,sdm845-qhp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4741 qmp->rx = qmp->tx; in qmp_pcie_parse_dt_legacy()
4743 qmp->rx = devm_of_iomap(dev, np, 1, NULL); in qmp_pcie_parse_dt_legacy()
4744 if (IS_ERR(qmp->rx)) in qmp_pcie_parse_dt_legacy()
4745 return PTR_ERR(qmp->rx); in qmp_pcie_parse_dt_legacy()
4747 qmp->pcs = devm_of_iomap(dev, np, 2, NULL); in qmp_pcie_parse_dt_legacy()
4748 if (IS_ERR(qmp->pcs)) in qmp_pcie_parse_dt_legacy()
4749 return PTR_ERR(qmp->pcs); in qmp_pcie_parse_dt_legacy()
4751 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt_legacy()
4752 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4753 if (IS_ERR(qmp->tx2)) in qmp_pcie_parse_dt_legacy()
4754 return PTR_ERR(qmp->tx2); in qmp_pcie_parse_dt_legacy()
4756 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); in qmp_pcie_parse_dt_legacy()
4757 if (IS_ERR(qmp->rx2)) in qmp_pcie_parse_dt_legacy()
4758 return PTR_ERR(qmp->rx2); in qmp_pcie_parse_dt_legacy()
4760 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); in qmp_pcie_parse_dt_legacy()
4762 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); in qmp_pcie_parse_dt_legacy()
4765 if (IS_ERR(qmp->pcs_misc) && in qmp_pcie_parse_dt_legacy()
4766 of_device_is_compatible(dev->of_node, "qcom,ipq6018-qmp-pcie-phy")) in qmp_pcie_parse_dt_legacy()
4767 qmp->pcs_misc = qmp->pcs + 0x400; in qmp_pcie_parse_dt_legacy()
4769 if (IS_ERR(qmp->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4770 if (cfg->tbls.pcs_misc || in qmp_pcie_parse_dt_legacy()
4771 (cfg->tbls_rc && cfg->tbls_rc->pcs_misc) || in qmp_pcie_parse_dt_legacy()
4772 (cfg->tbls_ep && cfg->tbls_ep->pcs_misc)) { in qmp_pcie_parse_dt_legacy()
4773 return PTR_ERR(qmp->pcs_misc); in qmp_pcie_parse_dt_legacy()
4781 if (!IS_ERR(qmp->pcs_misc) && cfg->offsets->pcs_lane1 != 0) in qmp_pcie_parse_dt_legacy()
4782 qmp->pcs_lane1 = qmp->pcs_misc + in qmp_pcie_parse_dt_legacy()
4783 (cfg->offsets->pcs_lane1 - cfg->offsets->pcs_misc); in qmp_pcie_parse_dt_legacy()
4791 qmp->num_pipe_clks = 1; in qmp_pcie_parse_dt_legacy()
4792 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt_legacy()
4793 qmp->pipe_clks[0].clk = clk; in qmp_pcie_parse_dt_legacy()
4804 tcsr = syscon_regmap_lookup_by_phandle_args(qmp->dev->of_node, in qmp_pcie_get_4ln_config()
4805 "qcom,4ln-config-sel", in qmp_pcie_get_4ln_config()
4809 if (ret == -ENOENT) in qmp_pcie_get_4ln_config()
4812 dev_err(qmp->dev, "failed to lookup syscon: %d\n", ret); in qmp_pcie_get_4ln_config()
4818 dev_err(qmp->dev, "failed to read tcsr: %d\n", ret); in qmp_pcie_get_4ln_config()
4822 qmp->tcsr_4ln_config = ret; in qmp_pcie_get_4ln_config()
4824 dev_dbg(qmp->dev, "4ln_config_sel = %d\n", qmp->tcsr_4ln_config); in qmp_pcie_get_4ln_config()
4831 struct platform_device *pdev = to_platform_device(qmp->dev); in qmp_pcie_parse_dt()
4832 const struct qmp_phy_cfg *cfg = qmp->cfg; in qmp_pcie_parse_dt()
4833 const struct qmp_pcie_offsets *offs = cfg->offsets; in qmp_pcie_parse_dt()
4834 struct device *dev = qmp->dev; in qmp_pcie_parse_dt()
4839 return -EINVAL; in qmp_pcie_parse_dt()
4849 qmp->serdes = base + offs->serdes; in qmp_pcie_parse_dt()
4850 qmp->pcs = base + offs->pcs; in qmp_pcie_parse_dt()
4851 qmp->pcs_misc = base + offs->pcs_misc; in qmp_pcie_parse_dt()
4852 qmp->pcs_lane1 = base + offs->pcs_lane1; in qmp_pcie_parse_dt()
4853 qmp->tx = base + offs->tx; in qmp_pcie_parse_dt()
4854 qmp->rx = base + offs->rx; in qmp_pcie_parse_dt()
4856 if (cfg->lanes >= 2) { in qmp_pcie_parse_dt()
4857 qmp->tx2 = base + offs->tx2; in qmp_pcie_parse_dt()
4858 qmp->rx2 = base + offs->rx2; in qmp_pcie_parse_dt()
4861 if (qmp->cfg->lanes >= 4 && qmp->tcsr_4ln_config) { in qmp_pcie_parse_dt()
4862 qmp->port_b = devm_platform_ioremap_resource(pdev, 1); in qmp_pcie_parse_dt()
4863 if (IS_ERR(qmp->port_b)) in qmp_pcie_parse_dt()
4864 return PTR_ERR(qmp->port_b); in qmp_pcie_parse_dt()
4867 qmp->txz = base + offs->txz; in qmp_pcie_parse_dt()
4868 qmp->rxz = base + offs->rxz; in qmp_pcie_parse_dt()
4870 if (cfg->tbls.ln_shrd) in qmp_pcie_parse_dt()
4871 qmp->ln_shrd = base + offs->ln_shrd; in qmp_pcie_parse_dt()
4873 qmp->num_pipe_clks = 2; in qmp_pcie_parse_dt()
4874 qmp->pipe_clks[0].id = "pipe"; in qmp_pcie_parse_dt()
4875 qmp->pipe_clks[1].id = "pipediv2"; in qmp_pcie_parse_dt()
4877 ret = devm_clk_bulk_get(dev, 1, qmp->pipe_clks); in qmp_pcie_parse_dt()
4881 ret = devm_clk_bulk_get_optional(dev, qmp->num_pipe_clks - 1, qmp->pipe_clks + 1); in qmp_pcie_parse_dt()
4890 struct device *dev = &pdev->dev; in qmp_pcie_probe()
4898 return -ENOMEM; in qmp_pcie_probe()
4900 qmp->dev = dev; in qmp_pcie_probe()
4902 qmp->cfg = of_device_get_match_data(dev); in qmp_pcie_probe()
4903 if (!qmp->cfg) in qmp_pcie_probe()
4904 return -EINVAL; in qmp_pcie_probe()
4906 WARN_ON_ONCE(!qmp->cfg->pwrdn_ctrl); in qmp_pcie_probe()
4907 WARN_ON_ONCE(!qmp->cfg->phy_status); in qmp_pcie_probe()
4922 np = of_get_next_available_child(dev->of_node, NULL); in qmp_pcie_probe()
4926 np = of_node_get(dev->of_node); in qmp_pcie_probe()
4936 qmp->mode = PHY_MODE_PCIE_RC; in qmp_pcie_probe()
4938 qmp->phy = devm_phy_create(dev, np, &qmp_pcie_phy_ops); in qmp_pcie_probe()
4939 if (IS_ERR(qmp->phy)) { in qmp_pcie_probe()
4940 ret = PTR_ERR(qmp->phy); in qmp_pcie_probe()
4945 phy_set_drvdata(qmp->phy, qmp); in qmp_pcie_probe()
4960 .compatible = "qcom,ipq6018-qmp-pcie-phy",
4963 .compatible = "qcom,ipq8074-qmp-gen3-pcie-phy",
4966 .compatible = "qcom,ipq8074-qmp-pcie-phy",
4969 .compatible = "qcom,ipq9574-qmp-gen3x1-pcie-phy",
4972 .compatible = "qcom,ipq9574-qmp-gen3x2-pcie-phy",
4975 .compatible = "qcom,msm8998-qmp-pcie-phy",
4978 .compatible = "qcom,qcs615-qmp-gen3x1-pcie-phy",
4981 .compatible = "qcom,qcs8300-qmp-gen4x2-pcie-phy",
4984 .compatible = "qcom,sa8775p-qmp-gen4x2-pcie-phy",
4987 .compatible = "qcom,sa8775p-qmp-gen4x4-pcie-phy",
4990 .compatible = "qcom,sar2130p-qmp-gen3x2-pcie-phy",
4993 .compatible = "qcom,sc8180x-qmp-pcie-phy",
4996 .compatible = "qcom,sc8280xp-qmp-gen3x1-pcie-phy",
4999 .compatible = "qcom,sc8280xp-qmp-gen3x2-pcie-phy",
5002 .compatible = "qcom,sc8280xp-qmp-gen3x4-pcie-phy",
5005 .compatible = "qcom,sdm845-qhp-pcie-phy",
5008 .compatible = "qcom,sdm845-qmp-pcie-phy",
5011 .compatible = "qcom,sdx55-qmp-pcie-phy",
5014 .compatible = "qcom,sdx65-qmp-gen4x2-pcie-phy",
5017 .compatible = "qcom,sm8150-qmp-gen3x1-pcie-phy",
5020 .compatible = "qcom,sm8150-qmp-gen3x2-pcie-phy",
5023 .compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy",
5026 .compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy",
5029 .compatible = "qcom,sm8250-qmp-modem-pcie-phy",
5032 .compatible = "qcom,sm8350-qmp-gen3x1-pcie-phy",
5035 .compatible = "qcom,sm8350-qmp-gen3x2-pcie-phy",
5038 .compatible = "qcom,sm8450-qmp-gen3x1-pcie-phy",
5041 .compatible = "qcom,sm8450-qmp-gen4x2-pcie-phy",
5044 .compatible = "qcom,sm8550-qmp-gen3x2-pcie-phy",
5047 .compatible = "qcom,sm8550-qmp-gen4x2-pcie-phy",
5050 .compatible = "qcom,sm8650-qmp-gen3x2-pcie-phy",
5053 .compatible = "qcom,sm8650-qmp-gen4x2-pcie-phy",
5056 .compatible = "qcom,x1e80100-qmp-gen3x2-pcie-phy",
5059 .compatible = "qcom,x1e80100-qmp-gen4x2-pcie-phy",
5062 .compatible = "qcom,x1e80100-qmp-gen4x4-pcie-phy",
5065 .compatible = "qcom,x1e80100-qmp-gen4x8-pcie-phy",
5068 .compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
5078 .name = "qcom-qmp-pcie-phy",