Lines Matching +full:100 +full:base +full:- +full:tx
1 // SPDX-License-Identifier: GPL-2.0-only
16 #include "phy-airoha-pcie-regs.h"
21 /* PCIe-PHY initialization time in ms needed by the hw to complete */
31 * struct airoha_pcie_phy - PCIe phy driver main structure
34 * @csr_2l: Analogic lane IO mapped register base address
35 * @pma0: IO mapped register base address of PMA0-PCIe
36 * @pma1: IO mapped register base address of PMA1-PCIe
37 * @p0_xr_dtime: IO mapped register base address of port0 Tx-Rx detection time
38 * @p1_xr_dtime: IO mapped register base address of port1 Tx-Rx detection time
39 * @rx_aeq: IO mapped register base address of Rx AEQ training
84 airoha_phy_clear_bits((pcie_phy)->csr_2l + (reg), (mask))
86 airoha_phy_set_bits((pcie_phy)->csr_2l + (reg), (mask))
88 airoha_phy_update_field((pcie_phy)->csr_2l + (reg), (mask), (val))
90 airoha_phy_clear_bits((pcie_phy)->pma0 + (reg), (mask))
92 airoha_phy_clear_bits((pcie_phy)->pma1 + (reg), (mask))
94 airoha_phy_set_bits((pcie_phy)->pma0 + (reg), (mask))
96 airoha_phy_set_bits((pcie_phy)->pma1 + (reg), (mask))
98 airoha_phy_update_field((pcie_phy)->pma0 + (reg), (mask), (val))
100 airoha_phy_update_field((pcie_phy)->pma1 + (reg), (mask), (val))
116 fl_out_target - 100); in airoha_phy_init_lane0_rx_fw_pre_calib()
119 fl_out_target + 100); in airoha_phy_init_lane0_rx_fw_pre_calib()
126 fl_out_target - 100); in airoha_phy_init_lane0_rx_fw_pre_calib()
129 fl_out_target + 100); in airoha_phy_init_lane0_rx_fw_pre_calib()
179 readl(pcie_phy->pma0 + in airoha_phy_init_lane0_rx_fw_pre_calib()
185 for (i = LEQ_LEN_CTRL_MAX_VAL; i >= 0; i--) { in airoha_phy_init_lane0_rx_fw_pre_calib()
200 readl(pcie_phy->pma0 + in airoha_phy_init_lane0_rx_fw_pre_calib()
225 val = readl(pcie_phy->pma0 + REG_PCIE_PMA_RO_RX_FREQDET); in airoha_phy_init_lane0_rx_fw_pre_calib()
277 fl_out_target - 100); in airoha_phy_init_lane1_rx_fw_pre_calib()
280 fl_out_target + 100); in airoha_phy_init_lane1_rx_fw_pre_calib()
287 fl_out_target - 100); in airoha_phy_init_lane1_rx_fw_pre_calib()
290 fl_out_target + 100); in airoha_phy_init_lane1_rx_fw_pre_calib()
339 readl(pcie_phy->pma1 + in airoha_phy_init_lane1_rx_fw_pre_calib()
345 for (i = LEQ_LEN_CTRL_MAX_VAL; i >= 0; i--) { in airoha_phy_init_lane1_rx_fw_pre_calib()
360 readl(pcie_phy->pma1 + in airoha_phy_init_lane1_rx_fw_pre_calib()
385 val = readl(pcie_phy->pma1 + REG_PCIE_PMA_RO_RX_FREQDET); in airoha_phy_init_lane1_rx_fw_pre_calib()
427 writel(0xcccbcccb, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_21); in airoha_pcie_phy_init_default()
428 writel(0xcccb, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_22); in airoha_pcie_phy_init_default()
429 writel(0xcccbcccb, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_21); in airoha_pcie_phy_init_default()
430 writel(0xcccb, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_22); in airoha_pcie_phy_init_default()
481 writel(0x2a00090b, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_17); in airoha_pcie_phy_init_rx()
482 writel(0x2a00090b, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_17); in airoha_pcie_phy_init_rx()
515 writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_JCPLL_SSC_DELTA1); in airoha_pcie_phy_init_jcpll()
649 writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_TXPLL_SSC_DELTA1); in airoha_pcie_phy_txpll()
686 writel(0x0, pcie_phy->csr_2l + REG_CSR_2L_TXPLL_SSC_DELTA1); in airoha_pcie_phy_txpll()
818 usleep_range(100, 200); in airoha_pcie_phy_set_rxlan0_signal_detect()
870 usleep_range(100, 200); in airoha_pcie_phy_set_rxlan1_signal_detect()
1036 writel(0x804000, pcie_phy->pma0 + REG_PCIE_PMA_DIG_RESERVE_27); in airoha_pcie_phy_set_rx_mode()
1060 writel(0x804000, pcie_phy->pma1 + REG_PCIE_PMA_DIG_RESERVE_27); in airoha_pcie_phy_set_rx_mode()
1096 usleep_range(100, 200); in airoha_pcie_phy_load_kflow()
1103 * airoha_pcie_phy_init() - Initialize the phy
1115 /* Setup Tx-Rx detection time */ in airoha_pcie_phy_init()
1121 writel(val, pcie_phy->p0_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44); in airoha_pcie_phy_init()
1122 writel(val, pcie_phy->p1_xr_dtime + REG_PCIE_PEXTP_DIG_GLB44); in airoha_pcie_phy_init()
1126 writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P0); in airoha_pcie_phy_init()
1127 writel(val, pcie_phy->rx_aeq + REG_PCIE_PEXTP_DIG_LN_RX30_P1); in airoha_pcie_phy_init()
1129 /* enable load FLL-K flow */ in airoha_pcie_phy_init()
1139 usleep_range(100, 200); in airoha_pcie_phy_init()
1147 /* TX PLL settings */ in airoha_pcie_phy_init()
1155 usleep_range(100, 200); in airoha_pcie_phy_init()
1164 usleep_range(100, 200); in airoha_pcie_phy_init()
1167 /* TX FLOW */ in airoha_pcie_phy_init()
1170 usleep_range(100, 200); in airoha_pcie_phy_init()
1173 /* Load K-Flow */ in airoha_pcie_phy_init()
1180 usleep_range(100, 200); in airoha_pcie_phy_init()
1218 struct device *dev = &pdev->dev; in airoha_pcie_phy_probe()
1223 return -ENOMEM; in airoha_pcie_phy_probe()
1225 pcie_phy->csr_2l = devm_platform_ioremap_resource_byname(pdev, "csr-2l"); in airoha_pcie_phy_probe()
1226 if (IS_ERR(pcie_phy->csr_2l)) in airoha_pcie_phy_probe()
1227 return dev_err_probe(dev, PTR_ERR(pcie_phy->csr_2l), in airoha_pcie_phy_probe()
1228 "Failed to map phy-csr-2l base\n"); in airoha_pcie_phy_probe()
1230 pcie_phy->pma0 = devm_platform_ioremap_resource_byname(pdev, "pma0"); in airoha_pcie_phy_probe()
1231 if (IS_ERR(pcie_phy->pma0)) in airoha_pcie_phy_probe()
1232 return dev_err_probe(dev, PTR_ERR(pcie_phy->pma0), in airoha_pcie_phy_probe()
1233 "Failed to map phy-pma0 base\n"); in airoha_pcie_phy_probe()
1235 pcie_phy->pma1 = devm_platform_ioremap_resource_byname(pdev, "pma1"); in airoha_pcie_phy_probe()
1236 if (IS_ERR(pcie_phy->pma1)) in airoha_pcie_phy_probe()
1237 return dev_err_probe(dev, PTR_ERR(pcie_phy->pma1), in airoha_pcie_phy_probe()
1238 "Failed to map phy-pma1 base\n"); in airoha_pcie_phy_probe()
1240 pcie_phy->phy = devm_phy_create(dev, dev->of_node, &airoha_pcie_phy_ops); in airoha_pcie_phy_probe()
1241 if (IS_ERR(pcie_phy->phy)) in airoha_pcie_phy_probe()
1242 return dev_err_probe(dev, PTR_ERR(pcie_phy->phy), in airoha_pcie_phy_probe()
1245 pcie_phy->p0_xr_dtime = in airoha_pcie_phy_probe()
1246 devm_platform_ioremap_resource_byname(pdev, "p0-xr-dtime"); in airoha_pcie_phy_probe()
1247 if (IS_ERR(pcie_phy->p0_xr_dtime)) in airoha_pcie_phy_probe()
1248 return dev_err_probe(dev, PTR_ERR(pcie_phy->p0_xr_dtime), in airoha_pcie_phy_probe()
1249 "Failed to map P0 Tx-Rx dtime base\n"); in airoha_pcie_phy_probe()
1251 pcie_phy->p1_xr_dtime = in airoha_pcie_phy_probe()
1252 devm_platform_ioremap_resource_byname(pdev, "p1-xr-dtime"); in airoha_pcie_phy_probe()
1253 if (IS_ERR(pcie_phy->p1_xr_dtime)) in airoha_pcie_phy_probe()
1254 return dev_err_probe(dev, PTR_ERR(pcie_phy->p1_xr_dtime), in airoha_pcie_phy_probe()
1255 "Failed to map P1 Tx-Rx dtime base\n"); in airoha_pcie_phy_probe()
1257 pcie_phy->rx_aeq = devm_platform_ioremap_resource_byname(pdev, "rx-aeq"); in airoha_pcie_phy_probe()
1258 if (IS_ERR(pcie_phy->rx_aeq)) in airoha_pcie_phy_probe()
1259 return dev_err_probe(dev, PTR_ERR(pcie_phy->rx_aeq), in airoha_pcie_phy_probe()
1260 "Failed to map Rx AEQ base\n"); in airoha_pcie_phy_probe()
1262 pcie_phy->dev = dev; in airoha_pcie_phy_probe()
1263 phy_set_drvdata(pcie_phy->phy, pcie_phy); in airoha_pcie_phy_probe()
1274 { .compatible = "airoha,en7581-pcie-phy" },
1282 .name = "airoha-pcie-phy",