1 // SPDX-License-Identifier: GPL-2.0
28 #define ONLY_2_4_6			(BIT(2) | BIT(4) | BIT(6))
29 #define ONLY_5_6_7			(BIT(5) | BIT(6) | BIT(7))
45  * per cpu-type PMU abstractions.
48  * implementations, we'll have to introduce per cpu-type tables.
120 	 * but attributes that get stored in hw->config_base.
122 	M1_PMU_CFG_COUNT_USER					= BIT(8),
123 	M1_PMU_CFG_COUNT_KERNEL					= BIT(9),
124 	M1_PMU_CFG_COUNT_HOST					= BIT(10),
125 	M1_PMU_CFG_COUNT_GUEST					= BIT(11),
129  * Per-event affinity table. Most events can be installed on counter
130  * 2-9, but there are a number of exceptions. Note that this table
136 	[M1_PMU_PERFCTR_RETIRE_UOP]				= BIT(7),
137 	[M1_PMU_PERFCTR_CORE_ACTIVE_CYCLE]			= ANY_BUT_0_1 | BIT(0),
138 	[M1_PMU_PERFCTR_INST_ALL]				= BIT(7) | BIT(1),
146 	[M1_PMU_PERFCTR_INST_INT_ST]				= BIT(7),
147 	[M1_PMU_PERFCTR_INST_INT_ALU]				= BIT(7),
150 	[M1_PMU_PERFCTR_INST_SIMD_ALU]				= BIT(7),
151 	[M1_PMU_PERFCTR_INST_LDST]				= BIT(7),
153 	[M1_PMU_PERFCTR_UNKNOWN_9f]				= BIT(7),
182 	[0 ... ARMV8_PMUV3_MAX_COMMON_EVENTS - 1]	= HW_OP_UNSUPPORTED,
198 	return sprintf(page, "event=0x%04llx\n", pmu_attr->id);  in m1_pmu_events_sysfs_show()
215 PMU_FORMAT_ATTR(event, "config:0-7");
276 	u64 val, bit;  in __m1_pmu_enable_counter()  local
280 		bit = BIT(get_bit_offset(index, PMCR0_CNT_ENABLE_0_7));  in __m1_pmu_enable_counter()
283 		bit = BIT(get_bit_offset(index - 8, PMCR0_CNT_ENABLE_8_9));  in __m1_pmu_enable_counter()
292 		val |= bit;  in __m1_pmu_enable_counter()
294 		val &= ~bit;  in __m1_pmu_enable_counter()
311 	u64 val, bit;  in __m1_pmu_enable_counter_interrupt()  local
315 		bit = BIT(get_bit_offset(index, PMCR0_PMI_ENABLE_0_7));  in __m1_pmu_enable_counter_interrupt()
318 		bit = BIT(get_bit_offset(index - 8, PMCR0_PMI_ENABLE_8_9));  in __m1_pmu_enable_counter_interrupt()
327 		val |= bit;  in __m1_pmu_enable_counter_interrupt()
329 		val &= ~bit;  in __m1_pmu_enable_counter_interrupt()
347 	u64 clear, set, user_bit, kernel_bit;  in __m1_pmu_configure_event_filter()  local
351 		user_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL0_0_7));  in __m1_pmu_configure_event_filter()
352 		kernel_bit = BIT(get_bit_offset(index, PMCR1_COUNT_A64_EL1_0_7));  in __m1_pmu_configure_event_filter()
355 		user_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL0_8_9));  in __m1_pmu_configure_event_filter()
356 		kernel_bit = BIT(get_bit_offset(index - 8, PMCR1_COUNT_A64_EL1_8_9));  in __m1_pmu_configure_event_filter()
362 	clear = set = 0;  in __m1_pmu_configure_event_filter()
366 		clear |= user_bit;  in __m1_pmu_configure_event_filter()
371 		clear |= kernel_bit;  in __m1_pmu_configure_event_filter()
374 		sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set);  in __m1_pmu_configure_event_filter()
376 		sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL12, clear, set);  in __m1_pmu_configure_event_filter()
381 	u64 clear = 0, set = 0;  in __m1_pmu_configure_eventsel()  local
388 	 * 2-5, resp. PMESR1 for counters 6-9).  in __m1_pmu_configure_eventsel()
394 		shift = (index - 2) * 8;  in __m1_pmu_configure_eventsel()
395 		clear |= (u64)0xff << shift;  in __m1_pmu_configure_eventsel()
397 		sysreg_clear_set_s(SYS_IMP_APL_PMESR0_EL1, clear, set);  in __m1_pmu_configure_eventsel()
400 		shift = (index - 6) * 8;  in __m1_pmu_configure_eventsel()
401 		clear |= (u64)0xff << shift;  in __m1_pmu_configure_eventsel()
403 		sysreg_clear_set_s(SYS_IMP_APL_PMESR1_EL1, clear, set);  in __m1_pmu_configure_eventsel()
427 	evt = event->hw.config_base & M1_PMU_CFG_EVENT;  in m1_pmu_enable_event()
428 	user = event->hw.config_base & M1_PMU_CFG_COUNT_USER;  in m1_pmu_enable_event()
429 	kernel = event->hw.config_base & M1_PMU_CFG_COUNT_KERNEL;  in m1_pmu_enable_event()
431 	m1_pmu_configure_counter(event->hw.idx, event->hw.config_base);  in m1_pmu_enable_event()
432 	m1_pmu_enable_counter(event->hw.idx);  in m1_pmu_enable_event()
433 	m1_pmu_enable_counter_interrupt(event->hw.idx);  in m1_pmu_enable_event()
439 	m1_pmu_disable_counter_interrupt(event->hw.idx);  in m1_pmu_disable_event()
440 	m1_pmu_disable_counter(event->hw.idx);  in m1_pmu_disable_event()
446 	struct pmu_hw_events *cpuc = this_cpu_ptr(cpu_pmu->hw_events);  in m1_pmu_handle_irq()
461 	cpu_pmu->stop(cpu_pmu);  in m1_pmu_handle_irq()
465 	for_each_set_bit(idx, cpu_pmu->cntr_mask, M1_PMU_NR_COUNTERS) {  in m1_pmu_handle_irq()
466 		struct perf_event *event = cpuc->events[idx];  in m1_pmu_handle_irq()
473 		perf_sample_data_init(&data, 0, event->hw.last_period);  in m1_pmu_handle_irq()
481 	cpu_pmu->start(cpu_pmu);  in m1_pmu_handle_irq()
488 	return m1_pmu_read_hw_counter(event->hw.idx);  in m1_pmu_read_counter()
493 	m1_pmu_write_hw_counter(value, event->hw.idx);  in m1_pmu_write_counter()
500 	unsigned long evtype = event->hw.config_base & M1_PMU_CFG_EVENT;  in m1_pmu_get_event_idx()
513 		if (!test_and_set_bit(idx, cpuc->used_mask))  in m1_pmu_get_event_idx()
517 	return -EAGAIN;  in m1_pmu_get_event_idx()
523 	clear_bit(event->hw.idx, cpuc->used_mask);  in m1_pmu_clear_event_idx()
550 	 * Although the counters are 48bit wide, bit 47 is what  in m1_pmu_map_event()
552 	 * being 47bit wide to mimick the behaviour of the ARM PMU.  in m1_pmu_map_event()
554 	event->hw.flags |= ARMPMU_EVT_47BIT;  in m1_pmu_map_event()
561 	 * Same deal as the above, except that M2 has 64bit counters.  in m2_pmu_map_event()
565 	event->hw.flags |= ARMPMU_EVT_63BIT;  in m2_pmu_map_event()
576 	return m1_event == HW_OP_UNSUPPORTED ? -EOPNOTSUPP : m1_event;  in m1_pmu_map_pmuv3_event()
585 			set_bit(event, pmu->pmceid_bitmap);  in m1_pmu_init_pmceid()
609 	if (!attr->exclude_guest && !is_kernel_in_hyp_mode()) {  in m1_pmu_set_event_filter()
611 		return -EOPNOTSUPP;  in m1_pmu_set_event_filter()
613 	if (!attr->exclude_kernel)  in m1_pmu_set_event_filter()
615 	if (!attr->exclude_user)  in m1_pmu_set_event_filter()
617 	if (!attr->exclude_host)  in m1_pmu_set_event_filter()
619 	if (!attr->exclude_guest)  in m1_pmu_set_event_filter()
622 	event->config_base = config_base;  in m1_pmu_set_event_filter()
629 	cpu_pmu->handle_irq	  = m1_pmu_handle_irq;  in m1_pmu_init()
630 	cpu_pmu->enable		  = m1_pmu_enable_event;  in m1_pmu_init()
631 	cpu_pmu->disable	  = m1_pmu_disable_event;  in m1_pmu_init()
632 	cpu_pmu->read_counter	  = m1_pmu_read_counter;  in m1_pmu_init()
633 	cpu_pmu->write_counter	  = m1_pmu_write_counter;  in m1_pmu_init()
634 	cpu_pmu->get_event_idx	  = m1_pmu_get_event_idx;  in m1_pmu_init()
635 	cpu_pmu->clear_event_idx  = m1_pmu_clear_event_idx;  in m1_pmu_init()
636 	cpu_pmu->start		  = m1_pmu_start;  in m1_pmu_init()
637 	cpu_pmu->stop		  = m1_pmu_stop;  in m1_pmu_init()
640 		cpu_pmu->map_event = m1_pmu_map_event;  in m1_pmu_init()
642 		cpu_pmu->map_event = m2_pmu_map_event;  in m1_pmu_init()
644 		return WARN_ON(-EINVAL);  in m1_pmu_init()
646 	cpu_pmu->reset		  = m1_pmu_reset;  in m1_pmu_init()
647 	cpu_pmu->set_event_filter = m1_pmu_set_event_filter;  in m1_pmu_init()
649 	cpu_pmu->map_pmuv3_event  = m1_pmu_map_pmuv3_event;  in m1_pmu_init()
652 	bitmap_set(cpu_pmu->cntr_mask, 0, M1_PMU_NR_COUNTERS);  in m1_pmu_init()
653 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_EVENTS] = &m1_pmu_events_attr_group;  in m1_pmu_init()
654 	cpu_pmu->attr_groups[ARMPMU_ATTR_GROUP_FORMATS] = &m1_pmu_format_attr_group;  in m1_pmu_init()
661 	cpu_pmu->name = "apple_icestorm_pmu";  in m1_pmu_ice_init()
667 	cpu_pmu->name = "apple_firestorm_pmu";  in m1_pmu_fire_init()
673 	cpu_pmu->name = "apple_avalanche_pmu";  in m2_pmu_avalanche_init()
679 	cpu_pmu->name = "apple_blizzard_pmu";  in m2_pmu_blizzard_init()
684 	{ .compatible = "apple,avalanche-pmu",	.data = m2_pmu_avalanche_init, },
685 	{ .compatible = "apple,blizzard-pmu",	.data = m2_pmu_blizzard_init, },
686 	{ .compatible = "apple,icestorm-pmu",	.data = m1_pmu_ice_init, },
687 	{ .compatible = "apple,firestorm-pmu",	.data = m1_pmu_fire_init, },
699 		.name			= "apple-m1-cpu-pmu",