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1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright 1993 -- 1997 Drew Eckhardt, Frederic Potter,
6 * David Mosberger-Tang
8 * Copyright 1997 -- 2000 Martin Mares <mj@ucw.cz>
43 int isa_dma_bridge_buggy;
47 int pci_pci_problems;
50 unsigned int pci_pm_d3hot_delay;
82 unsigned int delay_ms = max(dev->d3hot_delay, pci_pm_d3hot_delay); in pci_dev_d3_sleep()
83 unsigned int upper; in pci_dev_d3_sleep()
95 return dev->reset_methods[0] != 0; in pci_reset_supported()
99 int pci_domains_supported = 1;
114 * pci=hpmmiosize=nnM overrides non-prefetchable MMIO size,
125 /* PCIe MPS/MRRS strategy; can be overridden by kernel command-line param */
139 * The default CLS is used if arch didn't set CLS explicitly and not
142 * measured in 32-bit words, not bytes.
151 unsigned int pcibios_max_latency = 255;
173 static int __init pcie_port_pm_setup(char *str) in pcie_port_pm_setup()
184 * pci_bus_max_busnr - returns maximum PCI bus number of given bus' children
188 * including the given PCI bus and its list of child PCI buses.
195 max = bus->busn_res.end; in pci_bus_max_busnr()
196 list_for_each_entry(tmp, &bus->children, node) { in pci_bus_max_busnr()
206 * pci_status_get_and_clear_errors - return and clear error bits in PCI_STATUS
209 * Returns error bits set in PCI_STATUS and clears them.
211 int pci_status_get_and_clear_errors(struct pci_dev *pdev) in pci_status_get_and_clear_errors()
214 int ret; in pci_status_get_and_clear_errors()
218 return -EIO; in pci_status_get_and_clear_errors()
229 static void __iomem *__pci_ioremap_resource(struct pci_dev *pdev, int bar, in __pci_ioremap_resource()
232 struct resource *res = &pdev->resource[bar]; in __pci_ioremap_resource()
233 resource_size_t start = res->start; in __pci_ioremap_resource()
239 if (res->flags & IORESOURCE_UNSET || !(res->flags & IORESOURCE_MEM)) { in __pci_ioremap_resource()
250 void __iomem *pci_ioremap_bar(struct pci_dev *pdev, int bar) in pci_ioremap_bar()
256 void __iomem *pci_ioremap_wc_bar(struct pci_dev *pdev, int bar) in pci_ioremap_wc_bar()
264 * pci_dev_str_match_path - test if a path string matches a device
275 * A path for a device can be obtained using 'lspci -t'. Using a path
277 * device and function address.
279 * Returns 1 if the string matches the device, 0 if it does not and
282 static int pci_dev_str_match_path(struct pci_dev *dev, const char *path, in pci_dev_str_match_path()
285 int ret; in pci_dev_str_match_path()
286 unsigned int seg, bus, slot, func; in pci_dev_str_match_path()
292 wpath = kmemdup_nul(path, *endptr - path, GFP_ATOMIC); in pci_dev_str_match_path()
294 return -ENOMEM; in pci_dev_str_match_path()
302 ret = -EINVAL; in pci_dev_str_match_path()
306 if (dev->devfn != PCI_DEVFN(slot, func)) { in pci_dev_str_match_path()
315 * and so on. in pci_dev_str_match_path()
332 ret = -EINVAL; in pci_dev_str_match_path()
337 ret = (seg == pci_domain_nr(dev->bus) && in pci_dev_str_match_path()
338 bus == dev->bus->number && in pci_dev_str_match_path()
339 dev->devfn == PCI_DEVFN(slot, func)); in pci_dev_str_match_path()
347 * pci_dev_str_match - test if a string matches a device
364 * through the use of 'lspci -t'.
369 * in-kernel code that uses PCI_ANY_ID which is ~0; this is for
370 * legacy reasons and convenience so users don't have to specify
373 * Returns 1 if the string matches the device, 0 if it does not and
376 static int pci_dev_str_match(struct pci_dev *dev, const char *p, in pci_dev_str_match()
379 int ret; in pci_dev_str_match()
380 int count; in pci_dev_str_match()
391 return -EINVAL; in pci_dev_str_match()
399 if ((!vendor || vendor == dev->vendor) && in pci_dev_str_match()
400 (!device || device == dev->device) && in pci_dev_str_match()
402 subsystem_vendor == dev->subsystem_vendor) && in pci_dev_str_match()
404 subsystem_device == dev->subsystem_device)) in pci_dev_str_match()
426 static u8 __pci_find_next_cap_ttl(struct pci_bus *bus, unsigned int devfn, in __pci_find_next_cap_ttl()
427 u8 pos, int cap, int *ttl) in __pci_find_next_cap_ttl()
434 while ((*ttl)--) { in __pci_find_next_cap_ttl()
450 static u8 __pci_find_next_cap(struct pci_bus *bus, unsigned int devfn, in __pci_find_next_cap()
451 u8 pos, int cap) in __pci_find_next_cap()
453 int ttl = PCI_FIND_CAP_TTL; in __pci_find_next_cap()
458 u8 pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap) in pci_find_next_capability()
460 return __pci_find_next_cap(dev->bus, dev->devfn, in pci_find_next_capability()
466 unsigned int devfn, u8 hdr_type) in __pci_bus_find_cap_start()
486 * pci_find_capability - query for devices' capabilities
493 * support it. Possible values for @cap include:
501 * %PCI_CAP_ID_PCIX PCI-X
504 u8 pci_find_capability(struct pci_dev *dev, int cap) in pci_find_capability()
508 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_capability()
510 pos = __pci_find_next_cap(dev->bus, dev->devfn, pos, cap); in pci_find_capability()
517 * pci_bus_find_capability - query for devices' capabilities
529 u8 pci_bus_find_capability(struct pci_bus *bus, unsigned int devfn, int cap) in pci_bus_find_capability()
544 * pci_find_next_ext_capability - Find an extended capability
552 * vendor-specific capability, and this provides a way to find them all.
554 u16 pci_find_next_ext_capability(struct pci_dev *dev, u16 start, int cap) in pci_find_next_ext_capability()
557 int ttl; in pci_find_next_ext_capability()
561 ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8; in pci_find_next_ext_capability()
563 if (dev->cfg_size <= PCI_CFG_SPACE_SIZE) in pci_find_next_ext_capability()
574 * cap version and next pointer all being 0. in pci_find_next_ext_capability()
579 while (ttl-- > 0) { in pci_find_next_ext_capability()
596 * pci_find_ext_capability - Find an extended capability
602 * not support it. Possible values for @cap include:
609 u16 pci_find_ext_capability(struct pci_dev *dev, int cap) in pci_find_ext_capability()
616 * pci_get_dsn - Read and return the 8-byte Device Serial Number
619 * Looks up the PCI_EXT_CAP_ID_DSN and reads the 8 bytes of the Device Serial
628 int pos; in pci_get_dsn()
637 * the lower half, and the second dword is the upper half. in pci_get_dsn()
649 static u8 __pci_find_next_ht_cap(struct pci_dev *dev, u8 pos, int ht_cap) in __pci_find_next_ht_cap()
651 int rc, ttl = PCI_FIND_CAP_TTL; in __pci_find_next_ht_cap()
659 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, pos, in __pci_find_next_ht_cap()
669 pos = __pci_find_next_cap_ttl(dev->bus, dev->devfn, in __pci_find_next_ht_cap()
678 * pci_find_next_ht_capability - query a device's HyperTransport capabilities
690 u8 pci_find_next_ht_capability(struct pci_dev *dev, u8 pos, int ht_cap) in pci_find_next_ht_capability()
697 * pci_find_ht_capability - query a device's HyperTransport capabilities
707 u8 pci_find_ht_capability(struct pci_dev *dev, int ht_cap) in pci_find_ht_capability()
711 pos = __pci_bus_find_cap_start(dev->bus, dev->devfn, dev->hdr_type); in pci_find_ht_capability()
720 * pci_find_vsec_capability - Find a vendor-specific extended capability
723 * @cap: Vendor-specific capability ID
729 u16 pci_find_vsec_capability(struct pci_dev *dev, u16 vendor, int cap) in pci_find_vsec_capability()
733 int ret; in pci_find_vsec_capability()
735 if (vendor != dev->vendor) in pci_find_vsec_capability()
753 * pci_find_dvsec_capability - Find DVSEC for vendor
756 * @dvsec: Designated Vendor-specific capability ID
758 * If DVSEC has Vendor ID @vendor and DVSEC ID @dvsec return the capability
763 int pos; in pci_find_dvsec_capability()
785 * pci_find_parent_resource - return resource region of parent bus of given
796 const struct pci_bus *bus = dev->bus; in pci_find_parent_resource()
808 if (r->flags & IORESOURCE_PREFETCH && in pci_find_parent_resource()
809 !(res->flags & IORESOURCE_PREFETCH)) in pci_find_parent_resource()
814 * be both a positively-decoded aperture and a in pci_find_parent_resource()
815 * subtractively-decoded region that contain the BAR. in pci_find_parent_resource()
816 * We want the positively-decoded one, so this depends in pci_find_parent_resource()
828 * pci_find_resource - Return matching PCI device resource
832 * Goes over standard PCI resources (BARs) and checks if the given resource
838 int i; in pci_find_resource()
841 struct resource *r = &dev->resource[i]; in pci_find_resource()
843 if (r->start && resource_contains(r, res)) in pci_find_resource()
852 * pci_resource_name - Return the name of the PCI resource
858 const char *pci_resource_name(struct pci_dev *dev, unsigned int i) in pci_resource_name()
901 if (dev->hdr_type == PCI_HEADER_TYPE_CARDBUS && in pci_resource_name()
912 * pci_wait_for_pending - wait for @mask bit(s) to clear in status word @pos
919 int pci_wait_for_pending(struct pci_dev *dev, int pos, u16 mask) in pci_wait_for_pending()
921 int i; in pci_wait_for_pending()
927 msleep((1 << (i - 1)) * 100); in pci_wait_for_pending()
937 static int pci_acs_enable;
940 * pci_request_acs - ask for ACS to be enabled if supported
962 int ret = 0; in __pci_config_acs()
972 int end; in __pci_config_acs()
975 end = delimit - p - 1; in __pci_config_acs()
979 while (end > -1) { in __pci_config_acs()
983 end--; in __pci_config_acs()
988 end--; in __pci_config_acs()
991 end--; in __pci_config_acs()
1034 pci_dbg(dev, "ACS control = %#06x\n", caps->ctrl); in __pci_config_acs()
1035 pci_dbg(dev, "ACS fw_ctrl = %#06x\n", caps->fw_ctrl); in __pci_config_acs()
1039 * and apply flags for all the mask bits that are 1. in __pci_config_acs()
1041 caps->ctrl = (caps->fw_ctrl & ~mask) | (flags & mask); in __pci_config_acs()
1043 pci_info(dev, "Configured ACS to %#06x\n", caps->ctrl); in __pci_config_acs()
1047 * pci_std_enable_acs - enable ACS on devices using standard ACS capabilities
1054 caps->ctrl |= (caps->cap & PCI_ACS_SV); in pci_std_enable_acs()
1057 caps->ctrl |= (caps->cap & PCI_ACS_RR); in pci_std_enable_acs()
1060 caps->ctrl |= (caps->cap & PCI_ACS_CR); in pci_std_enable_acs()
1063 caps->ctrl |= (caps->cap & PCI_ACS_UF); in pci_std_enable_acs()
1065 /* Enable Translation Blocking for external devices and noats */ in pci_std_enable_acs()
1066 if (pci_ats_disabled() || dev->external_facing || dev->untrusted) in pci_std_enable_acs()
1067 caps->ctrl |= (caps->cap & PCI_ACS_TB); in pci_std_enable_acs()
1071 * pci_enable_acs - enable ACS if hardware support it
1078 int pos; in pci_enable_acs()
1086 pos = dev->acs_cap; in pci_enable_acs()
1110 * pci_restore_bars - restore a device's BAR values (e.g. after wake-up)
1113 * Restore the BAR values for a given device, so as to make it
1118 int i; in pci_restore_bars()
1132 static inline int platform_pci_set_power_state(struct pci_dev *dev, in platform_pci_set_power_state()
1163 static inline int platform_pci_set_wakeup(struct pci_dev *dev, bool enable) in platform_pci_set_wakeup()
1188 * pci_update_current_state - Read power state of given device and cache it
1202 dev->current_state = PCI_D3cold; in pci_update_current_state()
1203 } else if (dev->pm_cap) { in pci_update_current_state()
1206 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_update_current_state()
1208 dev->current_state = PCI_D3cold; in pci_update_current_state()
1211 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_update_current_state()
1213 dev->current_state = state; in pci_update_current_state()
1218 * pci_refresh_power_state - Refresh the given device's power state data
1221 * Ask the platform to refresh the devices power state information and invoke
1227 pci_update_current_state(dev, dev->current_state); in pci_refresh_power_state()
1231 * pci_platform_power_transition - Use platform to change device power state
1235 int pci_platform_power_transition(struct pci_dev *dev, pci_power_t state) in pci_platform_power_transition()
1237 int error; in pci_platform_power_transition()
1242 else if (!dev->pm_cap) /* Fall back to PCI_D0 */ in pci_platform_power_transition()
1243 dev->current_state = PCI_D0; in pci_platform_power_transition()
1249 static int pci_resume_one(struct pci_dev *pci_dev, void *ign) in pci_resume_one()
1251 pm_request_resume(&pci_dev->dev); in pci_resume_one()
1256 * pci_resume_bus - Walk given bus and runtime resume devices on it
1265 static int pci_dev_wait(struct pci_dev *dev, char *reset_type, int timeout) in pci_dev_wait()
1267 int delay = 1; in pci_dev_wait()
1288 * Vendor ID until we get non-RRS status. in pci_dev_wait()
1295 * ID for VFs and non-existent devices also returns ~0, so read the in pci_dev_wait()
1303 return -ENOTTY; in pci_dev_wait()
1306 if (root && root->config_rrs_sv) { in pci_dev_wait()
1318 delay - 1, reset_type); in pci_dev_wait()
1319 return -ENOTTY; in pci_dev_wait()
1331 delay - 1, reset_type); in pci_dev_wait()
1339 pci_info(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1342 pci_dbg(dev, "ready %dms after %s\n", delay - 1, in pci_dev_wait()
1349 * pci_power_up - Put the given device into D0
1357 * put the device in D0 via non-PCI means.
1359 int pci_power_up(struct pci_dev *dev) in pci_power_up()
1367 if (!dev->pm_cap) { in pci_power_up()
1370 dev->current_state = PCI_D0; in pci_power_up()
1372 dev->current_state = state; in pci_power_up()
1374 return -EIO; in pci_power_up()
1377 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_power_up()
1380 pci_power_name(dev->current_state)); in pci_power_up()
1381 dev->current_state = PCI_D3cold; in pci_power_up()
1382 return -EIO; in pci_power_up()
1387 need_restore = (state == PCI_D3hot || dev->current_state >= PCI_D3hot) && in pci_power_up()
1395 * PME_En, and sets PowerState to 0. in pci_power_up()
1397 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, 0); in pci_power_up()
1406 dev->current_state = PCI_D0; in pci_power_up()
1414 * pci_set_full_power_state - Put a PCI device into D0 and update its state
1419 * to confirm the state change, restore its BARs if they might be lost and
1426 static int pci_set_full_power_state(struct pci_dev *dev, bool locked) in pci_set_full_power_state()
1429 int ret; in pci_set_full_power_state()
1433 if (dev->current_state == PCI_D0) in pci_set_full_power_state()
1439 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_full_power_state()
1440 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_full_power_state()
1441 if (dev->current_state != PCI_D0) { in pci_set_full_power_state()
1443 pci_power_name(dev->current_state)); in pci_set_full_power_state()
1450 * For example, at least some versions of the 3c905B and the in pci_set_full_power_state()
1461 if (dev->bus->self) in pci_set_full_power_state()
1462 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_full_power_state()
1468 * __pci_dev_set_current_state - Set current state of a PCI device
1472 static int __pci_dev_set_current_state(struct pci_dev *dev, void *data) in __pci_dev_set_current_state()
1476 dev->current_state = state; in __pci_dev_set_current_state()
1481 * pci_bus_set_current_state - Walk given bus and set current state of devices
1503 * pci_set_low_power_state - Put a PCI device into a low-power state.
1508 * Use the device's PCI_PM_CTRL register to put it into a low-power state.
1511 * -EINVAL if the requested state is invalid.
1512 * -EIO if device does not support PCI PM or its PM capabilities register has a
1517 static int pci_set_low_power_state(struct pci_dev *dev, pci_power_t state, bool locked) in pci_set_low_power_state()
1521 if (!dev->pm_cap) in pci_set_low_power_state()
1522 return -EIO; in pci_set_low_power_state()
1526 * we're already in a low-power state, we can only go deeper. E.g., in pci_set_low_power_state()
1530 if (dev->current_state <= PCI_D3cold && dev->current_state > state) { in pci_set_low_power_state()
1532 pci_power_name(dev->current_state), in pci_set_low_power_state()
1534 return -EINVAL; in pci_set_low_power_state()
1538 if ((state == PCI_D1 && !dev->d1_support) in pci_set_low_power_state()
1539 || (state == PCI_D2 && !dev->d2_support)) in pci_set_low_power_state()
1540 return -EIO; in pci_set_low_power_state()
1542 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1545 pci_power_name(dev->current_state), in pci_set_low_power_state()
1547 dev->current_state = PCI_D3cold; in pci_set_low_power_state()
1548 return -EIO; in pci_set_low_power_state()
1555 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_set_low_power_state()
1563 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_set_low_power_state()
1564 dev->current_state = pmcsr & PCI_PM_CTRL_STATE_MASK; in pci_set_low_power_state()
1565 if (dev->current_state != state) in pci_set_low_power_state()
1567 pci_power_name(dev->current_state), in pci_set_low_power_state()
1570 if (dev->bus->self) in pci_set_low_power_state()
1571 pcie_aspm_pm_state_change(dev->bus->self, locked); in pci_set_low_power_state()
1576 static int __pci_set_power_state(struct pci_dev *dev, pci_power_t state, bool locked) in __pci_set_power_state()
1578 int error; in __pci_set_power_state()
1596 if (dev->current_state == state) in __pci_set_power_state()
1606 if (state >= PCI_D3hot && (dev->dev_flags & PCI_DEV_FLAGS_NO_D3)) in __pci_set_power_state()
1620 if (dev->current_state == PCI_D3cold) in __pci_set_power_state()
1621 __pci_bus_set_current_state(dev->subordinate, PCI_D3cold, locked); in __pci_set_power_state()
1633 * pci_set_power_state - Set the power state of a PCI device
1637 * Transition a device to a new power state, using the platform firmware and/or
1641 * -EINVAL if the requested state is invalid.
1642 * -EIO if device does not support PCI PM or its PM capabilities register has a
1644 * 0 if the transition is to D1 or D2 but D1 and D2 are not supported.
1649 int pci_set_power_state(struct pci_dev *dev, pci_power_t state) in pci_set_power_state()
1655 int pci_set_power_state_locked(struct pci_dev *dev, pci_power_t state) in pci_set_power_state_locked()
1670 hlist_for_each_entry(tmp, &pci_dev->saved_cap_space, next) { in _pci_find_saved_cap()
1671 if (tmp->cap.cap_extended == extended && tmp->cap.cap_nr == cap) in _pci_find_saved_cap()
1687 static int pci_save_pcie_state(struct pci_dev *dev) in pci_save_pcie_state()
1689 int i = 0; in pci_save_pcie_state()
1699 return -ENOMEM; in pci_save_pcie_state()
1702 cap = (u16 *)&save_state->cap.data[0]; in pci_save_pcie_state()
1719 int i = 0; in pci_restore_pcie_state()
1736 * Check and re-configure the bit here before restoring device. in pci_restore_pcie_state()
1741 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcie_state()
1751 static int pci_save_pcix_state(struct pci_dev *dev) in pci_save_pcix_state()
1753 int pos; in pci_save_pcix_state()
1763 return -ENOMEM; in pci_save_pcix_state()
1767 (u16 *)save_state->cap.data); in pci_save_pcix_state()
1774 int i = 0, pos; in pci_restore_pcix_state()
1782 cap = (u16 *)&save_state->cap.data[0]; in pci_restore_pcix_state()
1788 * pci_save_state - save the PCI configuration space of a device before
1792 int pci_save_state(struct pci_dev *dev) in pci_save_state()
1794 int i; in pci_save_state()
1797 pci_read_config_dword(dev, i * 4, &dev->saved_config_space[i]); in pci_save_state()
1799 i * 4, dev->saved_config_space[i]); in pci_save_state()
1801 dev->state_saved = true; in pci_save_state()
1819 static void pci_restore_config_dword(struct pci_dev *pdev, int offset, in pci_restore_config_dword()
1820 u32 saved_val, int retry, bool force) in pci_restore_config_dword()
1829 pci_dbg(pdev, "restore config %#04x: %#010x -> %#010x\n", in pci_restore_config_dword()
1832 if (retry-- <= 0) in pci_restore_config_dword()
1844 int start, int end, int retry, in pci_restore_config_space_range()
1847 int index; in pci_restore_config_space_range()
1849 for (index = end; index >= start; index--) in pci_restore_config_space_range()
1851 pdev->saved_config_space[index], in pci_restore_config_space_range()
1857 if (pdev->hdr_type == PCI_HEADER_TYPE_NORMAL) { in pci_restore_config_space()
1862 } else if (pdev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_restore_config_space()
1879 unsigned int pos, nbars, i; in pci_restore_rebar_state()
1882 pos = pdev->rebar_cap; in pci_restore_rebar_state()
1891 int bar_idx, size; in pci_restore_rebar_state()
1904 * pci_restore_state - Restore the saved state of a PCI device
1909 if (!dev->state_saved) in pci_restore_state()
1930 /* Restore ACS and IOV configuration state */ in pci_restore_state()
1934 dev->state_saved = false; in pci_restore_state()
1944 * pci_store_saved_state - Allocate and return an opaque struct containing
1957 if (!dev->state_saved) in pci_store_saved_state()
1962 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) in pci_store_saved_state()
1963 size += sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1969 memcpy(state->config_space, dev->saved_config_space, in pci_store_saved_state()
1970 sizeof(state->config_space)); in pci_store_saved_state()
1972 cap = state->cap; in pci_store_saved_state()
1973 hlist_for_each_entry(tmp, &dev->saved_cap_space, next) { in pci_store_saved_state()
1974 size_t len = sizeof(struct pci_cap_saved_data) + tmp->cap.size; in pci_store_saved_state()
1975 memcpy(cap, &tmp->cap, len); in pci_store_saved_state()
1985 * pci_load_saved_state - Reload the provided save state into struct pci_dev.
1989 int pci_load_saved_state(struct pci_dev *dev, in pci_load_saved_state()
1994 dev->state_saved = false; in pci_load_saved_state()
1999 memcpy(dev->saved_config_space, state->config_space, in pci_load_saved_state()
2000 sizeof(state->config_space)); in pci_load_saved_state()
2002 cap = state->cap; in pci_load_saved_state()
2003 while (cap->size) { in pci_load_saved_state()
2006 tmp = _pci_find_saved_cap(dev, cap->cap_nr, cap->cap_extended); in pci_load_saved_state()
2007 if (!tmp || tmp->cap.size != cap->size) in pci_load_saved_state()
2008 return -EINVAL; in pci_load_saved_state()
2010 memcpy(tmp->cap.data, cap->data, tmp->cap.size); in pci_load_saved_state()
2012 sizeof(struct pci_cap_saved_data) + cap->size); in pci_load_saved_state()
2015 dev->state_saved = true; in pci_load_saved_state()
2021 * pci_load_and_free_saved_state - Reload the save state pointed to by state,
2022 * and free the memory allocated for it.
2026 int pci_load_and_free_saved_state(struct pci_dev *dev, in pci_load_and_free_saved_state()
2029 int ret = pci_load_saved_state(dev, *state); in pci_load_and_free_saved_state()
2036 int __weak pcibios_enable_device(struct pci_dev *dev, int bars) in pcibios_enable_device()
2041 static int pci_host_bridge_enable_device(struct pci_dev *dev) in pci_host_bridge_enable_device()
2043 struct pci_host_bridge *host_bridge = pci_find_host_bridge(dev->bus); in pci_host_bridge_enable_device()
2044 int err; in pci_host_bridge_enable_device()
2046 if (host_bridge && host_bridge->enable_device) { in pci_host_bridge_enable_device()
2047 err = host_bridge->enable_device(host_bridge, dev); in pci_host_bridge_enable_device()
2057 struct pci_host_bridge *host_bridge = pci_find_host_bridge(dev->bus); in pci_host_bridge_disable_device()
2059 if (host_bridge && host_bridge->disable_device) in pci_host_bridge_disable_device()
2060 host_bridge->disable_device(host_bridge, dev); in pci_host_bridge_disable_device()
2063 static int do_pci_enable_device(struct pci_dev *dev, int bars) in do_pci_enable_device()
2065 int err; in do_pci_enable_device()
2071 if (err < 0 && err != -EIO) in do_pci_enable_device()
2087 if (dev->msi_enabled || dev->msix_enabled) in do_pci_enable_device()
2108 * pci_reenable_device - Resume abandoned device
2111 * NOTE: This function is a backend of pci_default_resume() and is not supposed
2112 * to be called by normal code, write proper resume handler and use it instead.
2114 int pci_reenable_device(struct pci_dev *dev) in pci_reenable_device()
2117 return do_pci_enable_device(dev, (1 << PCI_NUM_RESOURCES) - 1); in pci_reenable_device()
2125 int retval; in pci_enable_bridge()
2132 if (!dev->is_busmaster) in pci_enable_bridge()
2144 static int pci_enable_device_flags(struct pci_dev *dev, unsigned long flags) in pci_enable_device_flags()
2147 int err; in pci_enable_device_flags()
2148 int i, bars = 0; in pci_enable_device_flags()
2156 pci_update_current_state(dev, dev->current_state); in pci_enable_device_flags()
2158 if (atomic_inc_return(&dev->enable_cnt) > 1) in pci_enable_device_flags()
2167 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2170 if (dev->resource[i].flags & flags) in pci_enable_device_flags()
2175 atomic_dec(&dev->enable_cnt); in pci_enable_device_flags()
2180 * pci_enable_device_mem - Initialize a device for use with Memory space
2183 * Initialize device before it's used by a driver. Ask low-level code
2187 int pci_enable_device_mem(struct pci_dev *dev) in pci_enable_device_mem()
2194 * pci_enable_device - Initialize device before it's used by a driver.
2197 * Initialize device before it's used by a driver. Ask low-level code
2198 * to enable I/O and memory. Wake up the device if it was suspended.
2204 int pci_enable_device(struct pci_dev *dev) in pci_enable_device()
2211 * pcibios_device_add - provide arch specific hooks when adding device dev
2218 int __weak pcibios_device_add(struct pci_dev *dev) in pcibios_device_add()
2224 * pcibios_release_device - provide arch specific hooks when releasing
2235 * pcibios_disable_device - disable arch specific PCI resources for device dev
2258 * pci_disable_enabled_device - Disable device without updating enable_cnt
2261 * NOTE: This function is a backend of PCI power management routines and is
2271 * pci_disable_device - Disable PCI device after use
2275 * anymore. This only involves disabling PCI bus-mastering, if active.
2282 dev_WARN_ONCE(&dev->dev, atomic_read(&dev->enable_cnt) <= 0, in pci_disable_device()
2283 "disabling already-disabled device"); in pci_disable_device()
2285 if (atomic_dec_return(&dev->enable_cnt) != 0) in pci_disable_device()
2292 dev->is_busmaster = 0; in pci_disable_device()
2297 * pcibios_set_pcie_reset_state - set reset state for device dev
2304 int __weak pcibios_set_pcie_reset_state(struct pci_dev *dev, in pcibios_set_pcie_reset_state()
2307 return -EINVAL; in pcibios_set_pcie_reset_state()
2311 * pci_set_pcie_reset_state - set reset state for device dev
2317 int pci_set_pcie_reset_state(struct pci_dev *dev, enum pcie_reset_state state) in pci_set_pcie_reset_state()
2334 * pcie_clear_root_pme_status - Clear root port PME interrupt status.
2343 * pci_check_pme_status - Check if given device has generated PME.
2346 * Check the PME status of the device and if set, clear it and clear PME enable
2347 * (if set). Return 'true' if PME status and PME enable were both set or
2352 int pmcsr_pos; in pci_check_pme_status()
2356 if (!dev->pm_cap) in pci_check_pme_status()
2359 pmcsr_pos = dev->pm_cap + PCI_PM_CTRL; in pci_check_pme_status()
2378 * pci_pme_wakeup - Wake up a PCI device if its PME Status bit is set.
2382 * Check if @dev has generated PME and queue a resume request for it in that
2385 static int pci_pme_wakeup(struct pci_dev *dev, void *pme_poll_reset) in pci_pme_wakeup()
2387 if (pme_poll_reset && dev->pme_poll) in pci_pme_wakeup()
2388 dev->pme_poll = false; in pci_pme_wakeup()
2392 pm_request_resume(&dev->dev); in pci_pme_wakeup()
2398 * pci_pme_wakeup_bus - Walk given bus and wake up devices on it, if necessary.
2409 * pci_pme_capable - check the capability of PCI device to generate PME#
2415 if (!dev->pm_cap) in pci_pme_capable()
2418 return !!(dev->pme_support & (1 << state)); in pci_pme_capable()
2428 struct pci_dev *pdev = pme_dev->dev; in pci_pme_list_scan()
2430 if (pdev->pme_poll) { in pci_pme_list_scan()
2431 struct pci_dev *bridge = pdev->bus->self; in pci_pme_list_scan()
2432 struct device *dev = &pdev->dev; in pci_pme_list_scan()
2433 struct device *bdev = bridge ? &bridge->dev : NULL; in pci_pme_list_scan()
2434 int bref = 0; in pci_pme_list_scan()
2447 if (bridge->current_state != PCI_D0) in pci_pme_list_scan()
2457 pdev->current_state != PCI_D3cold) in pci_pme_list_scan()
2464 list_del(&pme_dev->list); in pci_pme_list_scan()
2478 if (!dev->pme_support) in __pci_pme_active()
2481 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in __pci_pme_active()
2482 /* Clear PME_Status by writing 1 to it and enable PME# */ in __pci_pme_active()
2487 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in __pci_pme_active()
2491 * pci_pme_restore - Restore PME configuration after config space restore.
2498 if (!dev->pme_support) in pci_pme_restore()
2501 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr); in pci_pme_restore()
2502 if (dev->wakeup_prepared) { in pci_pme_restore()
2509 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, pmcsr); in pci_pme_restore()
2513 * pci_pme_active - enable or disable PCI device's PME# function
2527 * do this, so the PME never gets delivered and the device in pci_pme_active()
2529 * periodically walk the list of suspended devices and check in pci_pme_active()
2532 * hit, and the power savings from the devices will still be a in pci_pme_active()
2535 * Although PCIe uses in-band PME message instead of PME# line in pci_pme_active()
2544 if (dev->pme_poll) { in pci_pme_active()
2553 pme_dev->dev = dev; in pci_pme_active()
2555 list_add(&pme_dev->list, &pci_pme_list); in pci_pme_active()
2564 if (pme_dev->dev == dev) { in pci_pme_active()
2565 list_del(&pme_dev->list); in pci_pme_active()
2579 * __pci_enable_wake - enable PCI device as wakeup event source
2585 * When such events involves platform-specific hooks, those hooks are
2593 * -EINVAL is returned if device is not supposed to wake up the system
2594 * Error code depending on the platform is returned if both the platform and
2595 * the native mechanism fail to enable the generation of wake-up events
2597 static int __pci_enable_wake(struct pci_dev *dev, pci_power_t state, bool enable) in __pci_enable_wake()
2599 int ret = 0; in __pci_enable_wake()
2602 * Bridges that are not power-manageable directly only signal in __pci_enable_wake()
2605 * power-manageable may signal wakeup for themselves (for example, in __pci_enable_wake()
2606 * on a hotplug event) and they need to be covered here. in __pci_enable_wake()
2612 if (!!enable == !!dev->wakeup_prepared) in __pci_enable_wake()
2618 * enable. To disable wake-up we call the platform first, for symmetry. in __pci_enable_wake()
2622 int error; in __pci_enable_wake()
2628 * signal PME when the hierarchy above it goes into D3cold and in __pci_enable_wake()
2639 dev->wakeup_prepared = true; in __pci_enable_wake()
2643 dev->wakeup_prepared = false; in __pci_enable_wake()
2650 * pci_enable_wake - change wakeup settings for a PCI device
2658 int pci_enable_wake(struct pci_dev *pci_dev, pci_power_t state, bool enable) in pci_enable_wake()
2660 if (enable && !device_may_wakeup(&pci_dev->dev)) in pci_enable_wake()
2661 return -EINVAL; in pci_enable_wake()
2668 * pci_wake_from_d3 - enable/disable device to wake up from D3_hot or D3_cold
2670 * @enable: True to enable wake-up event generation; false to disable
2673 * and this function allows them to set that up cleanly - pci_enable_wake()
2674 * should not be called twice in a row to enable wake-up due to PCI PM vs ACPI
2679 * D3_hot and D3_cold and the platform is unable to enable wake-up power for it.
2681 int pci_wake_from_d3(struct pci_dev *dev, bool enable) in pci_wake_from_d3()
2690 * pci_target_state - find an appropriate low power state for a given PCI dev
2721 * If the device is in D3cold even though it's not power-manageable by in pci_target_state()
2722 * the platform, it may have been powered down by non-standard means. in pci_target_state()
2725 if (dev->current_state == PCI_D3cold) in pci_target_state()
2727 else if (!dev->pm_cap) in pci_target_state()
2730 if (wakeup && dev->pme_support) { in pci_target_state()
2737 while (state && !(dev->pme_support & (1 << state))) in pci_target_state()
2738 state--; in pci_target_state()
2742 else if (dev->pme_support & 1) in pci_target_state()
2750 * pci_prepare_to_sleep - prepare PCI device for system-wide transition
2755 * it can wake up the system and/or is power manageable by the platform
2756 * (PCI_D3hot is the default) and put the device into that state.
2758 int pci_prepare_to_sleep(struct pci_dev *dev) in pci_prepare_to_sleep()
2760 bool wakeup = device_may_wakeup(&dev->dev); in pci_prepare_to_sleep()
2762 int error; in pci_prepare_to_sleep()
2765 return -EIO; in pci_prepare_to_sleep()
2779 * pci_back_from_sleep - turn PCI device on during system-wide transition
2783 * Disable device's system wake-up capability and put it into D0.
2785 int pci_back_from_sleep(struct pci_dev *dev) in pci_back_from_sleep()
2787 int ret = pci_set_power_state(dev, PCI_D0); in pci_back_from_sleep()
2798 * pci_finish_runtime_suspend - Carry out PCI-specific part of runtime suspend.
2801 * Prepare @dev to generate wake-up events at run time and put it into a low
2804 int pci_finish_runtime_suspend(struct pci_dev *dev) in pci_finish_runtime_suspend()
2807 int error; in pci_finish_runtime_suspend()
2809 target_state = pci_target_state(dev, device_can_wakeup(&dev->dev)); in pci_finish_runtime_suspend()
2811 return -EIO; in pci_finish_runtime_suspend()
2824 * pci_dev_run_wake - Check if device can generate run-time wake-up events.
2827 * Return true if the device itself is capable of generating wake-up events
2829 * PME and one of its upstream bridges can generate wake-up events.
2833 struct pci_bus *bus = dev->bus; in pci_dev_run_wake()
2835 if (!dev->pme_support) in pci_dev_run_wake()
2838 /* PME-capable in principle, but not from the target power state */ in pci_dev_run_wake()
2842 if (device_can_wakeup(&dev->dev)) in pci_dev_run_wake()
2845 while (bus->parent) { in pci_dev_run_wake()
2846 struct pci_dev *bridge = bus->self; in pci_dev_run_wake()
2848 if (device_can_wakeup(&bridge->dev)) in pci_dev_run_wake()
2851 bus = bus->parent; in pci_dev_run_wake()
2855 if (bus->bridge) in pci_dev_run_wake()
2856 return device_can_wakeup(bus->bridge); in pci_dev_run_wake()
2863 * pci_dev_need_resume - Check if it is necessary to resume the device.
2866 * Return 'true' if the device is not runtime-suspended or it has to be
2867 * reconfigured due to wakeup settings difference between system and runtime
2869 * (system-wide) transition.
2873 struct device *dev = &pci_dev->dev; in pci_dev_need_resume()
2886 return target_state != pci_dev->current_state && in pci_dev_need_resume()
2888 pci_dev->current_state != PCI_D3hot; in pci_dev_need_resume()
2892 * pci_dev_adjust_pme - Adjust PME setting for a suspended device.
2895 * If the device is suspended and it is not configured for system wakeup,
2898 * Note that if the device's power state is D3cold and the platform check in
2904 struct device *dev = &pci_dev->dev; in pci_dev_adjust_pme()
2906 spin_lock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2909 pci_dev->current_state < PCI_D3cold) in pci_dev_adjust_pme()
2912 spin_unlock_irq(&dev->power.lock); in pci_dev_adjust_pme()
2916 * pci_dev_complete_resume - Finalize resume from system sleep for a device.
2919 * If the device is runtime suspended and wakeup-capable, enable PME for it as
2925 struct device *dev = &pci_dev->dev; in pci_dev_complete_resume()
2930 spin_lock_irq(&dev->power.lock); in pci_dev_complete_resume()
2932 if (pm_runtime_suspended(dev) && pci_dev->current_state < PCI_D3cold) in pci_dev_complete_resume()
2935 spin_unlock_irq(&dev->power.lock); in pci_dev_complete_resume()
2939 * pci_choose_state - Choose the power state of a PCI device.
2943 * Returns PCI power state suitable for @dev and @state.
2956 struct device *dev = &pdev->dev; in pci_config_pm_runtime_get()
2957 struct device *parent = dev->parent; in pci_config_pm_runtime_get()
2963 * pdev->current_state is set to PCI_D3cold during suspending, in pci_config_pm_runtime_get()
2972 if (pdev->current_state == PCI_D3cold) in pci_config_pm_runtime_get()
2978 struct device *dev = &pdev->dev; in pci_config_pm_runtime_put()
2979 struct device *parent = dev->parent; in pci_config_pm_runtime_put()
2995 .ident = "X299 DESIGNARE EX-CF",
2998 DMI_MATCH(DMI_BOARD_NAME, "X299 DESIGNARE EX-CF"),
3004 * into D3cold and back into D0 on Elo Continental Z2 board
3016 * https://gitlab.freedesktop.org/drm/amd/-/issues/3229
3018 .ident = "Hewlett-Packard HP Pavilion 17 Notebook PC/1972",
3020 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
3030 * pci_bridge_d3_possible - Is it possible to put the bridge into D3
3034 * Currently we only allow D3 for some PCIe ports and for Thunderbolt.
3050 * may not be put into D3 by the OS (Thunderbolt on non-Macs). in pci_bridge_d3_possible()
3052 if (bridge->is_hotplug_bridge && !pciehp_is_native(bridge)) in pci_bridge_d3_possible()
3059 if (bridge->is_thunderbolt) in pci_bridge_d3_possible()
3071 if (bridge->is_hotplug_bridge) in pci_bridge_d3_possible()
3089 static int pci_dev_check_d3cold(struct pci_dev *dev, void *data) in pci_dev_check_d3cold()
3094 dev->no_d3cold || !dev->d3cold_allowed || in pci_dev_check_d3cold()
3096 /* ... and if it is wakeup capable to do so from D3cold. */ in pci_dev_check_d3cold()
3097 (device_may_wakeup(&dev->dev) && in pci_dev_check_d3cold()
3109 * pci_bridge_d3_update - Update bridge D3 capabilities
3118 bool remove = !device_is_registered(&dev->dev); in pci_bridge_d3_update()
3130 if (remove && bridge->bridge_d3) in pci_bridge_d3_update()
3134 * If D3 is currently allowed for the bridge and a child is added or in pci_bridge_d3_update()
3150 if (d3cold_ok && !bridge->bridge_d3) in pci_bridge_d3_update()
3151 pci_walk_bus(bridge->subordinate, pci_dev_check_d3cold, in pci_bridge_d3_update()
3154 if (bridge->bridge_d3 != d3cold_ok) { in pci_bridge_d3_update()
3155 bridge->bridge_d3 = d3cold_ok; in pci_bridge_d3_update()
3162 * pci_d3cold_enable - Enable D3cold for device
3171 if (dev->no_d3cold) { in pci_d3cold_enable()
3172 dev->no_d3cold = false; in pci_d3cold_enable()
3179 * pci_d3cold_disable - Disable D3cold for device
3188 if (!dev->no_d3cold) { in pci_d3cold_disable()
3189 dev->no_d3cold = true; in pci_d3cold_disable()
3196 * pci_pm_init - Initialize PM functions of given PCI device
3201 int pm; in pci_pm_init()
3205 pm_runtime_forbid(&dev->dev); in pci_pm_init()
3206 pm_runtime_set_active(&dev->dev); in pci_pm_init()
3207 pm_runtime_enable(&dev->dev); in pci_pm_init()
3208 device_enable_async_suspend(&dev->dev); in pci_pm_init()
3209 dev->wakeup_prepared = false; in pci_pm_init()
3211 dev->pm_cap = 0; in pci_pm_init()
3212 dev->pme_support = 0; in pci_pm_init()
3227 dev->pm_cap = pm; in pci_pm_init()
3228 dev->d3hot_delay = PCI_PM_D3HOT_WAIT; in pci_pm_init()
3229 dev->d3cold_delay = PCI_PM_D3COLD_WAIT; in pci_pm_init()
3230 dev->bridge_d3 = pci_bridge_d3_possible(dev); in pci_pm_init()
3231 dev->d3cold_allowed = true; in pci_pm_init()
3233 dev->d1_support = false; in pci_pm_init()
3234 dev->d2_support = false; in pci_pm_init()
3237 dev->d1_support = true; in pci_pm_init()
3239 dev->d2_support = true; in pci_pm_init()
3241 if (dev->d1_support || dev->d2_support) in pci_pm_init()
3243 dev->d1_support ? " D1" : "", in pci_pm_init()
3244 dev->d2_support ? " D2" : ""); in pci_pm_init()
3255 dev->pme_support = FIELD_GET(PCI_PM_CAP_PME_MASK, pmc); in pci_pm_init()
3256 dev->pme_poll = true; in pci_pm_init()
3258 * Make device's PM flags reflect the wake-up capability, but in pci_pm_init()
3261 device_set_wakeup_capable(&dev->dev, true); in pci_pm_init()
3268 dev->imm_ready = 1; in pci_pm_init()
3298 return &dev->resource[bei]; in pci_ea_get_resource()
3302 return &dev->resource[PCI_IOV_RESOURCES + in pci_ea_get_resource()
3303 bei - PCI_EA_BEI_VF_BAR0]; in pci_ea_get_resource()
3306 return &dev->resource[PCI_ROM_RESOURCE]; in pci_ea_get_resource()
3312 static int pci_ea_read(struct pci_dev *dev, int offset) in pci_ea_read()
3316 int ent_size, ent_offset = offset; in pci_ea_read()
3366 /* Read Base MSBs (if 64-bit entry) */ in pci_ea_read()
3375 /* entry starts above 32-bit boundary, can't use */ in pci_ea_read()
3385 /* Read MaxOffset MSBs (if 64-bit entry) */ in pci_ea_read()
3407 if (ent_size != ent_offset - offset) { in pci_ea_read()
3408 pci_err(dev, "EA Entry Size (%d) does not match length read (%d)\n", in pci_ea_read()
3409 ent_size, ent_offset - offset); in pci_ea_read()
3413 res->name = pci_name(dev); in pci_ea_read()
3414 res->start = start; in pci_ea_read()
3415 res->end = end; in pci_ea_read()
3416 res->flags = flags; in pci_ea_read()
3438 int ea; in pci_ea_init()
3440 int offset; in pci_ea_init()
3441 int i; in pci_ea_init()
3449 pci_bus_read_config_byte(dev->bus, dev->devfn, ea + PCI_EA_NUM_ENT, in pci_ea_init()
3456 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) in pci_ea_init()
3467 hlist_add_head(&new_cap->next, &pci_dev->saved_cap_space); in pci_add_saved_cap()
3471 * _pci_add_cap_save_buffer - allocate buffer for saving given
3478 static int _pci_add_cap_save_buffer(struct pci_dev *dev, u16 cap, in _pci_add_cap_save_buffer()
3479 bool extended, unsigned int size) in _pci_add_cap_save_buffer()
3481 int pos; in _pci_add_cap_save_buffer()
3494 return -ENOMEM; in _pci_add_cap_save_buffer()
3496 save_state->cap.cap_nr = cap; in _pci_add_cap_save_buffer()
3497 save_state->cap.cap_extended = extended; in _pci_add_cap_save_buffer()
3498 save_state->cap.size = size; in _pci_add_cap_save_buffer()
3504 int pci_add_cap_save_buffer(struct pci_dev *dev, char cap, unsigned int size) in pci_add_cap_save_buffer()
3509 int pci_add_ext_cap_save_buffer(struct pci_dev *dev, u16 cap, unsigned int size) in pci_add_ext_cap_save_buffer()
3515 * pci_allocate_cap_save_buffers - allocate buffers for saving capabilities
3520 int error; in pci_allocate_cap_save_buffers()
3529 pci_err(dev, "unable to preallocate PCI-X save buffer\n"); in pci_allocate_cap_save_buffers()
3544 hlist_for_each_entry_safe(tmp, n, &dev->saved_cap_space, next) in pci_free_cap_save_buffers()
3549 * pci_configure_ari - enable or disable ARI forwarding
3552 * If @dev and its upstream bridge both support ARI, enable ARI in the
3560 if (pcie_ari_disabled || !pci_is_pcie(dev) || dev->devfn) in pci_configure_ari()
3563 bridge = dev->bus->self; in pci_configure_ari()
3574 bridge->ari_enabled = 1; in pci_configure_ari()
3578 bridge->ari_enabled = 0; in pci_configure_ari()
3584 int pos; in pci_acs_flags_enabled()
3587 pos = pdev->acs_cap; in pci_acs_flags_enabled()
3594 * capability field can therefore be assumed as hard-wired enabled. in pci_acs_flags_enabled()
3604 * pci_acs_enabled - test ACS against required flags for a given device
3614 * opportunity for peer-to-peer access. We therefore return 'true'
3621 int ret; in pci_acs_enabled()
3628 * Conventional PCI and PCI-X devices never support ACS, either in pci_acs_enabled()
3637 * PCI/X-to-PCIe bridges are not specifically mentioned by the spec, in pci_acs_enabled()
3639 * handle them as we would a non-PCIe device. in pci_acs_enabled()
3652 * PCIe 3.0, 6.12.1.1 specifies that downstream and root ports should in pci_acs_enabled()
3653 * implement ACS in order to indicate their peer-to-peer capabilities, in pci_acs_enabled()
3654 * regardless of whether they are single- or multi-function devices. in pci_acs_enabled()
3661 * implemented by the remaining PCIe types to indicate peer-to-peer in pci_acs_enabled()
3670 if (!pdev->multifunction) in pci_acs_enabled()
3684 * pci_acs_path_enabled - test ACS flags from start to end in a hierarchy
3703 if (pci_is_root_bus(pdev->bus)) in pci_acs_path_enabled()
3706 parent = pdev->bus->self; in pci_acs_path_enabled()
3713 * pci_acs_init - Initialize ACS if hardware supports it
3718 dev->acs_cap = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_ACS); in pci_acs_init()
3731 pdev->rebar_cap = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_REBAR); in pci_rebar_init()
3735 * pci_rebar_find_pos - find position of resize ctrl reg for BAR
3740 * Returns -ENOTSUPP if resizable BARs are not supported at all.
3741 * Returns -ENOENT if no ctrl register for the BAR could be found.
3743 static int pci_rebar_find_pos(struct pci_dev *pdev, int bar) in pci_rebar_find_pos()
3745 unsigned int pos, nbars, i; in pci_rebar_find_pos()
3748 pos = pdev->rebar_cap; in pci_rebar_find_pos()
3750 return -ENOTSUPP; in pci_rebar_find_pos()
3756 int bar_idx; in pci_rebar_find_pos()
3764 return -ENOENT; in pci_rebar_find_pos()
3768 * pci_rebar_get_possible_sizes - get possible sizes for BAR
3775 u32 pci_rebar_get_possible_sizes(struct pci_dev *pdev, int bar) in pci_rebar_get_possible_sizes()
3777 int pos; in pci_rebar_get_possible_sizes()
3788 if (pdev->vendor == PCI_VENDOR_ID_ATI && pdev->device == 0x731f && in pci_rebar_get_possible_sizes()
3797 * pci_rebar_get_current_size - get the current size of a BAR
3804 int pci_rebar_get_current_size(struct pci_dev *pdev, int bar) in pci_rebar_get_current_size()
3806 int pos; in pci_rebar_get_current_size()
3818 * pci_rebar_set_size - set a new size for a BAR
3826 int pci_rebar_set_size(struct pci_dev *pdev, int bar, int size) in pci_rebar_set_size()
3828 int pos; in pci_rebar_set_size()
3843 * pci_enable_atomic_ops_to_root - enable AtomicOp requests to root port
3851 * blocking is disabled on all upstream ports, and the root port supports
3852 * the requested completion capabilities (32-bit, 64-bit and/or 128-bit
3855 int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask) in pci_enable_atomic_ops_to_root()
3857 struct pci_bus *bus = dev->bus; in pci_enable_atomic_ops_to_root()
3863 * in Device Control 2 is reserved in VFs and the PF value applies in pci_enable_atomic_ops_to_root()
3866 if (dev->is_virtfn) in pci_enable_atomic_ops_to_root()
3867 return -EINVAL; in pci_enable_atomic_ops_to_root()
3870 return -EINVAL; in pci_enable_atomic_ops_to_root()
3873 * Per PCIe r4.0, sec 6.15, endpoints and root ports may be in pci_enable_atomic_ops_to_root()
3875 * requesters and root ports as completers. No endpoints as in pci_enable_atomic_ops_to_root()
3876 * completers, and no peer-to-peer. in pci_enable_atomic_ops_to_root()
3885 return -EINVAL; in pci_enable_atomic_ops_to_root()
3888 while (bus->parent) { in pci_enable_atomic_ops_to_root()
3889 bridge = bus->self; in pci_enable_atomic_ops_to_root()
3898 return -EINVAL; in pci_enable_atomic_ops_to_root()
3904 return -EINVAL; in pci_enable_atomic_ops_to_root()
3913 return -EINVAL; in pci_enable_atomic_ops_to_root()
3916 bus = bus->parent; in pci_enable_atomic_ops_to_root()
3926 * pci_release_region - Release a PCI bar
3931 * Releases the PCI I/O and memory resources previously reserved by a
3935 void pci_release_region(struct pci_dev *pdev, int bar) in pci_release_region()
3962 * __pci_request_region - Reserved PCI I/O and memory resource
3981 static int __pci_request_region(struct pci_dev *pdev, int bar, in __pci_request_region()
3982 const char *name, int exclusive) in __pci_request_region()
3985 return -EINVAL; in __pci_request_region()
4012 &pdev->resource[bar]); in __pci_request_region()
4013 return -EBUSY; in __pci_request_region()
4017 * pci_request_region - Reserve PCI I/O and memory resource
4036 int pci_request_region(struct pci_dev *pdev, int bar, const char *name) in pci_request_region()
4043 * pci_release_selected_regions - Release selected PCI I/O and memory resources
4047 * Release selected PCI I/O and memory resources previously reserved.
4050 void pci_release_selected_regions(struct pci_dev *pdev, int bars) in pci_release_selected_regions()
4052 int i; in pci_release_selected_regions()
4060 static int __pci_request_selected_regions(struct pci_dev *pdev, int bars, in __pci_request_selected_regions()
4061 const char *name, int excl) in __pci_request_selected_regions()
4063 int i; in __pci_request_selected_regions()
4072 while (--i >= 0) in __pci_request_selected_regions()
4076 return -EBUSY; in __pci_request_selected_regions()
4081 * pci_request_selected_regions - Reserve selected PCI I/O and memory resources
4093 int pci_request_selected_regions(struct pci_dev *pdev, int bars, in pci_request_selected_regions()
4101 * pci_request_selected_regions_exclusive - Request regions exclusively
4113 int pci_request_selected_regions_exclusive(struct pci_dev *pdev, int bars, in pci_request_selected_regions_exclusive()
4122 * pci_release_regions - Release reserved PCI I/O and memory resources
4126 * Releases all PCI I/O and memory resources previously reserved by a
4132 pci_release_selected_regions(pdev, (1 << PCI_STD_NUM_BARS) - 1); in pci_release_regions()
4137 * pci_request_regions - Reserve PCI I/O and memory resources
4153 int pci_request_regions(struct pci_dev *pdev, const char *name) in pci_request_regions()
4156 ((1 << PCI_STD_NUM_BARS) - 1), name); in pci_request_regions()
4161 * pci_request_regions_exclusive - Reserve PCI I/O and memory resources
4172 * and the sysfs MMIO access will not be allowed.
4182 int pci_request_regions_exclusive(struct pci_dev *pdev, const char *name) in pci_request_regions_exclusive()
4185 ((1 << PCI_STD_NUM_BARS) - 1), name); in pci_request_regions_exclusive()
4193 int pci_register_io_range(const struct fwnode_handle *fwnode, phys_addr_t addr, in pci_register_io_range()
4196 int ret = 0; in pci_register_io_range()
4201 return -EINVAL; in pci_register_io_range()
4205 return -ENOMEM; in pci_register_io_range()
4207 range->fwnode = fwnode; in pci_register_io_range()
4208 range->size = size; in pci_register_io_range()
4209 range->hw_start = addr; in pci_register_io_range()
4210 range->flags = LOGIC_PIO_CPU_MMIO; in pci_register_io_range()
4217 if (ret == -EEXIST) in pci_register_io_range()
4241 return (unsigned long)-1; in pci_address_to_pio()
4248 * pci_remap_iospace - Remap the memory mapped I/O space
4252 * Remap the memory mapped I/O space described by the @res and the CPU
4254 * architectures that have memory mapped IO functions defined (and the
4258 int pci_remap_iospace(const struct resource *res, phys_addr_t phys_addr) in pci_remap_iospace()
4261 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_remap_iospace()
4263 if (!(res->flags & IORESOURCE_IO)) in pci_remap_iospace()
4264 return -EINVAL; in pci_remap_iospace()
4266 if (res->end > IO_SPACE_LIMIT) in pci_remap_iospace()
4267 return -EINVAL; in pci_remap_iospace()
4277 return -ENODEV; in pci_remap_iospace()
4284 * pci_unmap_iospace - Unmap the memory mapped I/O space
4288 * architectures that have memory mapped IO functions defined (and the
4294 unsigned long vaddr = (unsigned long)PCI_IOBASE + res->start; in pci_unmap_iospace()
4315 dev->is_busmaster = enable; in __pci_set_master()
4319 * pcibios_setup - process "pci=" kernel boot arguments
4331 * pcibios_set_master - enable PCI bus-mastering for device dev
4334 * Enables PCI bus-mastering for the device. This is the default
4358 * pci_set_master - enables bus-mastering for device dev
4361 * Enables bus-mastering on the device and calls pcibios_set_master()
4372 * pci_clear_master - disables bus-mastering for device dev
4382 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed
4387 * Copyright 1998-2001 by Jes Sorensen, <jes@trained-monkey.org>.
4389 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4391 int pci_set_cacheline_size(struct pci_dev *dev) in pci_set_cacheline_size()
4396 return -EINVAL; in pci_set_cacheline_size()
4415 return -EINVAL; in pci_set_cacheline_size()
4420 * pci_set_mwi - enables memory-write-invalidate PCI transaction
4423 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4425 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4427 int pci_set_mwi(struct pci_dev *dev) in pci_set_mwi()
4432 int rc; in pci_set_mwi()
4441 pci_dbg(dev, "enabling Mem-Wr-Inval\n"); in pci_set_mwi()
4451 * pci_try_set_mwi - enables memory-write-invalidate PCI transaction
4454 * Enables the Memory-Write-Invalidate transaction in %PCI_COMMAND.
4457 * RETURNS: An appropriate -ERRNO error value on error, or zero for success.
4459 int pci_try_set_mwi(struct pci_dev *dev) in pci_try_set_mwi()
4470 * pci_clear_mwi - disables Memory-Write-Invalidate for device dev
4473 * Disables PCI Memory-Write-Invalidate transaction on the device
4490 * pci_disable_parity - disable parity checking for device
4507 * pci_intx - enables/disables PCI INTx for device dev
4513 void pci_intx(struct pci_dev *pdev, int enable) in pci_intx()
4532 * pci_wait_for_pending_transaction - wait for pending transaction
4537 int pci_wait_for_pending_transaction(struct pci_dev *dev) in pci_wait_for_pending_transaction()
4548 * pcie_flr - initiate a PCIe function level reset
4552 * checking any flags and DEVCAP
4554 int pcie_flr(struct pci_dev *dev) in pcie_flr()
4561 if (dev->imm_ready) in pcie_flr()
4576 * pcie_reset_flr - initiate a PCIe function level reset
4582 int pcie_reset_flr(struct pci_dev *dev, bool probe) in pcie_reset_flr()
4584 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pcie_reset_flr()
4585 return -ENOTTY; in pcie_reset_flr()
4587 if (!(dev->devcap & PCI_EXP_DEVCAP_FLR)) in pcie_reset_flr()
4588 return -ENOTTY; in pcie_reset_flr()
4597 static int pci_af_flr(struct pci_dev *dev, bool probe) in pci_af_flr()
4599 int pos; in pci_af_flr()
4604 return -ENOTTY; in pci_af_flr()
4606 if (dev->dev_flags & PCI_DEV_FLAGS_NO_FLR_RESET) in pci_af_flr()
4607 return -ENOTTY; in pci_af_flr()
4611 return -ENOTTY; in pci_af_flr()
4617 * Wait for Transaction Pending bit to clear. A word-aligned test in pci_af_flr()
4618 * is used, so we use the control offset rather than status and shift in pci_af_flr()
4627 if (dev->imm_ready) in pci_af_flr()
4642 * pci_pm_reset - Put device into PCI_D3 and back into PCI_D0.
4646 * If @dev supports native PCI PM and its PCI_PM_CTRL_NO_SOFT_RESET flag is
4648 * PCI_D0. If that's the case and the device is not in a low-power state
4649 * already, force it into PCI_D3hot and back to PCI_D0, causing it to be reset.
4652 * cooldown period, which for the D0->D3hot and D3hot->D0 transitions is 10 ms
4656 static int pci_pm_reset(struct pci_dev *dev, bool probe) in pci_pm_reset()
4660 if (!dev->pm_cap || dev->dev_flags & PCI_DEV_FLAGS_NO_PM_RESET) in pci_pm_reset()
4661 return -ENOTTY; in pci_pm_reset()
4663 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &csr); in pci_pm_reset()
4665 return -ENOTTY; in pci_pm_reset()
4670 if (dev->current_state != PCI_D0) in pci_pm_reset()
4671 return -EINVAL; in pci_pm_reset()
4675 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4680 pci_write_config_word(dev, dev->pm_cap + PCI_PM_CTRL, csr); in pci_pm_reset()
4683 return pci_dev_wait(dev, "PM D3hot->D0", PCIE_RESET_READY_POLL_MS); in pci_pm_reset()
4687 * pcie_wait_for_link_status - Wait for link status change
4692 * Return 0 if successful, or -ETIMEDOUT if status has not changed within
4695 static int pcie_wait_for_link_status(struct pci_dev *pdev, in pcie_wait_for_link_status()
4713 return -ETIMEDOUT; in pcie_wait_for_link_status()
4717 * pcie_retrain_link - Request a link retrain and wait for it to complete
4725 * Return 0 if successful, or -ETIMEDOUT if training has not completed
4728 int pcie_retrain_link(struct pci_dev *pdev, bool use_lt) in pcie_retrain_link()
4730 int rc; in pcie_retrain_link()
4744 if (pdev->clear_retrain_link) { in pcie_retrain_link()
4765 * pcie_wait_for_link_delay - Wait until link is active or inactive
4773 int delay) in pcie_wait_for_link_delay()
4775 int rc; in pcie_wait_for_link_delay()
4781 if (!pdev->link_active_reporting) { in pcie_wait_for_link_delay()
4815 * pcie_wait_for_link - Wait until link is active or inactive
4828 * spec says 100 ms, but firmware can lower it and we allow drivers to
4833 static int pci_bus_max_d3cold_delay(const struct pci_bus *bus) in pci_bus_max_d3cold_delay()
4836 int min_delay = 100; in pci_bus_max_d3cold_delay()
4837 int max_delay = 0; in pci_bus_max_d3cold_delay()
4839 list_for_each_entry(pdev, &bus->devices, bus_list) { in pci_bus_max_d3cold_delay()
4840 if (pdev->d3cold_delay < min_delay) in pci_bus_max_d3cold_delay()
4841 min_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4842 if (pdev->d3cold_delay > max_delay) in pci_bus_max_d3cold_delay()
4843 max_delay = pdev->d3cold_delay; in pci_bus_max_d3cold_delay()
4850 * pci_bridge_wait_for_secondary_bus - Wait for secondary bus to be accessible
4852 * @reset_type: reset type in human-readable form
4862 * Return 0 on success or -ENOTTY if the first device on the secondary bus
4865 int pci_bridge_wait_for_secondary_bus(struct pci_dev *dev, char *reset_type) in pci_bridge_wait_for_secondary_bus()
4868 int delay; in pci_bridge_wait_for_secondary_bus()
4880 * For any hot-added devices the access delay is handled in pciehp in pci_bridge_wait_for_secondary_bus()
4884 if (!dev->subordinate || list_empty(&dev->subordinate->devices)) { in pci_bridge_wait_for_secondary_bus()
4890 delay = pci_bus_max_d3cold_delay(dev->subordinate); in pci_bridge_wait_for_secondary_bus()
4896 child = pci_dev_get(list_first_entry(&dev->subordinate->devices, in pci_bridge_wait_for_secondary_bus()
4901 * Conventional PCI and PCI-X we need to wait Tpvrh + Trhfa before in pci_bridge_wait_for_secondary_bus()
4911 * For PCIe downstream and root ports that do not support speeds in pci_bridge_wait_for_secondary_bus()
4916 * However, 100 ms is the minimum and the PCIe spec says the in pci_bridge_wait_for_secondary_bus()
4922 * Therefore we wait for 100 ms and check for the device presence in pci_bridge_wait_for_secondary_bus()
4934 if (!pci_dev_wait(child, reset_type, PCI_RESET_WAIT - delay)) in pci_bridge_wait_for_secondary_bus()
4939 * whether the link is active and if not bail out early with in pci_bridge_wait_for_secondary_bus()
4942 if (!dev->link_active_reporting) in pci_bridge_wait_for_secondary_bus()
4943 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4947 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4950 PCIE_RESET_READY_POLL_MS - PCI_RESET_WAIT); in pci_bridge_wait_for_secondary_bus()
4958 return -ENOTTY; in pci_bridge_wait_for_secondary_bus()
4962 PCIE_RESET_READY_POLL_MS - delay); in pci_bridge_wait_for_secondary_bus()
4989 * pci_bridge_secondary_bus_reset - Reset the secondary bus on a PCI bridge.
4993 * Devices on the secondary bus are left in power-on state.
4995 int pci_bridge_secondary_bus_reset(struct pci_dev *dev) in pci_bridge_secondary_bus_reset()
4997 if (!dev->block_cfg_access) in pci_bridge_secondary_bus_reset()
5006 static int pci_parent_bus_reset(struct pci_dev *dev, bool probe) in pci_parent_bus_reset()
5010 if (pci_is_root_bus(dev->bus) || dev->subordinate || in pci_parent_bus_reset()
5011 !dev->bus->self || dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_parent_bus_reset()
5012 return -ENOTTY; in pci_parent_bus_reset()
5014 list_for_each_entry(pdev, &dev->bus->devices, bus_list) in pci_parent_bus_reset()
5016 return -ENOTTY; in pci_parent_bus_reset()
5021 return pci_bridge_secondary_bus_reset(dev->bus->self); in pci_parent_bus_reset()
5024 static int pci_reset_hotplug_slot(struct hotplug_slot *hotplug, bool probe) in pci_reset_hotplug_slot()
5026 int rc = -ENOTTY; in pci_reset_hotplug_slot()
5028 if (!hotplug || !try_module_get(hotplug->owner)) in pci_reset_hotplug_slot()
5031 if (hotplug->ops->reset_slot) in pci_reset_hotplug_slot()
5032 rc = hotplug->ops->reset_slot(hotplug, probe); in pci_reset_hotplug_slot()
5034 module_put(hotplug->owner); in pci_reset_hotplug_slot()
5039 static int pci_dev_reset_slot_function(struct pci_dev *dev, bool probe) in pci_dev_reset_slot_function()
5041 if (dev->multifunction || dev->subordinate || !dev->slot || in pci_dev_reset_slot_function()
5042 dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET) in pci_dev_reset_slot_function()
5043 return -ENOTTY; in pci_dev_reset_slot_function()
5045 return pci_reset_hotplug_slot(dev->slot->hotplug, probe); in pci_dev_reset_slot_function()
5057 int rc; in cxl_sbr_masked()
5078 static int pci_reset_bus_function(struct pci_dev *dev, bool probe) in pci_reset_bus_function()
5081 int rc; in pci_reset_bus_function()
5091 return -ENOTTY; in pci_reset_bus_function()
5095 if (rc != -ENOTTY) in pci_reset_bus_function()
5100 static int cxl_reset_bus_function(struct pci_dev *dev, bool probe) in cxl_reset_bus_function()
5104 int rc; in cxl_reset_bus_function()
5108 return -ENOTTY; in cxl_reset_bus_function()
5112 return -ENOTTY; in cxl_reset_bus_function()
5119 return -ENOTTY; in cxl_reset_bus_function()
5141 device_lock(&dev->dev); in pci_dev_lock()
5147 int pci_dev_trylock(struct pci_dev *dev) in pci_dev_trylock()
5149 if (device_trylock(&dev->dev)) { in pci_dev_trylock()
5152 device_unlock(&dev->dev); in pci_dev_trylock()
5162 device_unlock(&dev->dev); in pci_dev_unlock()
5169 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_save_and_disable()
5172 * dev->driver->err_handler->reset_prepare() is protected against in pci_dev_save_and_disable()
5173 * races with ->remove() by the device lock, which must be held by in pci_dev_save_and_disable()
5176 if (err_handler && err_handler->reset_prepare) in pci_dev_save_and_disable()
5177 err_handler->reset_prepare(dev); in pci_dev_save_and_disable()
5178 else if (dev->driver) in pci_dev_save_and_disable()
5182 * Wake-up device prior to save. PM registers default to D0 after in pci_dev_save_and_disable()
5183 * reset and a simple register restore doesn't reliably return in pci_dev_save_and_disable()
5184 * to a non-D0 state anyway. in pci_dev_save_and_disable()
5191 * INTx-disable which is set. This not only disables MMIO and I/O port in pci_dev_save_and_disable()
5193 * DMA from the device including MSI/MSI-X interrupts. For PCI 2.3 in pci_dev_save_and_disable()
5194 * compliant devices, INTx-disable prevents legacy interrupts. in pci_dev_save_and_disable()
5202 dev->driver ? dev->driver->err_handler : NULL; in pci_dev_restore()
5207 * dev->driver->err_handler->reset_done() is protected against in pci_dev_restore()
5208 * races with ->remove() by the device lock, which must be held by in pci_dev_restore()
5211 if (err_handler && err_handler->reset_done) in pci_dev_restore()
5212 err_handler->reset_done(dev); in pci_dev_restore()
5213 else if (dev->driver) in pci_dev_restore()
5217 /* dev->reset_methods[] is a 0-terminated list of indices into this array */
5230 * __pci_reset_function_locked - reset a PCI device function while holding
5238 * The device function is presumed to be unused and the caller is holding
5243 * device including MSI, bus mastering, BARs, decoding IO and memory spaces,
5249 int __pci_reset_function_locked(struct pci_dev *dev) in __pci_reset_function_locked()
5251 int i, m, rc; in __pci_reset_function_locked()
5257 * A reset method returns -ENOTTY if it doesn't support this device and in __pci_reset_function_locked()
5265 m = dev->reset_methods[i]; in __pci_reset_function_locked()
5267 return -ENOTTY; in __pci_reset_function_locked()
5270 pci_dbg(dev, "reset via %s\n", method->name); in __pci_reset_function_locked()
5271 rc = method->reset_fn(dev, PCI_RESET_DO_RESET); in __pci_reset_function_locked()
5275 pci_dbg(dev, "%s failed with %d\n", method->name, rc); in __pci_reset_function_locked()
5276 if (rc != -ENOTTY) in __pci_reset_function_locked()
5280 return -ENOTTY; in __pci_reset_function_locked()
5285 * pci_init_reset_methods - check whether device can be safely reset
5286 * and store supported reset mechanisms.
5290 * other functions in the same device. The PCI device must be in D0-D3hot
5293 * Stores reset mechanisms supported by device in reset_methods byte array
5298 int m, i, rc; in pci_init_reset_methods()
5308 dev->reset_methods[i++] = m; in pci_init_reset_methods()
5309 else if (rc != -ENOTTY) in pci_init_reset_methods()
5313 dev->reset_methods[i] = 0; in pci_init_reset_methods()
5317 * pci_reset_function - quiesce and reset a PCI device function
5326 * from __pci_reset_function_locked() in that it saves and restores device state
5327 * over the reset and takes the PCI device lock.
5332 int pci_reset_function(struct pci_dev *dev) in pci_reset_function()
5335 int rc; in pci_reset_function()
5338 return -ENOTTY; in pci_reset_function()
5364 * pci_reset_function_locked - quiesce and reset a PCI device function
5373 * from __pci_reset_function_locked() in that it saves and restores device state
5380 int pci_reset_function_locked(struct pci_dev *dev) in pci_reset_function_locked()
5382 int rc; in pci_reset_function_locked()
5385 return -ENOTTY; in pci_reset_function_locked()
5398 * pci_try_reset_function - quiesce and reset a PCI device function
5401 * Same as above, except return -EAGAIN if unable to lock device.
5403 int pci_try_reset_function(struct pci_dev *dev) in pci_try_reset_function()
5405 int rc; in pci_try_reset_function()
5408 return -ENOTTY; in pci_try_reset_function()
5411 return -EAGAIN; in pci_try_reset_function()
5428 if (bus->self && (bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_bus_resettable()
5431 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_resettable()
5432 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_bus_resettable()
5433 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_bus_resettable()
5445 pci_dev_lock(bus->self); in pci_bus_lock()
5446 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_lock()
5447 if (dev->subordinate) in pci_bus_lock()
5448 pci_bus_lock(dev->subordinate); in pci_bus_lock()
5459 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_unlock()
5460 if (dev->subordinate) in pci_bus_unlock()
5461 pci_bus_unlock(dev->subordinate); in pci_bus_unlock()
5465 pci_dev_unlock(bus->self); in pci_bus_unlock()
5469 static int pci_bus_trylock(struct pci_bus *bus) in pci_bus_trylock()
5473 if (!pci_dev_trylock(bus->self)) in pci_bus_trylock()
5476 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5477 if (dev->subordinate) { in pci_bus_trylock()
5478 if (!pci_bus_trylock(dev->subordinate)) in pci_bus_trylock()
5486 list_for_each_entry_continue_reverse(dev, &bus->devices, bus_list) { in pci_bus_trylock()
5487 if (dev->subordinate) in pci_bus_trylock()
5488 pci_bus_unlock(dev->subordinate); in pci_bus_trylock()
5492 pci_dev_unlock(bus->self); in pci_bus_trylock()
5501 if (slot->bus->self && in pci_slot_resettable()
5502 (slot->bus->self->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET)) in pci_slot_resettable()
5505 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_resettable()
5506 if (!dev->slot || dev->slot != slot) in pci_slot_resettable()
5508 if (dev->dev_flags & PCI_DEV_FLAGS_NO_BUS_RESET || in pci_slot_resettable()
5509 (dev->subordinate && !pci_bus_resettable(dev->subordinate))) in pci_slot_resettable()
5521 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_lock()
5522 if (!dev->slot || dev->slot != slot) in pci_slot_lock()
5524 if (dev->subordinate) in pci_slot_lock()
5525 pci_bus_lock(dev->subordinate); in pci_slot_lock()
5536 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_unlock()
5537 if (!dev->slot || dev->slot != slot) in pci_slot_unlock()
5539 if (dev->subordinate) in pci_slot_unlock()
5540 pci_bus_unlock(dev->subordinate); in pci_slot_unlock()
5546 static int pci_slot_trylock(struct pci_slot *slot) in pci_slot_trylock()
5550 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_trylock()
5551 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5553 if (dev->subordinate) { in pci_slot_trylock()
5554 if (!pci_bus_trylock(dev->subordinate)) { in pci_slot_trylock()
5565 &slot->bus->devices, bus_list) { in pci_slot_trylock()
5566 if (!dev->slot || dev->slot != slot) in pci_slot_trylock()
5568 if (dev->subordinate) in pci_slot_trylock()
5569 pci_bus_unlock(dev->subordinate); in pci_slot_trylock()
5577 * Save and disable devices from the top of the tree down while holding
5584 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_save_and_disable_locked()
5586 if (dev->subordinate) in pci_bus_save_and_disable_locked()
5587 pci_bus_save_and_disable_locked(dev->subordinate); in pci_bus_save_and_disable_locked()
5600 list_for_each_entry(dev, &bus->devices, bus_list) { in pci_bus_restore_locked()
5602 if (dev->subordinate) { in pci_bus_restore_locked()
5604 pci_bus_restore_locked(dev->subordinate); in pci_bus_restore_locked()
5610 * Save and disable devices from the top of the tree down while holding
5617 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_save_and_disable_locked()
5618 if (!dev->slot || dev->slot != slot) in pci_slot_save_and_disable_locked()
5621 if (dev->subordinate) in pci_slot_save_and_disable_locked()
5622 pci_bus_save_and_disable_locked(dev->subordinate); in pci_slot_save_and_disable_locked()
5635 list_for_each_entry(dev, &slot->bus->devices, bus_list) { in pci_slot_restore_locked()
5636 if (!dev->slot || dev->slot != slot) in pci_slot_restore_locked()
5639 if (dev->subordinate) { in pci_slot_restore_locked()
5641 pci_bus_restore_locked(dev->subordinate); in pci_slot_restore_locked()
5646 static int pci_slot_reset(struct pci_slot *slot, bool probe) in pci_slot_reset()
5648 int rc; in pci_slot_reset()
5651 return -ENOTTY; in pci_slot_reset()
5658 rc = pci_reset_hotplug_slot(slot->hotplug, probe); in pci_slot_reset()
5667 * pci_probe_reset_slot - probe whether a PCI slot can be reset
5672 int pci_probe_reset_slot(struct pci_slot *slot) in pci_probe_reset_slot()
5679 * __pci_reset_slot - Try to reset a PCI slot
5687 * function of the slot and any subordinate buses behind the slot are reset
5688 * through this function. PCI config space of all devices in the slot and
5689 * behind the slot is saved before and restored after reset.
5691 * Same as above except return -EAGAIN if the slot cannot be locked
5693 static int __pci_reset_slot(struct pci_slot *slot) in __pci_reset_slot()
5695 int rc; in __pci_reset_slot()
5704 rc = pci_reset_hotplug_slot(slot->hotplug, PCI_RESET_DO_RESET); in __pci_reset_slot()
5708 rc = -EAGAIN; in __pci_reset_slot()
5713 static int pci_bus_reset(struct pci_bus *bus, bool probe) in pci_bus_reset()
5715 int ret; in pci_bus_reset()
5717 if (!bus->self || !pci_bus_resettable(bus)) in pci_bus_reset()
5718 return -ENOTTY; in pci_bus_reset()
5727 ret = pci_bridge_secondary_bus_reset(bus->self); in pci_bus_reset()
5735 * pci_bus_error_reset - reset the bridge's subordinate bus
5742 int pci_bus_error_reset(struct pci_dev *bridge) in pci_bus_error_reset()
5744 struct pci_bus *bus = bridge->subordinate; in pci_bus_error_reset()
5748 return -ENOTTY; in pci_bus_error_reset()
5751 if (list_empty(&bus->slots)) in pci_bus_error_reset()
5754 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5758 list_for_each_entry(slot, &bus->slots, list) in pci_bus_error_reset()
5766 return pci_bus_reset(bridge->subordinate, PCI_RESET_DO_RESET); in pci_bus_error_reset()
5770 * pci_probe_reset_bus - probe whether a PCI bus can be reset
5775 int pci_probe_reset_bus(struct pci_bus *bus) in pci_probe_reset_bus()
5782 * __pci_reset_bus - Try to reset a PCI bus
5785 * Same as above except return -EAGAIN if the bus cannot be locked
5787 int __pci_reset_bus(struct pci_bus *bus) in __pci_reset_bus()
5789 int rc; in __pci_reset_bus()
5798 rc = pci_bridge_secondary_bus_reset(bus->self); in __pci_reset_bus()
5802 rc = -EAGAIN; in __pci_reset_bus()
5808 * pci_reset_bus - Try to reset a PCI bus
5811 * Same as above except return -EAGAIN if the bus cannot be locked
5813 int pci_reset_bus(struct pci_dev *pdev) in pci_reset_bus()
5815 return (!pci_probe_reset_slot(pdev->slot)) ? in pci_reset_bus()
5816 __pci_reset_slot(pdev->slot) : __pci_reset_bus(pdev->bus); in pci_reset_bus()
5821 * pcix_get_max_mmrbc - get PCI-X maximum designed memory read byte count
5827 int pcix_get_max_mmrbc(struct pci_dev *dev) in pcix_get_max_mmrbc()
5829 int cap; in pcix_get_max_mmrbc()
5834 return -EINVAL; in pcix_get_max_mmrbc()
5837 return -EINVAL; in pcix_get_max_mmrbc()
5844 * pcix_get_mmrbc - get PCI-X maximum memory read byte count
5850 int pcix_get_mmrbc(struct pci_dev *dev) in pcix_get_mmrbc()
5852 int cap; in pcix_get_mmrbc()
5857 return -EINVAL; in pcix_get_mmrbc()
5860 return -EINVAL; in pcix_get_mmrbc()
5867 * pcix_set_mmrbc - set PCI-X maximum memory read byte count
5870 * valid values are 512, 1024, 2048, 4096
5875 int pcix_set_mmrbc(struct pci_dev *dev, int mmrbc) in pcix_set_mmrbc()
5877 int cap; in pcix_set_mmrbc()
5882 return -EINVAL; in pcix_set_mmrbc()
5884 v = ffs(mmrbc) - 10; in pcix_set_mmrbc()
5888 return -EINVAL; in pcix_set_mmrbc()
5891 return -EINVAL; in pcix_set_mmrbc()
5894 return -E2BIG; in pcix_set_mmrbc()
5897 return -EINVAL; in pcix_set_mmrbc()
5901 if (v > o && (dev->bus->bus_flags & PCI_BUS_FLAGS_NO_MMRBC)) in pcix_set_mmrbc()
5902 return -EIO; in pcix_set_mmrbc()
5907 return -EIO; in pcix_set_mmrbc()
5914 * pcie_get_readrq - get PCI Express read request size
5919 int pcie_get_readrq(struct pci_dev *dev) in pcie_get_readrq()
5930 * pcie_set_readrq - set PCI Express maximum memory read request
5933 * valid values are 128, 256, 512, 1024, 2048, 4096
5937 int pcie_set_readrq(struct pci_dev *dev, int rq) in pcie_set_readrq()
5940 int ret; in pcie_set_readrq()
5941 struct pci_host_bridge *bridge = pci_find_host_bridge(dev->bus); in pcie_set_readrq()
5944 return -EINVAL; in pcie_set_readrq()
5952 int mps = pcie_get_mps(dev); in pcie_set_readrq()
5958 v = FIELD_PREP(PCI_EXP_DEVCTL_READRQ, ffs(rq) - 8); in pcie_set_readrq()
5960 if (bridge->no_inc_mrrs) { in pcie_set_readrq()
5961 int max_mrrs = pcie_get_readrq(dev); in pcie_set_readrq()
5965 return -EINVAL; in pcie_set_readrq()
5977 * pcie_get_mps - get PCI Express maximum payload size
5982 int pcie_get_mps(struct pci_dev *dev) in pcie_get_mps()
5993 * pcie_set_mps - set PCI Express maximum payload size
5996 * valid values are 128, 256, 512, 1024, 2048, 4096
6000 int pcie_set_mps(struct pci_dev *dev, int mps) in pcie_set_mps()
6003 int ret; in pcie_set_mps()
6006 return -EINVAL; in pcie_set_mps()
6008 v = ffs(mps) - 8; in pcie_set_mps()
6009 if (v > dev->pcie_mpss) in pcie_set_mps()
6010 return -EINVAL; in pcie_set_mps()
6025 int pcie_link_speed_mbps(struct pci_dev *pdev) in pcie_link_speed_mbps()
6028 int err; in pcie_link_speed_mbps()
6039 * pcie_bandwidth_available - determine minimum link settings of a PCIe
6040 * device and its bandwidth limitation
6046 * Walk up the PCI device chain and find the point where the minimum
6047 * bandwidth is available. Return the bandwidth available there and (if
6048 * limiting_dev, speed, and width pointers are supplied) information about
6096 * pcie_get_supported_speeds - query Supported Link Speed Vector
6108 * Speeds field in Link Capabilities is used and only 2.5 GT/s and 5.0 GT/s
6132 /* PCIe r3.0-compliant */ in pcie_get_supported_speeds()
6146 * pcie_get_speed_cap - query for the PCI device's link speed capability
6155 return PCIE_LNKCAP2_SLS2SPEED(dev->supported_speeds); in pcie_get_speed_cap()
6160 * pcie_get_width_cap - query for the PCI device's link width capability
6179 * pcie_bandwidth_capable - calculate a PCI device's link bandwidth capability
6185 * and width, multiplying them, and applying encoding overhead. The result
6202 * __pcie_print_link_status - Report the PCI device's link speed and width
6207 * capable of, report the device's maximum possible bandwidth and the
6209 * the available bandwidth, even if the device isn't constrained.
6222 if (dev->bus && dev->bus->flit_mode) in __pcie_print_link_status()
6239 * pcie_print_link_status - Report the PCI device's link speed and width
6251 * pci_select_bars - Make BAR mask from the type of resource
6257 int pci_select_bars(struct pci_dev *dev, unsigned long flags) in pci_select_bars()
6259 int i, bars = 0; in pci_select_bars()
6275 static int pci_set_vga_state_arch(struct pci_dev *dev, bool decode, in pci_set_vga_state_arch()
6276 unsigned int command_bits, u32 flags) in pci_set_vga_state_arch()
6285 * pci_set_vga_state - set VGA decode state on device and parents if requested
6288 * @command_bits: PCI_COMMAND_IO and/or PCI_COMMAND_MEMORY
6289 * @flags: traverse ancestors and change bridges
6292 int pci_set_vga_state(struct pci_dev *dev, bool decode, in pci_set_vga_state()
6293 unsigned int command_bits, u32 flags) in pci_set_vga_state()
6298 int rc; in pci_set_vga_state()
6319 bus = dev->bus; in pci_set_vga_state()
6321 bridge = bus->self; in pci_set_vga_state()
6332 bus = bus->parent; in pci_set_vga_state()
6345 adev = ACPI_COMPANION(&pdev->dev); in pci_pr3_present()
6349 return adev->power.flags.power_resources && in pci_pr3_present()
6350 acpi_has_method(adev->handle, "_PR3"); in pci_pr3_present()
6356 * pci_add_dma_alias - Add a DMA devfn alias for a device
6358 * @devfn_from: alias slot and function
6361 * This helper encodes an 8-bit devfn as a bit number in dma_alias_mask
6362 * which is used to program permissible bus-devfn source addresses for DMA
6364 * and are useful for devices generating DMA requests beyond or different
6365 * from their logical bus-devfn. Examples include device quirks where the
6366 * device simply uses the wrong devfn, as well as non-transparent bridges
6370 * prior to any potential DMA mapping and therefore prior to driver probing
6376 unsigned int nr_devfns) in pci_add_dma_alias()
6378 int devfn_to; in pci_add_dma_alias()
6380 nr_devfns = min(nr_devfns, (unsigned int)MAX_NR_DEVFNS - devfn_from); in pci_add_dma_alias()
6381 devfn_to = devfn_from + nr_devfns - 1; in pci_add_dma_alias()
6383 if (!dev->dma_alias_mask) in pci_add_dma_alias()
6384 dev->dma_alias_mask = bitmap_zalloc(MAX_NR_DEVFNS, GFP_KERNEL); in pci_add_dma_alias()
6385 if (!dev->dma_alias_mask) { in pci_add_dma_alias()
6390 bitmap_set(dev->dma_alias_mask, devfn_from, nr_devfns); in pci_add_dma_alias()
6403 return (dev1->dma_alias_mask && in pci_devs_are_dma_aliases()
6404 test_bit(dev2->devfn, dev1->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6405 (dev2->dma_alias_mask && in pci_devs_are_dma_aliases()
6406 test_bit(dev1->devfn, dev2->dma_alias_mask)) || in pci_devs_are_dma_aliases()
6419 return pci_bus_read_dev_vendor_id(pdev->bus, pdev->devfn, &v, 0); in pci_device_is_present()
6425 struct pci_dev *bridge = dev->bus->self; in pci_ignore_hotplug()
6427 dev->ignore_hotplug = 1; in pci_ignore_hotplug()
6430 bridge->ignore_hotplug = 1; in pci_ignore_hotplug()
6435 * pci_real_dma_dev - Get PCI DMA device for PCI device
6438 * Permits the platform to provide architecture-specific functionality to
6455 * Arches that don't want to expose struct resource to userland as-is in
6456 * sysfs and /proc can implement their own pci_resource_to_user().
6458 void __weak pci_resource_to_user(const struct pci_dev *dev, int bar, in pci_resource_to_user()
6462 *start = rsrc->start; in pci_resource_to_user()
6463 *end = rsrc->end; in pci_resource_to_user()
6470 * pci_specified_resource_alignment - get resource alignment specified by user.
6480 int align_order, count; in pci_specified_resource_alignment()
6483 int ret; in pci_specified_resource_alignment()
6531 static void pci_request_resource_alignment(struct pci_dev *dev, int bar, in pci_request_resource_alignment()
6534 struct resource *r = &dev->resource[bar]; in pci_request_resource_alignment()
6538 if (!(r->flags & IORESOURCE_MEM)) in pci_request_resource_alignment()
6541 if (r->flags & IORESOURCE_PCI_FIXED) { in pci_request_resource_alignment()
6567 * 2) Retain the resource size, but use IORESOURCE_STARTALIGN and in pci_request_resource_alignment()
6568 * set r->start to the desired alignment. By itself this in pci_request_resource_alignment()
6574 * the "pci=resource_alignment" argument, "resize" is true and we in pci_request_resource_alignment()
6576 * devices and we use the second. in pci_request_resource_alignment()
6583 r->start = 0; in pci_request_resource_alignment()
6584 r->end = align - 1; in pci_request_resource_alignment()
6586 r->flags &= ~IORESOURCE_SIZEALIGN; in pci_request_resource_alignment()
6587 r->flags |= IORESOURCE_STARTALIGN; in pci_request_resource_alignment()
6590 r->flags |= IORESOURCE_UNSET; in pci_request_resource_alignment()
6594 * This function disables memory decoding and releases memory resources
6597 * Later on, the kernel will assign page-aligned memory resource back
6602 int i; in pci_reassigndev_resource_alignment()
6609 * VF BARs are read-only zero according to SR-IOV spec r1.1, sec in pci_reassigndev_resource_alignment()
6611 * described by the VF BARx register in the PF's SR-IOV capability. in pci_reassigndev_resource_alignment()
6614 if (dev->is_virtfn) in pci_reassigndev_resource_alignment()
6622 if (dev->hdr_type == PCI_HEADER_TYPE_NORMAL && in pci_reassigndev_resource_alignment()
6623 (dev->class >> 8) == PCI_CLASS_BRIDGE_HOST) { in pci_reassigndev_resource_alignment()
6640 if (dev->hdr_type == PCI_HEADER_TYPE_BRIDGE) { in pci_reassigndev_resource_alignment()
6642 r = &dev->resource[i]; in pci_reassigndev_resource_alignment()
6643 if (!(r->flags & IORESOURCE_MEM)) in pci_reassigndev_resource_alignment()
6645 r->flags |= IORESOURCE_UNSET; in pci_reassigndev_resource_alignment()
6646 r->end = resource_size(r) - 1; in pci_reassigndev_resource_alignment()
6647 r->start = 0; in pci_reassigndev_resource_alignment()
6670 if (count >= (PAGE_SIZE - 1)) in resource_alignment_store()
6671 return -EINVAL; in resource_alignment_store()
6675 return -ENOMEM; in resource_alignment_store()
6698 static int __init pci_resource_alignment_sysfs_init(void) in pci_resource_alignment_sysfs_init()
6719 int domain_nr; in of_pci_reserve_static_domain_nr()
6734 static int of_pci_bus_find_domain_nr(struct device *parent) in of_pci_bus_find_domain_nr()
6737 int domain_nr; in of_pci_bus_find_domain_nr()
6751 domain_nr = of_get_pci_domain_nr(parent->of_node); in of_pci_bus_find_domain_nr()
6767 static void of_pci_bus_release_domain_nr(struct device *parent, int domain_nr) in of_pci_bus_release_domain_nr()
6773 if (of_get_pci_domain_nr(parent->of_node) == domain_nr) in of_pci_bus_release_domain_nr()
6779 int pci_bus_find_domain_nr(struct pci_bus *bus, struct device *parent) in pci_bus_find_domain_nr()
6785 void pci_bus_release_domain_nr(struct device *parent, int domain_nr) in pci_bus_release_domain_nr()
6794 * pci_ext_cfg_avail - can we access extended PCI config space?
6800 int __weak pci_ext_cfg_avail(void) in pci_ext_cfg_avail()
6810 static int __init pci_setup(char *str) in pci_setup()
6883 * 'resource_alignment_param' and 'disable_acs_redir_param' are initialized
6887 * service available during an early_param() call. So we allocate memory and
6888 * copy the variable here before the init section is freed.
6891 static int __init pci_realloc_setup_params(void) in pci_realloc_setup_params()