pci/controller/pcie-mediatek-gen3.c

3  * MediaTek PCIe host controller driver.
132 /* Time in ms needed to complete PCIe reset on EN7581 SoC */
149  * @power_up: pcie power_up callback
151  * @flags: pcie device flags.
154 	int (*power_up)(struct mtk_gen3_pcie *pcie);
175  * struct mtk_gen3_pcie - PCIe port information
176  * @dev: pointer to PCIe device
182  * @clks: PCIe clocks
183  * @num_clks: PCIe clocks count for this port
184  * @max_link_speed: Maximum link speed (PCIe Gen) for this port
185  * @num_lanes: Number of PCIe lanes for this port
186  * @irq: PCIe controller interrupt number
265 	struct mtk_gen3_pcie *pcie = bus->sysdata;  in mtk_pcie_config_tlp_header()  local
274 	writel_relaxed(val, pcie->base + PCIE_CFGNUM_REG);  in mtk_pcie_config_tlp_header()
280 	struct mtk_gen3_pcie *pcie = bus->sysdata;  in mtk_pcie_map_bus()  local
282 	return pcie->base + PCIE_CFG_OFFSET_ADDR + where;  in mtk_pcie_map_bus()
310 static int mtk_pcie_set_trans_table(struct mtk_gen3_pcie *pcie,  in mtk_pcie_set_trans_table()  argument
334 			dev_err(pcie->dev, "illegal table size %#llx\n",  in mtk_pcie_set_trans_table()
339 		table = pcie->base + PCIE_TRANS_TABLE_BASE_REG + *num * PCIE_ATR_TLB_SET_OFFSET;  in mtk_pcie_set_trans_table()
355 		dev_dbg(pcie->dev, "set %s trans window[%d]: cpu_addr = %#llx, pci_addr = %#llx, size = %#llx\n",  in mtk_pcie_set_trans_table()
367 		dev_warn(pcie->dev, "not enough translate table for addr: %#llx, limited to [%d]\n",  in mtk_pcie_set_trans_table()
373 static void mtk_pcie_enable_msi(struct mtk_gen3_pcie *pcie)  in mtk_pcie_enable_msi()  argument
379 		struct mtk_msi_set *msi_set = &pcie->msi_sets[i];  in mtk_pcie_enable_msi()
381 		msi_set->base = pcie->base + PCIE_MSI_SET_BASE_REG +  in mtk_pcie_enable_msi()
383 		msi_set->msg_addr = pcie->reg_base + PCIE_MSI_SET_BASE_REG +  in mtk_pcie_enable_msi()
389 			       pcie->base + PCIE_MSI_SET_ADDR_HI_BASE +  in mtk_pcie_enable_msi()
393 	val = readl_relaxed(pcie->base + PCIE_MSI_SET_ENABLE_REG);  in mtk_pcie_enable_msi()
395 	writel_relaxed(val, pcie->base + PCIE_MSI_SET_ENABLE_REG);  in mtk_pcie_enable_msi()
397 	val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);  in mtk_pcie_enable_msi()
399 	writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);  in mtk_pcie_enable_msi()
402 static int mtk_pcie_startup_port(struct mtk_gen3_pcie *pcie)  in mtk_pcie_startup_port()  argument
405 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);  in mtk_pcie_startup_port()
410 	/* Set as RC mode and set controller PCIe Gen speed restriction, if any */  in mtk_pcie_startup_port()
411 	val = readl_relaxed(pcie->base + PCIE_SETTING_REG);  in mtk_pcie_startup_port()
413 	if (pcie->max_link_speed) {  in mtk_pcie_startup_port()
417 		if (pcie->max_link_speed >= 2)  in mtk_pcie_startup_port()
419 					  GENMASK(pcie->max_link_speed - 2, 0));  in mtk_pcie_startup_port()
421 	if (pcie->num_lanes) {  in mtk_pcie_startup_port()
425 		if (pcie->num_lanes > 1)  in mtk_pcie_startup_port()
427 					  GENMASK(fls(pcie->num_lanes >> 2), 0));  in mtk_pcie_startup_port()
429 	writel_relaxed(val, pcie->base + PCIE_SETTING_REG);  in mtk_pcie_startup_port()
432 	if (pcie->max_link_speed) {  in mtk_pcie_startup_port()
433 		val = readl_relaxed(pcie->base + PCIE_CONF_LINK2_CTL_STS);  in mtk_pcie_startup_port()
435 		val |= FIELD_PREP(PCIE_CONF_LINK2_LCR2_LINK_SPEED, pcie->max_link_speed);  in mtk_pcie_startup_port()
436 		writel_relaxed(val, pcie->base + PCIE_CONF_LINK2_CTL_STS);  in mtk_pcie_startup_port()
440 	val = readl_relaxed(pcie->base + PCIE_PCI_IDS_1);  in mtk_pcie_startup_port()
443 	writel_relaxed(val, pcie->base + PCIE_PCI_IDS_1);  in mtk_pcie_startup_port()
446 	val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);  in mtk_pcie_startup_port()
448 	writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);  in mtk_pcie_startup_port()
451 	val = readl_relaxed(pcie->base + PCIE_MISC_CTRL_REG);  in mtk_pcie_startup_port()
453 	writel_relaxed(val, pcie->base + PCIE_MISC_CTRL_REG);  in mtk_pcie_startup_port()
457 	 * causing occasional PCIe link down. In order to overcome the issue,  in mtk_pcie_startup_port()
459 	 * PCIe block is reset using en7523_reset_assert() and  in mtk_pcie_startup_port()
462 	if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {  in mtk_pcie_startup_port()
464 		val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);  in mtk_pcie_startup_port()
467 		writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);  in mtk_pcie_startup_port()
470 		 * Described in PCIe CEM specification revision 6.0.  in mtk_pcie_startup_port()
480 		writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);  in mtk_pcie_startup_port()
484 	err = readl_poll_timeout(pcie->base + PCIE_LINK_STATUS_REG, val,  in mtk_pcie_startup_port()
491 		val = readl_relaxed(pcie->base + PCIE_LTSSM_STATUS_REG);  in mtk_pcie_startup_port()
495 		dev_err(pcie->dev,  in mtk_pcie_startup_port()
496 			"PCIe link down, current LTSSM state: %s (%#x)\n",  in mtk_pcie_startup_port()
501 	mtk_pcie_enable_msi(pcie);  in mtk_pcie_startup_port()
503 	/* Set PCIe translation windows */  in mtk_pcie_startup_port()
520 		err = mtk_pcie_set_trans_table(pcie, cpu_addr, pci_addr, size,  in mtk_pcie_startup_port()
558 	struct mtk_gen3_pcie *pcie = data->domain->host_data;  in mtk_compose_msi_msg()  local
566 	dev_dbg(pcie->dev, "msi#%#lx address_hi %#x address_lo %#x data %d\n",  in mtk_compose_msi_msg()
583 	struct mtk_gen3_pcie *pcie = data->domain->host_data;  in mtk_msi_bottom_irq_mask()  local
589 	raw_spin_lock_irqsave(&pcie->irq_lock, flags);  in mtk_msi_bottom_irq_mask()
593 	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);  in mtk_msi_bottom_irq_mask()
599 	struct mtk_gen3_pcie *pcie = data->domain->host_data;  in mtk_msi_bottom_irq_unmask()  local
605 	raw_spin_lock_irqsave(&pcie->irq_lock, flags);  in mtk_msi_bottom_irq_unmask()
609 	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);  in mtk_msi_bottom_irq_unmask()
624 	struct mtk_gen3_pcie *pcie = domain->host_data;  in mtk_msi_bottom_domain_alloc()  local
628 	mutex_lock(&pcie->lock);  in mtk_msi_bottom_domain_alloc()
630 	hwirq = bitmap_find_free_region(pcie->msi_irq_in_use, PCIE_MSI_IRQS_NUM,  in mtk_msi_bottom_domain_alloc()
633 	mutex_unlock(&pcie->lock);  in mtk_msi_bottom_domain_alloc()
639 	msi_set = &pcie->msi_sets[set_idx];  in mtk_msi_bottom_domain_alloc()
652 	struct mtk_gen3_pcie *pcie = domain->host_data;  in mtk_msi_bottom_domain_free()  local
655 	mutex_lock(&pcie->lock);  in mtk_msi_bottom_domain_free()
657 	bitmap_release_region(pcie->msi_irq_in_use, data->hwirq,  in mtk_msi_bottom_domain_free()
660 	mutex_unlock(&pcie->lock);  in mtk_msi_bottom_domain_free()
672 	struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);  in mtk_intx_mask()  local
676 	raw_spin_lock_irqsave(&pcie->irq_lock, flags);  in mtk_intx_mask()
677 	val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);  in mtk_intx_mask()
679 	writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);  in mtk_intx_mask()
680 	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);  in mtk_intx_mask()
685 	struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);  in mtk_intx_unmask()  local
689 	raw_spin_lock_irqsave(&pcie->irq_lock, flags);  in mtk_intx_unmask()
690 	val = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);  in mtk_intx_unmask()
692 	writel_relaxed(val, pcie->base + PCIE_INT_ENABLE_REG);  in mtk_intx_unmask()
693 	raw_spin_unlock_irqrestore(&pcie->irq_lock, flags);  in mtk_intx_unmask()
706 	struct mtk_gen3_pcie *pcie = irq_data_get_irq_chip_data(data);  in mtk_intx_eoi()  local
710 	writel_relaxed(BIT(hwirq), pcie->base + PCIE_INT_STATUS_REG);  in mtk_intx_eoi()
733 static int mtk_pcie_init_irq_domains(struct mtk_gen3_pcie *pcie)  in mtk_pcie_init_irq_domains()  argument
735 	struct device *dev = pcie->dev;  in mtk_pcie_init_irq_domains()
739 	raw_spin_lock_init(&pcie->irq_lock);  in mtk_pcie_init_irq_domains()
748 	pcie->intx_domain = irq_domain_add_linear(intc_node, PCI_NUM_INTX,  in mtk_pcie_init_irq_domains()
749 						  &intx_domain_ops, pcie);  in mtk_pcie_init_irq_domains()
750 	if (!pcie->intx_domain) {  in mtk_pcie_init_irq_domains()
757 	mutex_init(&pcie->lock);  in mtk_pcie_init_irq_domains()
759 	pcie->msi_bottom_domain = irq_domain_add_linear(node, PCIE_MSI_IRQS_NUM,  in mtk_pcie_init_irq_domains()
760 				  &mtk_msi_bottom_domain_ops, pcie);  in mtk_pcie_init_irq_domains()
761 	if (!pcie->msi_bottom_domain) {  in mtk_pcie_init_irq_domains()
767 	pcie->msi_domain = pci_msi_create_irq_domain(dev->fwnode,  in mtk_pcie_init_irq_domains()
769 						     pcie->msi_bottom_domain);  in mtk_pcie_init_irq_domains()
770 	if (!pcie->msi_domain) {  in mtk_pcie_init_irq_domains()
780 	irq_domain_remove(pcie->msi_bottom_domain);  in mtk_pcie_init_irq_domains()
782 	irq_domain_remove(pcie->intx_domain);  in mtk_pcie_init_irq_domains()
788 static void mtk_pcie_irq_teardown(struct mtk_gen3_pcie *pcie)  in mtk_pcie_irq_teardown()  argument
790 	irq_set_chained_handler_and_data(pcie->irq, NULL, NULL);  in mtk_pcie_irq_teardown()
792 	if (pcie->intx_domain)  in mtk_pcie_irq_teardown()
793 		irq_domain_remove(pcie->intx_domain);  in mtk_pcie_irq_teardown()
795 	if (pcie->msi_domain)  in mtk_pcie_irq_teardown()
796 		irq_domain_remove(pcie->msi_domain);  in mtk_pcie_irq_teardown()
798 	if (pcie->msi_bottom_domain)  in mtk_pcie_irq_teardown()
799 		irq_domain_remove(pcie->msi_bottom_domain);  in mtk_pcie_irq_teardown()
801 	irq_dispose_mapping(pcie->irq);  in mtk_pcie_irq_teardown()
804 static void mtk_pcie_msi_handler(struct mtk_gen3_pcie *pcie, int set_idx)  in mtk_pcie_msi_handler()  argument
806 	struct mtk_msi_set *msi_set = &pcie->msi_sets[set_idx];  in mtk_pcie_msi_handler()
821 			generic_handle_domain_irq(pcie->msi_bottom_domain, hwirq);  in mtk_pcie_msi_handler()
828 	struct mtk_gen3_pcie *pcie = irq_desc_get_handler_data(desc);  in mtk_pcie_irq_handler()  local
835 	status = readl_relaxed(pcie->base + PCIE_INT_STATUS_REG);  in mtk_pcie_irq_handler()
838 		generic_handle_domain_irq(pcie->intx_domain,  in mtk_pcie_irq_handler()
844 		mtk_pcie_msi_handler(pcie, irq_bit - PCIE_MSI_SHIFT);  in mtk_pcie_irq_handler()
846 		writel_relaxed(BIT(irq_bit), pcie->base + PCIE_INT_STATUS_REG);  in mtk_pcie_irq_handler()
852 static int mtk_pcie_setup_irq(struct mtk_gen3_pcie *pcie)  in mtk_pcie_setup_irq()  argument
854 	struct device *dev = pcie->dev;  in mtk_pcie_setup_irq()
858 	err = mtk_pcie_init_irq_domains(pcie);  in mtk_pcie_setup_irq()
862 	pcie->irq = platform_get_irq(pdev, 0);  in mtk_pcie_setup_irq()
863 	if (pcie->irq < 0)  in mtk_pcie_setup_irq()
864 		return pcie->irq;  in mtk_pcie_setup_irq()
866 	irq_set_chained_handler_and_data(pcie->irq, mtk_pcie_irq_handler, pcie);  in mtk_pcie_setup_irq()
871 static int mtk_pcie_parse_port(struct mtk_gen3_pcie *pcie)  in mtk_pcie_parse_port()  argument
873 	int i, ret, num_resets = pcie->soc->phy_resets.num_resets;  in mtk_pcie_parse_port()
874 	struct device *dev = pcie->dev;  in mtk_pcie_parse_port()
879 	regs = platform_get_resource_byname(pdev, IORESOURCE_MEM, "pcie-mac");  in mtk_pcie_parse_port()
882 	pcie->base = devm_ioremap_resource(dev, regs);  in mtk_pcie_parse_port()
883 	if (IS_ERR(pcie->base)) {  in mtk_pcie_parse_port()
885 		return PTR_ERR(pcie->base);  in mtk_pcie_parse_port()
888 	pcie->reg_base = regs->start;  in mtk_pcie_parse_port()
891 		pcie->phy_resets[i].id = pcie->soc->phy_resets.id[i];  in mtk_pcie_parse_port()
894 							  pcie->phy_resets);  in mtk_pcie_parse_port()
900 	pcie->mac_reset = devm_reset_control_get_optional_exclusive(dev, "mac");  in mtk_pcie_parse_port()
901 	if (IS_ERR(pcie->mac_reset)) {  in mtk_pcie_parse_port()
902 		ret = PTR_ERR(pcie->mac_reset);  in mtk_pcie_parse_port()
909 	pcie->phy = devm_phy_optional_get(dev, "pcie-phy");  in mtk_pcie_parse_port()
910 	if (IS_ERR(pcie->phy)) {  in mtk_pcie_parse_port()
911 		ret = PTR_ERR(pcie->phy);  in mtk_pcie_parse_port()
918 	pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);  in mtk_pcie_parse_port()
919 	if (pcie->num_clks < 0) {  in mtk_pcie_parse_port()
921 		return pcie->num_clks;  in mtk_pcie_parse_port()
930 			pcie->num_lanes = num_lanes;  in mtk_pcie_parse_port()
936 static int mtk_pcie_en7581_power_up(struct mtk_gen3_pcie *pcie)  in mtk_pcie_en7581_power_up()  argument
938 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);  in mtk_pcie_en7581_power_up()
939 	struct device *dev = pcie->dev;  in mtk_pcie_en7581_power_up()
950 	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_en7581_power_up()
951 				  pcie->phy_resets);  in mtk_pcie_en7581_power_up()
958 	 * hw to detect if a given address is accessible on PCIe controller.  in mtk_pcie_en7581_power_up()
980 	err = phy_init(pcie->phy);  in mtk_pcie_en7581_power_up()
986 	err = phy_power_on(pcie->phy);  in mtk_pcie_en7581_power_up()
992 	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_en7581_power_up()
993 					  pcie->phy_resets);  in mtk_pcie_en7581_power_up()
1012 	writel_relaxed(val, pcie->base + PCIE_EQ_PRESET_01_REG);  in mtk_pcie_en7581_power_up()
1018 	writel_relaxed(val, pcie->base + PCIE_PIPE4_PIE8_REG);  in mtk_pcie_en7581_power_up()
1020 	err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);  in mtk_pcie_en7581_power_up()
1027 	 * Airoha EN7581 performs PCIe reset via clk callbacks since it has a  in mtk_pcie_en7581_power_up()
1029 	 * complete the PCIe reset.  in mtk_pcie_en7581_power_up()
1038 	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_en7581_power_up()
1039 				  pcie->phy_resets);  in mtk_pcie_en7581_power_up()
1041 	phy_power_off(pcie->phy);  in mtk_pcie_en7581_power_up()
1043 	phy_exit(pcie->phy);  in mtk_pcie_en7581_power_up()
1048 static int mtk_pcie_power_up(struct mtk_gen3_pcie *pcie)  in mtk_pcie_power_up()  argument
1050 	struct device *dev = pcie->dev;  in mtk_pcie_power_up()
1057 	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_power_up()
1058 				  pcie->phy_resets);  in mtk_pcie_power_up()
1059 	reset_control_assert(pcie->mac_reset);  in mtk_pcie_power_up()
1063 	err = reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_power_up()
1064 					  pcie->phy_resets);  in mtk_pcie_power_up()
1070 	err = phy_init(pcie->phy);  in mtk_pcie_power_up()
1076 	err = phy_power_on(pcie->phy);  in mtk_pcie_power_up()
1083 	reset_control_deassert(pcie->mac_reset);  in mtk_pcie_power_up()
1088 	err = clk_bulk_prepare_enable(pcie->num_clks, pcie->clks);  in mtk_pcie_power_up()
1099 	reset_control_assert(pcie->mac_reset);  in mtk_pcie_power_up()
1100 	phy_power_off(pcie->phy);  in mtk_pcie_power_up()
1102 	phy_exit(pcie->phy);  in mtk_pcie_power_up()
1104 	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_power_up()
1105 				  pcie->phy_resets);  in mtk_pcie_power_up()
1110 static void mtk_pcie_power_down(struct mtk_gen3_pcie *pcie)  in mtk_pcie_power_down()  argument
1112 	clk_bulk_disable_unprepare(pcie->num_clks, pcie->clks);  in mtk_pcie_power_down()
1114 	pm_runtime_put_sync(pcie->dev);  in mtk_pcie_power_down()
1115 	pm_runtime_disable(pcie->dev);  in mtk_pcie_power_down()
1116 	reset_control_assert(pcie->mac_reset);  in mtk_pcie_power_down()
1118 	phy_power_off(pcie->phy);  in mtk_pcie_power_down()
1119 	phy_exit(pcie->phy);  in mtk_pcie_power_down()
1120 	reset_control_bulk_assert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_power_down()
1121 				  pcie->phy_resets);  in mtk_pcie_power_down()
1124 static int mtk_pcie_get_controller_max_link_speed(struct mtk_gen3_pcie *pcie)  in mtk_pcie_get_controller_max_link_speed()  argument
1129 	val = readl_relaxed(pcie->base + PCIE_BASE_CFG_REG);  in mtk_pcie_get_controller_max_link_speed()
1136 static int mtk_pcie_setup(struct mtk_gen3_pcie *pcie)  in mtk_pcie_setup()  argument
1140 	err = mtk_pcie_parse_port(pcie);  in mtk_pcie_setup()
1148 	reset_control_bulk_deassert(pcie->soc->phy_resets.num_resets,  in mtk_pcie_setup()
1149 				    pcie->phy_resets);  in mtk_pcie_setup()
1152 	err = pcie->soc->power_up(pcie);  in mtk_pcie_setup()
1156 	err = of_pci_get_max_link_speed(pcie->dev->of_node);  in mtk_pcie_setup()
1159 		max_speed = mtk_pcie_get_controller_max_link_speed(pcie);  in mtk_pcie_setup()
1163 			pcie->max_link_speed = err;  in mtk_pcie_setup()
1164 			dev_info(pcie->dev,  in mtk_pcie_setup()
1166 				 max_speed, pcie->max_link_speed);  in mtk_pcie_setup()
1171 	err = mtk_pcie_startup_port(pcie);  in mtk_pcie_setup()
1175 	err = mtk_pcie_setup_irq(pcie);  in mtk_pcie_setup()
1182 	mtk_pcie_power_down(pcie);  in mtk_pcie_setup()
1190 	struct mtk_gen3_pcie *pcie;  in mtk_pcie_probe()  local
1194 	host = devm_pci_alloc_host_bridge(dev, sizeof(*pcie));  in mtk_pcie_probe()
1198 	pcie = pci_host_bridge_priv(host);  in mtk_pcie_probe()
1200 	pcie->dev = dev;  in mtk_pcie_probe()
1201 	pcie->soc = device_get_match_data(dev);  in mtk_pcie_probe()
1202 	platform_set_drvdata(pdev, pcie);  in mtk_pcie_probe()
1204 	err = mtk_pcie_setup(pcie);  in mtk_pcie_probe()
1209 	host->sysdata = pcie;  in mtk_pcie_probe()
1213 		mtk_pcie_irq_teardown(pcie);  in mtk_pcie_probe()
1214 		mtk_pcie_power_down(pcie);  in mtk_pcie_probe()
1223 	struct mtk_gen3_pcie *pcie = platform_get_drvdata(pdev);  in mtk_pcie_remove()  local
1224 	struct pci_host_bridge *host = pci_host_bridge_from_priv(pcie);  in mtk_pcie_remove()
1231 	mtk_pcie_irq_teardown(pcie);  in mtk_pcie_remove()
1232 	mtk_pcie_power_down(pcie);  in mtk_pcie_remove()
1235 static void mtk_pcie_irq_save(struct mtk_gen3_pcie *pcie)  in mtk_pcie_irq_save()  argument
1239 	raw_spin_lock(&pcie->irq_lock);  in mtk_pcie_irq_save()
1241 	pcie->saved_irq_state = readl_relaxed(pcie->base + PCIE_INT_ENABLE_REG);  in mtk_pcie_irq_save()
1244 		struct mtk_msi_set *msi_set = &pcie->msi_sets[i];  in mtk_pcie_irq_save()
1250 	raw_spin_unlock(&pcie->irq_lock);  in mtk_pcie_irq_save()
1253 static void mtk_pcie_irq_restore(struct mtk_gen3_pcie *pcie)  in mtk_pcie_irq_restore()  argument
1257 	raw_spin_lock(&pcie->irq_lock);  in mtk_pcie_irq_restore()
1259 	writel_relaxed(pcie->saved_irq_state, pcie->base + PCIE_INT_ENABLE_REG);  in mtk_pcie_irq_restore()
1262 		struct mtk_msi_set *msi_set = &pcie->msi_sets[i];  in mtk_pcie_irq_restore()
1268 	raw_spin_unlock(&pcie->irq_lock);  in mtk_pcie_irq_restore()
1271 static int mtk_pcie_turn_off_link(struct mtk_gen3_pcie *pcie)  in mtk_pcie_turn_off_link()  argument
1275 	val = readl_relaxed(pcie->base + PCIE_ICMD_PM_REG);  in mtk_pcie_turn_off_link()
1277 	writel_relaxed(val, pcie->base + PCIE_ICMD_PM_REG);  in mtk_pcie_turn_off_link()
1280 	return readl_poll_timeout(pcie->base + PCIE_LTSSM_STATUS_REG, val,  in mtk_pcie_turn_off_link()
1288 	struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);  in mtk_pcie_suspend_noirq()  local
1293 	err = mtk_pcie_turn_off_link(pcie);  in mtk_pcie_suspend_noirq()
1295 		dev_err(pcie->dev, "cannot enter L2 state\n");  in mtk_pcie_suspend_noirq()
1299 	if (!(pcie->soc->flags & SKIP_PCIE_RSTB)) {  in mtk_pcie_suspend_noirq()
1301 		val = readl_relaxed(pcie->base + PCIE_RST_CTRL_REG);  in mtk_pcie_suspend_noirq()
1303 		writel_relaxed(val, pcie->base + PCIE_RST_CTRL_REG);  in mtk_pcie_suspend_noirq()
1306 	dev_dbg(pcie->dev, "entered L2 states successfully");  in mtk_pcie_suspend_noirq()
1308 	mtk_pcie_irq_save(pcie);  in mtk_pcie_suspend_noirq()
1309 	mtk_pcie_power_down(pcie);  in mtk_pcie_suspend_noirq()
1316 	struct mtk_gen3_pcie *pcie = dev_get_drvdata(dev);  in mtk_pcie_resume_noirq()  local
1319 	err = pcie->soc->power_up(pcie);  in mtk_pcie_resume_noirq()
1323 	err = mtk_pcie_startup_port(pcie);  in mtk_pcie_resume_noirq()
1325 		mtk_pcie_power_down(pcie);  in mtk_pcie_resume_noirq()
1329 	mtk_pcie_irq_restore(pcie);  in mtk_pcie_resume_noirq()
1359 	{ .compatible = "airoha,en7581-pcie", .data = &mtk_pcie_soc_en7581 },
1360 	{ .compatible = "mediatek,mt8192-pcie", .data = &mtk_pcie_soc_mt8192 },
1369 		.name = "mtk-pcie-gen3",
1377 MODULE_DESCRIPTION("MediaTek Gen3 PCIe host controller driver");