Lines Matching +full:ssc +full:- +full:internal
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Copyright (C) 2009 - 2019 Broadcom */
26 #include <linux/pci-ecam.h>
37 /* BRCM_PCIE_CAP_REGS - Offset for the mandatory capability config regs */
166 #define BRCM_INT_PCI_MSI_MASK GENMASK(BRCM_INT_PCI_MSI_NR - 1, 0)
168 32 - BRCM_INT_PCI_MSI_LEGACY_NR)
196 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX])
197 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA])
198 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1])
199 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG])
200 #define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE])
282 /* Internal PCIe Host Controller Information.*/
288 bool ssc; member
306 return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425; in is_bmips()
311 * non-linear values of PCIE_X_MISC_RC_BAR[123]_CONFIG_LO.SIZE
319 return (log2_in - 12) + 0x1c; in brcm_pcie_encode_ibar_size()
322 return log2_in - 15; in brcm_pcie_encode_ibar_size()
373 * Configures device for Spread Spectrum Clocking (SSC) mode; a negative
378 int pll, ssc; in brcm_pcie_set_ssc() local
382 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
387 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
394 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
400 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
405 ssc = FIELD_GET(SSC_STATUS_SSC_MASK, tmp); in brcm_pcie_set_ssc()
408 return ssc && pll ? 0 : -EIO; in brcm_pcie_set_ssc()
414 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
415 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
418 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
421 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
434 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
435 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
439 limit_addr_mb = (cpu_addr + size - 1) / SZ_1M; in brcm_pcie_set_outbound_win()
441 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
446 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
456 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
459 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
462 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
465 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
491 dev = msi->dev; in brcm_pcie_msi_isr()
493 status = readl(msi->intr_base + MSI_INT_STATUS); in brcm_pcie_msi_isr()
494 status >>= msi->legacy_shift; in brcm_pcie_msi_isr()
496 for_each_set_bit(bit, &status, msi->nr) { in brcm_pcie_msi_isr()
498 ret = generic_handle_domain_irq(msi->inner_domain, bit); in brcm_pcie_msi_isr()
510 msg->address_lo = lower_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
511 msg->address_hi = upper_32_bits(msi->target_addr); in brcm_msi_compose_msi_msg()
512 msg->data = (0xffff & PCIE_MISC_MSI_DATA_CONFIG_VAL_32) | data->hwirq; in brcm_msi_compose_msi_msg()
518 const int shift_amt = data->hwirq + msi->legacy_shift; in brcm_msi_ack_irq()
520 writel(1 << shift_amt, msi->intr_base + MSI_INT_CLR); in brcm_msi_ack_irq()
534 mutex_lock(&msi->lock); in brcm_msi_alloc()
535 hwirq = bitmap_find_free_region(msi->used, msi->nr, in brcm_msi_alloc()
537 mutex_unlock(&msi->lock); in brcm_msi_alloc()
545 mutex_lock(&msi->lock); in brcm_msi_free()
546 bitmap_release_region(msi->used, hwirq, order_base_2(nr_irqs)); in brcm_msi_free()
547 mutex_unlock(&msi->lock); in brcm_msi_free()
553 struct brcm_msi *msi = domain->host_data; in brcm_irq_domain_alloc()
563 &brcm_msi_bottom_irq_chip, domain->host_data, in brcm_irq_domain_alloc()
574 brcm_msi_free(msi, d->hwirq, nr_irqs); in brcm_irq_domain_free()
584 struct fwnode_handle *fwnode = of_node_to_fwnode(msi->np); in brcm_allocate_domains()
585 struct device *dev = msi->dev; in brcm_allocate_domains()
587 msi->inner_domain = irq_domain_add_linear(NULL, msi->nr, &msi_domain_ops, msi); in brcm_allocate_domains()
588 if (!msi->inner_domain) { in brcm_allocate_domains()
590 return -ENOMEM; in brcm_allocate_domains()
593 msi->msi_domain = pci_msi_create_irq_domain(fwnode, in brcm_allocate_domains()
595 msi->inner_domain); in brcm_allocate_domains()
596 if (!msi->msi_domain) { in brcm_allocate_domains()
598 irq_domain_remove(msi->inner_domain); in brcm_allocate_domains()
599 return -ENOMEM; in brcm_allocate_domains()
607 irq_domain_remove(msi->msi_domain); in brcm_free_domains()
608 irq_domain_remove(msi->inner_domain); in brcm_free_domains()
613 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
617 irq_set_chained_handler_and_data(msi->irq, NULL, NULL); in brcm_msi_remove()
623 u32 val = msi->legacy ? BRCM_INT_PCI_MSI_LEGACY_MASK : in brcm_msi_set_regs()
626 writel(val, msi->intr_base + MSI_INT_MASK_CLR); in brcm_msi_set_regs()
627 writel(val, msi->intr_base + MSI_INT_CLR); in brcm_msi_set_regs()
633 writel(lower_32_bits(msi->target_addr) | 0x1, in brcm_msi_set_regs()
634 msi->base + PCIE_MISC_MSI_BAR_CONFIG_LO); in brcm_msi_set_regs()
635 writel(upper_32_bits(msi->target_addr), in brcm_msi_set_regs()
636 msi->base + PCIE_MISC_MSI_BAR_CONFIG_HI); in brcm_msi_set_regs()
638 val = msi->legacy ? PCIE_MISC_MSI_DATA_CONFIG_VAL_8 : PCIE_MISC_MSI_DATA_CONFIG_VAL_32; in brcm_msi_set_regs()
639 writel(val, msi->base + PCIE_MISC_MSI_DATA_CONFIG); in brcm_msi_set_regs()
646 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
648 irq = irq_of_parse_and_map(dev->of_node, 1); in brcm_pcie_enable_msi()
651 return -ENODEV; in brcm_pcie_enable_msi()
656 return -ENOMEM; in brcm_pcie_enable_msi()
658 mutex_init(&msi->lock); in brcm_pcie_enable_msi()
659 msi->dev = dev; in brcm_pcie_enable_msi()
660 msi->base = pcie->base; in brcm_pcie_enable_msi()
661 msi->np = pcie->np; in brcm_pcie_enable_msi()
662 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
663 msi->irq = irq; in brcm_pcie_enable_msi()
664 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
672 if (msi->legacy) { in brcm_pcie_enable_msi()
673 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); in brcm_pcie_enable_msi()
674 msi->nr = BRCM_INT_PCI_MSI_LEGACY_NR; in brcm_pcie_enable_msi()
675 msi->legacy_shift = 24; in brcm_pcie_enable_msi()
677 msi->intr_base = msi->base + PCIE_MSI_INTR2_BASE; in brcm_pcie_enable_msi()
678 msi->nr = BRCM_INT_PCI_MSI_NR; in brcm_pcie_enable_msi()
679 msi->legacy_shift = 0; in brcm_pcie_enable_msi()
686 irq_set_chained_handler_and_data(msi->irq, brcm_pcie_msi_isr, msi); in brcm_pcie_enable_msi()
689 pcie->msi = msi; in brcm_pcie_enable_msi()
697 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
705 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
715 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus()
716 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
723 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm_pcie_map_bus()
728 idx = PCIE_ECAM_OFFSET(bus->number, devfn, 0); in brcm_pcie_map_bus()
736 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus()
737 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
744 /* An access to our HW w/o link-up will cause a CPU Abort */ in brcm7425_pcie_map_bus()
749 idx = PCIE_ECAM_OFFSET(bus->number, devfn, where); in brcm7425_pcie_map_bus()
760 if (pcie->bridge_reset) { in brcm_pcie_bridge_sw_init_set_generic()
762 ret = reset_control_assert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
764 ret = reset_control_deassert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
767 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", in brcm_pcie_bridge_sw_init_set_generic()
773 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
775 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
785 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
787 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
796 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
797 return -EINVAL; in brcm_pcie_perst_set_4908()
800 ret = reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
802 ret = reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
805 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", in brcm_pcie_perst_set_4908()
815 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
817 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
826 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
828 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
842 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); in brcm_pcie_post_setup_bcm2712()
847 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); in brcm_pcie_post_setup_bcm2712()
855 * Set L1SS sub-state timers to avoid lengthy state transitions, in brcm_pcie_post_setup_bcm2712()
858 tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); in brcm_pcie_post_setup_bcm2712()
861 writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); in brcm_pcie_post_setup_bcm2712()
869 b->size = size; in add_inbound_win()
870 b->cpu_addr = cpu_addr; in add_inbound_win()
871 b->pci_offset = pci_offset; in add_inbound_win()
881 struct device *dev = pcie->dev; in brcm_pcie_get_inbound_wins()
887 * The HW registers (and PCIe) use order-1 numbering for BARs. As such, in brcm_pcie_get_inbound_wins()
896 * internal registers of the SoC. This feature is deprecated, has in brcm_pcie_get_inbound_wins()
900 if (pcie->cfg->soc_base != BCM7712) in brcm_pcie_get_inbound_wins()
903 resource_list_for_each_entry(entry, &bridge->dma_ranges) { in brcm_pcie_get_inbound_wins()
904 u64 pcie_start = entry->res->start - entry->offset; in brcm_pcie_get_inbound_wins()
905 u64 cpu_start = entry->res->start; in brcm_pcie_get_inbound_wins()
907 size = resource_size(entry->res); in brcm_pcie_get_inbound_wins()
913 * offering a non-overlapping viewport to system memory. in brcm_pcie_get_inbound_wins()
917 if (pcie->cfg->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
920 if (n > pcie->cfg->num_inbound_wins) in brcm_pcie_get_inbound_wins()
925 dev_err(dev, "DT node has no dma-ranges\n"); in brcm_pcie_get_inbound_wins()
926 return -EINVAL; in brcm_pcie_get_inbound_wins()
930 * 7712 and newer chips do not have an internal memory mapping system in brcm_pcie_get_inbound_wins()
934 if (pcie->cfg->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
937 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_inbound_wins()
941 pcie->num_memc = 1; in brcm_pcie_get_inbound_wins()
942 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
944 pcie->num_memc = ret; in brcm_pcie_get_inbound_wins()
948 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
949 size += pcie->memc_size[i]; in brcm_pcie_get_inbound_wins()
952 size = 1ULL << fls64(size - 1); in brcm_pcie_get_inbound_wins()
963 * whatever the device-tree provides. This is because of an HW issue on in brcm_pcie_get_inbound_wins()
965 * firmware has to dynamically edit dma-ranges due to a bug on the in brcm_pcie_get_inbound_wins()
967 * lower 3GB of memory. Given this, we decided to keep the dma-ranges in brcm_pcie_get_inbound_wins()
968 * in check, avoiding hard to debug device-tree related issues in the in brcm_pcie_get_inbound_wins()
974 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_inbound_wins()
976 * represent system memory -- e.g. 3GB of memory requires a 4GB in brcm_pcie_get_inbound_wins()
977 * viewport -- we can map the outbound memory in or after 3GB and even in brcm_pcie_get_inbound_wins()
984 * - The best-case scenario, memory up to 3GB, is to place the inbound in brcm_pcie_get_inbound_wins()
985 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_inbound_wins()
989 * - If the system memory is 4GB or larger we cannot start the inbound in brcm_pcie_get_inbound_wins()
994 if (!size || (pci_offset & (size - 1)) || in brcm_pcie_get_inbound_wins()
998 return -EINVAL; in brcm_pcie_get_inbound_wins()
1016 return PCIE_MISC_RC_BAR1_CONFIG_LO + 8 * (bar - 1); in brcm_bar_reg_offset()
1018 return PCIE_MISC_RC_BAR4_CONFIG_LO + 8 * (bar - 4); in brcm_bar_reg_offset()
1024 return PCIE_MISC_UBUS_BAR1_CONFIG_REMAP + 8 * (bar - 1); in brcm_ubus_reg_offset()
1026 return PCIE_MISC_UBUS_BAR4_CONFIG_REMAP + 8 * (bar - 4); in brcm_ubus_reg_offset()
1033 void __iomem *base = pcie->base; in set_inbound_win_registers()
1057 if (pcie->cfg->soc_base == BCM7712) { in set_inbound_win_registers()
1072 void __iomem *base = pcie->base; in brcm_pcie_setup()
1081 ret = pcie->cfg->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
1086 if (pcie->cfg->soc_base == BCM2711) { in brcm_pcie_setup()
1087 ret = pcie->cfg->perst_set(pcie, 1); in brcm_pcie_setup()
1089 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1097 ret = pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1117 else if (pcie->cfg->soc_base == BCM2711) in brcm_pcie_setup()
1119 else if (pcie->cfg->soc_base == BCM7278) in brcm_pcie_setup()
1143 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
1144 return -EINVAL; in brcm_pcie_setup()
1148 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1149 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
1165 * account the rounding-up we're forced to perform). in brcm_pcie_setup()
1169 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
1171 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
1174 /* Don't advertise L0s capability if 'aspm-no-l0s' */ in brcm_pcie_setup()
1176 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1185 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1193 resource_list_for_each_entry(entry, &bridge->windows) { in brcm_pcie_setup()
1194 struct resource *res = entry->res; in brcm_pcie_setup()
1200 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1201 return -EINVAL; in brcm_pcie_setup()
1205 u64 start = res->start; in brcm_pcie_setup()
1213 start - entry->offset, in brcm_pcie_setup()
1217 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1218 res->start - entry->offset, in brcm_pcie_setup()
1223 /* PCIe->SCB endian mode for inbound window */ in brcm_pcie_setup()
1229 if (pcie->cfg->post_setup) { in brcm_pcie_setup()
1230 ret = pcie->cfg->post_setup(pcie); in brcm_pcie_setup()
1239 * This extends the timeout period for an access to an internal bus. This
1246 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1250 if (pcie->cfg->soc_base == BCM7712) in brcm_extend_rbus_timeout()
1254 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1259 static const char err_msg[] = "invalid 'brcm,clkreq-mode' DT string\n"; in brcm_config_clkreq()
1264 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1265 if (ret && ret != -EINVAL) { in brcm_config_clkreq()
1266 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1271 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1274 if (strcmp(mode, "no-l1ss") == 0) { in brcm_config_clkreq()
1276 * "no-l1ss" -- Provides Clock Power Management, L0s, and in brcm_config_clkreq()
1284 * We want to un-advertise L1 substates because if the OS in brcm_config_clkreq()
1287 * "no-l1ss" mode. in brcm_config_clkreq()
1289 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1291 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1295 * "default" -- Provides L0s, L1, and L1SS, but not in brcm_config_clkreq()
1307 * "safe" -- No power savings; refclk is driven by RC in brcm_config_clkreq()
1311 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1314 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1316 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1321 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1322 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1328 if (pcie->gen) in brcm_pcie_start_link()
1329 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1332 ret = pcie->cfg->perst_set(pcie, 0); in brcm_pcie_start_link()
1344 * configure RC. Intermittently check status for link-up, up to a in brcm_pcie_start_link()
1352 return -ENODEV; in brcm_pcie_start_link()
1357 if (pcie->ssc) { in brcm_pcie_start_link()
1362 dev_err(dev, "failed attempt to enter ssc mode\n"); in brcm_pcie_start_link()
1370 ssc_good ? "(SSC)" : "(!SSC)"); in brcm_pcie_start_link()
1390 sr->num_supplies = ARRAY_SIZE(supplies); in alloc_subdev_regulators()
1392 sr->supplies[i].supply = supplies[i]; in alloc_subdev_regulators()
1400 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus()
1401 struct device *dev = &bus->dev; in brcm_pcie_add_bus()
1405 if (!bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_add_bus()
1408 if (dev->of_node) { in brcm_pcie_add_bus()
1415 pcie->sr = sr; in brcm_pcie_add_bus()
1417 ret = regulator_bulk_get(dev, sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1420 pcie->sr = NULL; in brcm_pcie_add_bus()
1424 ret = regulator_bulk_enable(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1427 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_add_bus()
1428 pcie->sr = NULL; in brcm_pcie_add_bus()
1439 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus()
1440 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1441 struct device *dev = &bus->dev; in brcm_pcie_remove_bus()
1443 if (!sr || !bus->parent || !pci_is_root_bus(bus->parent)) in brcm_pcie_remove_bus()
1446 if (regulator_bulk_disable(sr->num_supplies, sr->supplies)) in brcm_pcie_remove_bus()
1448 regulator_bulk_free(sr->num_supplies, sr->supplies); in brcm_pcie_remove_bus()
1449 pcie->sr = NULL; in brcm_pcie_remove_bus()
1452 /* L23 is a low-power PCIe link state */
1455 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1475 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1488 const int beg = start ? 0 : PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS - 1; in brcm_phy_cntl()
1489 const int end = start ? PCIE_DVT_PMU_PCIE_PHY_CTRL_DAST_NFLDS : -1; in brcm_phy_cntl()
1492 void __iomem *base = pcie->base; in brcm_phy_cntl()
1495 for (i = beg; i != end; start ? i++ : i--) { in brcm_phy_cntl()
1507 ret = (tmp & combined_mask) == val ? 0 : -EIO; in brcm_phy_cntl()
1509 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1516 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1521 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1526 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1532 ret = pcie->cfg->perst_set(pcie, 1); in brcm_pcie_turn_off()
1546 if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) in brcm_pcie_turn_off()
1548 ret = pcie->cfg->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1557 if (device_may_wakeup(&dev->dev)) { in pci_dev_may_wakeup()
1559 dev_info(&dev->dev, "Possible wake-up device; regulators will not be disabled\n"); in pci_dev_may_wakeup()
1582 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1588 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1591 * downstream device is enabled as a wake-up source, do not in brcm_pcie_suspend_noirq()
1594 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1595 pci_walk_bus(bridge->bus, pci_dev_may_wakeup, in brcm_pcie_suspend_noirq()
1596 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1597 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1598 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1599 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1602 rret = reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1610 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1622 base = pcie->base; in brcm_pcie_resume_noirq()
1623 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1627 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1636 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1650 if (pcie->sr) { in brcm_pcie_resume_noirq()
1651 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1658 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1660 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1661 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1673 if (pcie->msi) in brcm_pcie_resume_noirq()
1674 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1679 if (pcie->sr) in brcm_pcie_resume_noirq()
1680 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1682 rret = reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1684 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); in brcm_pcie_resume_noirq()
1686 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1695 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1696 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1697 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1698 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1706 pci_stop_root_bus(bridge->bus); in brcm_pcie_remove()
1707 pci_remove_root_bus(bridge->bus); in brcm_pcie_remove()
1819 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1820 { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
1821 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1822 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1823 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1824 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1825 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1826 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1827 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1828 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1850 struct device_node *np = pdev->dev.of_node; in brcm_pcie_probe()
1856 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1858 return -ENOMEM; in brcm_pcie_probe()
1860 data = of_device_get_match_data(&pdev->dev); in brcm_pcie_probe()
1863 return -EINVAL; in brcm_pcie_probe()
1867 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1868 pcie->np = np; in brcm_pcie_probe()
1869 pcie->cfg = data; in brcm_pcie_probe()
1871 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1872 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1873 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1875 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1876 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1877 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1880 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1882 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1884 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1885 if (IS_ERR(pcie->rescal)) in brcm_pcie_probe()
1886 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1888 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1889 if (IS_ERR(pcie->perst_reset)) in brcm_pcie_probe()
1890 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1892 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); in brcm_pcie_probe()
1893 if (IS_ERR(pcie->bridge_reset)) in brcm_pcie_probe()
1894 return PTR_ERR(pcie->bridge_reset); in brcm_pcie_probe()
1896 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); in brcm_pcie_probe()
1897 if (IS_ERR(pcie->swinit_reset)) in brcm_pcie_probe()
1898 return PTR_ERR(pcie->swinit_reset); in brcm_pcie_probe()
1900 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1902 return dev_err_probe(&pdev->dev, ret, "could not enable clock\n"); in brcm_pcie_probe()
1904 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1906 if (pcie->swinit_reset) { in brcm_pcie_probe()
1907 ret = reset_control_assert(pcie->swinit_reset); in brcm_pcie_probe()
1909 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1910 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1917 ret = reset_control_deassert(pcie->swinit_reset); in brcm_pcie_probe()
1919 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1920 return dev_err_probe(&pdev->dev, ret, in brcm_pcie_probe()
1921 "could not de-assert reset 'swinit'\n"); in brcm_pcie_probe()
1925 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1927 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1928 return dev_err_probe(&pdev->dev, ret, "failed to deassert 'rescal'\n"); in brcm_pcie_probe()
1933 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1934 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1942 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1943 if (pcie->cfg->soc_base == BCM4908 && in brcm_pcie_probe()
1944 pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1945 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1946 ret = -ENODEV; in brcm_pcie_probe()
1951 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1953 if (msi_np == pcie->np) in brcm_pcie_probe()
1959 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1964 bridge->ops = pcie->cfg->soc_base == BCM7425 ? in brcm_pcie_probe()
1966 bridge->sysdata = pcie; in brcm_pcie_probe()
1972 ret = -ENODEV; in brcm_pcie_probe()
1998 .name = "brcm-pcie",