Lines Matching full:pcie
40 /* Broadcom STB PCIe Register Offsets */
161 /* PCIe parameters */
196 #define IDX_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_INDEX]) argument
197 #define DATA_ADDR(pcie) ((pcie)->cfg->offsets[EXT_CFG_DATA]) argument
198 #define PCIE_RGR1_SW_INIT_1(pcie) ((pcie)->cfg->offsets[RGR1_SW_INIT_1]) argument
199 #define HARD_DEBUG(pcie) ((pcie)->cfg->offsets[PCIE_HARD_DEBUG]) argument
200 #define INTR2_CPU_BASE(pcie) ((pcie)->cfg->offsets[PCIE_INTR2_CPU_BASE]) argument
240 * The RESCAL block is tied to PCIe controller #1, regardless of the number of
241 * controllers, and turning off PCIe controller #1 prevents access to the RESCAL
254 int (*perst_set)(struct brcm_pcie *pcie, u32 val);
255 int (*bridge_sw_init_set)(struct brcm_pcie *pcie, u32 val);
256 int (*post_setup)(struct brcm_pcie *pcie);
282 /* Internal PCIe Host Controller Information.*/
304 static inline bool is_bmips(const struct brcm_pcie *pcie) in is_bmips() argument
306 return pcie->cfg->soc_base == BCM7435 || pcie->cfg->soc_base == BCM7425; in is_bmips()
376 static int brcm_pcie_set_ssc(struct brcm_pcie *pcie) in brcm_pcie_set_ssc() argument
382 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, in brcm_pcie_set_ssc()
387 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
394 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
400 ret = brcm_pcie_mdio_read(pcie->base, MDIO_PORT0, in brcm_pcie_set_ssc()
412 static void brcm_pcie_set_gen(struct brcm_pcie *pcie, int gen) in brcm_pcie_set_gen() argument
414 u16 lnkctl2 = readw(pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
415 u32 lnkcap = readl(pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
418 writel(lnkcap, pcie->base + PCIE_RC_CFG_PRIV1_LINK_CAPABILITY); in brcm_pcie_set_gen()
421 writew(lnkctl2, pcie->base + BRCM_PCIE_CAP_REGS + PCI_EXP_LNKCTL2); in brcm_pcie_set_gen()
424 static void brcm_pcie_set_outbound_win(struct brcm_pcie *pcie, in brcm_pcie_set_outbound_win() argument
434 writel(lower_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_LO(win)); in brcm_pcie_set_outbound_win()
435 writel(upper_32_bits(pcie_addr), pcie->base + PCIE_MEM_WIN0_HI(win)); in brcm_pcie_set_outbound_win()
441 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
446 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_LIMIT(win)); in brcm_pcie_set_outbound_win()
448 if (is_bmips(pcie)) in brcm_pcie_set_outbound_win()
456 tmp = readl(pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
459 writel(tmp, pcie->base + PCIE_MEM_WIN0_BASE_HI(win)); in brcm_pcie_set_outbound_win()
462 tmp = readl(pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
465 writel(tmp, pcie->base + PCIE_MEM_WIN0_LIMIT_HI(win)); in brcm_pcie_set_outbound_win()
469 .name = "BRCM STB PCIe MSI",
611 static void brcm_msi_remove(struct brcm_pcie *pcie) in brcm_msi_remove() argument
613 struct brcm_msi *msi = pcie->msi; in brcm_msi_remove()
642 static int brcm_pcie_enable_msi(struct brcm_pcie *pcie) in brcm_pcie_enable_msi() argument
646 struct device *dev = pcie->dev; in brcm_pcie_enable_msi()
660 msi->base = pcie->base; in brcm_pcie_enable_msi()
661 msi->np = pcie->np; in brcm_pcie_enable_msi()
662 msi->target_addr = pcie->msi_target_addr; in brcm_pcie_enable_msi()
664 msi->legacy = pcie->hw_rev < BRCM_PCIE_HW_REV_33; in brcm_pcie_enable_msi()
673 msi->intr_base = msi->base + INTR2_CPU_BASE(pcie); in brcm_pcie_enable_msi()
689 pcie->msi = msi; in brcm_pcie_enable_msi()
695 static bool brcm_pcie_rc_mode(struct brcm_pcie *pcie) in brcm_pcie_rc_mode() argument
697 void __iomem *base = pcie->base; in brcm_pcie_rc_mode()
703 static bool brcm_pcie_link_up(struct brcm_pcie *pcie) in brcm_pcie_link_up() argument
705 u32 val = readl(pcie->base + PCIE_MISC_PCIE_STATUS); in brcm_pcie_link_up()
715 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_map_bus() local
716 void __iomem *base = pcie->base; in brcm_pcie_map_bus()
724 if (!brcm_pcie_link_up(pcie)) in brcm_pcie_map_bus()
729 writel(idx, base + IDX_ADDR(pcie)); in brcm_pcie_map_bus()
730 return base + DATA_ADDR(pcie) + PCIE_ECAM_REG(where); in brcm_pcie_map_bus()
736 struct brcm_pcie *pcie = bus->sysdata; in brcm7425_pcie_map_bus() local
737 void __iomem *base = pcie->base; in brcm7425_pcie_map_bus()
745 if (!brcm_pcie_link_up(pcie)) in brcm7425_pcie_map_bus()
750 writel(idx, base + IDX_ADDR(pcie)); in brcm7425_pcie_map_bus()
751 return base + DATA_ADDR(pcie); in brcm7425_pcie_map_bus()
754 static int brcm_pcie_bridge_sw_init_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_generic() argument
760 if (pcie->bridge_reset) { in brcm_pcie_bridge_sw_init_set_generic()
762 ret = reset_control_assert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
764 ret = reset_control_deassert(pcie->bridge_reset); in brcm_pcie_bridge_sw_init_set_generic()
767 dev_err(pcie->dev, "failed to %s 'bridge' reset, err=%d\n", in brcm_pcie_bridge_sw_init_set_generic()
773 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
775 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_generic()
780 static int brcm_pcie_bridge_sw_init_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_bridge_sw_init_set_7278() argument
785 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
787 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_bridge_sw_init_set_7278()
792 static int brcm_pcie_perst_set_4908(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_4908() argument
796 if (WARN_ONCE(!pcie->perst_reset, "missing PERST# reset controller\n")) in brcm_pcie_perst_set_4908()
800 ret = reset_control_assert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
802 ret = reset_control_deassert(pcie->perst_reset); in brcm_pcie_perst_set_4908()
805 dev_err(pcie->dev, "failed to %s 'perst' reset, err=%d\n", in brcm_pcie_perst_set_4908()
810 static int brcm_pcie_perst_set_7278(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_7278() argument
815 tmp = readl(pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
817 writel(tmp, pcie->base + PCIE_MISC_PCIE_CTRL); in brcm_pcie_perst_set_7278()
822 static int brcm_pcie_perst_set_generic(struct brcm_pcie *pcie, u32 val) in brcm_pcie_perst_set_generic() argument
826 tmp = readl(pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
828 writel(tmp, pcie->base + PCIE_RGR1_SW_INIT_1(pcie)); in brcm_pcie_perst_set_generic()
833 static int brcm_pcie_post_setup_bcm2712(struct brcm_pcie *pcie) in brcm_pcie_post_setup_bcm2712() argument
842 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, SET_ADDR_OFFSET, 0x1600); in brcm_pcie_post_setup_bcm2712()
847 ret = brcm_pcie_mdio_write(pcie->base, MDIO_PORT0, regs[i], data[i]); in brcm_pcie_post_setup_bcm2712()
858 tmp = readl(pcie->base + PCIE_RC_PL_PHY_CTL_15); in brcm_pcie_post_setup_bcm2712()
861 writel(tmp, pcie->base + PCIE_RC_PL_PHY_CTL_15); in brcm_pcie_post_setup_bcm2712()
875 static int brcm_pcie_get_inbound_wins(struct brcm_pcie *pcie, in brcm_pcie_get_inbound_wins() argument
878 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_get_inbound_wins()
881 struct device *dev = pcie->dev; in brcm_pcie_get_inbound_wins()
887 * The HW registers (and PCIe) use order-1 numbering for BARs. As such, in brcm_pcie_get_inbound_wins()
900 if (pcie->cfg->soc_base != BCM7712) in brcm_pcie_get_inbound_wins()
917 if (pcie->cfg->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
920 if (n > pcie->cfg->num_inbound_wins) in brcm_pcie_get_inbound_wins()
934 if (pcie->cfg->soc_base == BCM7712) in brcm_pcie_get_inbound_wins()
937 ret = of_property_read_variable_u64_array(pcie->np, "brcm,scb-sizes", pcie->memc_size, 1, in brcm_pcie_get_inbound_wins()
941 pcie->num_memc = 1; in brcm_pcie_get_inbound_wins()
942 pcie->memc_size[0] = 1ULL << fls64(tot_size - 1); in brcm_pcie_get_inbound_wins()
944 pcie->num_memc = ret; in brcm_pcie_get_inbound_wins()
948 for (i = 0, size = 0; i < pcie->num_memc; i++) in brcm_pcie_get_inbound_wins()
949 size += pcie->memc_size[i]; in brcm_pcie_get_inbound_wins()
966 * PCIe controller integration, which prohibits any access above the in brcm_pcie_get_inbound_wins()
971 * The PCIe host controller by design must set the inbound viewport to in brcm_pcie_get_inbound_wins()
974 * matters, the viewport must start on a pcie-address that is aligned in brcm_pcie_get_inbound_wins()
985 * region in the first 4GB of pcie-space, as some legacy devices can in brcm_pcie_get_inbound_wins()
1029 static void set_inbound_win_registers(struct brcm_pcie *pcie, in set_inbound_win_registers() argument
1033 void __iomem *base = pcie->base; in set_inbound_win_registers()
1057 if (pcie->cfg->soc_base == BCM7712) { in set_inbound_win_registers()
1069 static int brcm_pcie_setup(struct brcm_pcie *pcie) in brcm_pcie_setup() argument
1072 void __iomem *base = pcie->base; in brcm_pcie_setup()
1081 ret = pcie->cfg->bridge_sw_init_set(pcie, 1); in brcm_pcie_setup()
1086 if (pcie->cfg->soc_base == BCM2711) { in brcm_pcie_setup()
1087 ret = pcie->cfg->perst_set(pcie, 1); in brcm_pcie_setup()
1089 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1097 ret = pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_setup()
1101 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_setup()
1102 if (is_bmips(pcie)) in brcm_pcie_setup()
1106 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_setup()
1115 if (is_bmips(pcie)) in brcm_pcie_setup()
1117 else if (pcie->cfg->soc_base == BCM2711) in brcm_pcie_setup()
1119 else if (pcie->cfg->soc_base == BCM7278) in brcm_pcie_setup()
1136 num_inbound_wins = brcm_pcie_get_inbound_wins(pcie, inbound_wins); in brcm_pcie_setup()
1140 set_inbound_win_registers(pcie, inbound_wins, num_inbound_wins); in brcm_pcie_setup()
1142 if (!brcm_pcie_rc_mode(pcie)) { in brcm_pcie_setup()
1143 dev_err(pcie->dev, "PCIe RC controller misconfigured as Endpoint\n"); in brcm_pcie_setup()
1148 for (memc = 0; memc < pcie->num_memc; memc++) { in brcm_pcie_setup()
1149 u32 scb_size_val = ilog2(pcie->memc_size[memc]) - 15; in brcm_pcie_setup()
1169 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_LT_4GB; in brcm_pcie_setup()
1171 pcie->msi_target_addr = BRCM_MSI_TARGET_ADDR_GT_4GB; in brcm_pcie_setup()
1176 if (!of_property_read_bool(pcie->np, "aspm-no-l0s")) in brcm_pcie_setup()
1185 * a PCIe-PCIe bridge (the default setting is to be EP mode). in brcm_pcie_setup()
1192 bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_setup()
1200 dev_err(pcie->dev, "too many outbound wins\n"); in brcm_pcie_setup()
1204 if (is_bmips(pcie)) { in brcm_pcie_setup()
1208 /* bmips PCIe outbound windows have a 128MB max size */ in brcm_pcie_setup()
1212 brcm_pcie_set_outbound_win(pcie, j, start, in brcm_pcie_setup()
1217 brcm_pcie_set_outbound_win(pcie, num_out_wins, res->start, in brcm_pcie_setup()
1223 /* PCIe->SCB endian mode for inbound window */ in brcm_pcie_setup()
1229 if (pcie->cfg->post_setup) { in brcm_pcie_setup()
1230 ret = pcie->cfg->post_setup(pcie); in brcm_pcie_setup()
1241 * presence of a PCIe access.
1243 static void brcm_extend_rbus_timeout(struct brcm_pcie *pcie) in brcm_extend_rbus_timeout() argument
1246 const unsigned int REG_OFFSET = PCIE_RGR1_SW_INIT_1(pcie) - 8; in brcm_extend_rbus_timeout()
1250 if (pcie->cfg->soc_base == BCM7712) in brcm_extend_rbus_timeout()
1254 writel(216 * timeout_us, pcie->base + REG_OFFSET); in brcm_extend_rbus_timeout()
1257 static void brcm_config_clkreq(struct brcm_pcie *pcie) in brcm_config_clkreq() argument
1264 ret = of_property_read_string(pcie->np, "brcm,clkreq-mode", &mode); in brcm_config_clkreq()
1266 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1271 clkreq_cntl = readl(pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1279 * L1SS capable AND the OS enables L1SS, all PCIe traffic in brcm_config_clkreq()
1289 tmp = readl(pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1291 writel(tmp, pcie->base + PCIE_RC_CFG_PRIV1_ROOT_CAP); in brcm_config_clkreq()
1299 * section 3.2.5.2.2 of the PCIe spec. This situation is in brcm_config_clkreq()
1303 brcm_extend_rbus_timeout(pcie); in brcm_config_clkreq()
1311 dev_err(pcie->dev, err_msg); in brcm_config_clkreq()
1314 writel(clkreq_cntl, pcie->base + HARD_DEBUG(pcie)); in brcm_config_clkreq()
1316 dev_info(pcie->dev, "clkreq-mode set to %s\n", mode); in brcm_config_clkreq()
1319 static int brcm_pcie_start_link(struct brcm_pcie *pcie) in brcm_pcie_start_link() argument
1321 struct device *dev = pcie->dev; in brcm_pcie_start_link()
1322 void __iomem *base = pcie->base; in brcm_pcie_start_link()
1328 if (pcie->gen) in brcm_pcie_start_link()
1329 brcm_pcie_set_gen(pcie, pcie->gen); in brcm_pcie_start_link()
1332 ret = pcie->cfg->perst_set(pcie, 0); in brcm_pcie_start_link()
1337 * Wait for 100ms after PERST# deassertion; see PCIe CEM specification in brcm_pcie_start_link()
1338 * sections 2.2, PCIe r5.0, 6.6.1. in brcm_pcie_start_link()
1347 for (i = 0; i < 100 && !brcm_pcie_link_up(pcie); i += 5) in brcm_pcie_start_link()
1350 if (!brcm_pcie_link_up(pcie)) { in brcm_pcie_start_link()
1355 brcm_config_clkreq(pcie); in brcm_pcie_start_link()
1357 if (pcie->ssc) { in brcm_pcie_start_link()
1358 ret = brcm_pcie_set_ssc(pcie); in brcm_pcie_start_link()
1400 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_add_bus() local
1415 pcie->sr = sr; in brcm_pcie_add_bus()
1420 pcie->sr = NULL; in brcm_pcie_add_bus()
1428 pcie->sr = NULL; in brcm_pcie_add_bus()
1433 brcm_pcie_start_link(pcie); in brcm_pcie_add_bus()
1439 struct brcm_pcie *pcie = bus->sysdata; in brcm_pcie_remove_bus() local
1440 struct subdev_regulators *sr = pcie->sr; in brcm_pcie_remove_bus()
1449 pcie->sr = NULL; in brcm_pcie_remove_bus()
1452 /* L23 is a low-power PCIe link state */
1453 static void brcm_pcie_enter_l23(struct brcm_pcie *pcie) in brcm_pcie_enter_l23() argument
1455 void __iomem *base = pcie->base; in brcm_pcie_enter_l23()
1475 dev_err(pcie->dev, "failed to enter low-power link state\n"); in brcm_pcie_enter_l23()
1478 static int brcm_phy_cntl(struct brcm_pcie *pcie, const int start) in brcm_phy_cntl() argument
1492 void __iomem *base = pcie->base; in brcm_phy_cntl()
1509 dev_err(pcie->dev, "failed to %s phy\n", (start ? "start" : "stop")); in brcm_phy_cntl()
1514 static inline int brcm_phy_start(struct brcm_pcie *pcie) in brcm_phy_start() argument
1516 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 1) : 0; in brcm_phy_start()
1519 static inline int brcm_phy_stop(struct brcm_pcie *pcie) in brcm_phy_stop() argument
1521 return pcie->cfg->has_phy ? brcm_phy_cntl(pcie, 0) : 0; in brcm_phy_stop()
1524 static int brcm_pcie_turn_off(struct brcm_pcie *pcie) in brcm_pcie_turn_off() argument
1526 void __iomem *base = pcie->base; in brcm_pcie_turn_off()
1529 if (brcm_pcie_link_up(pcie)) in brcm_pcie_turn_off()
1530 brcm_pcie_enter_l23(pcie); in brcm_pcie_turn_off()
1532 ret = pcie->cfg->perst_set(pcie, 1); in brcm_pcie_turn_off()
1542 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_turn_off()
1544 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_turn_off()
1546 if (!(pcie->cfg->quirks & CFG_QUIRK_AVOID_BRIDGE_SHUTDOWN)) in brcm_pcie_turn_off()
1547 /* Shutdown PCIe bridge */ in brcm_pcie_turn_off()
1548 ret = pcie->cfg->bridge_sw_init_set(pcie, 1); in brcm_pcie_turn_off()
1566 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_suspend_noirq() local
1567 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_suspend_noirq()
1570 ret = brcm_pcie_turn_off(pcie); in brcm_pcie_suspend_noirq()
1579 if (brcm_phy_stop(pcie)) in brcm_pcie_suspend_noirq()
1582 ret = reset_control_rearm(pcie->rescal); in brcm_pcie_suspend_noirq()
1588 if (pcie->sr) { in brcm_pcie_suspend_noirq()
1594 pcie->ep_wakeup_capable = false; in brcm_pcie_suspend_noirq()
1596 &pcie->ep_wakeup_capable); in brcm_pcie_suspend_noirq()
1597 if (!pcie->ep_wakeup_capable) { in brcm_pcie_suspend_noirq()
1598 ret = regulator_bulk_disable(pcie->sr->num_supplies, in brcm_pcie_suspend_noirq()
1599 pcie->sr->supplies); in brcm_pcie_suspend_noirq()
1602 rret = reset_control_reset(pcie->rescal); in brcm_pcie_suspend_noirq()
1610 clk_disable_unprepare(pcie->clk); in brcm_pcie_suspend_noirq()
1617 struct brcm_pcie *pcie = dev_get_drvdata(dev); in brcm_pcie_resume_noirq() local
1622 base = pcie->base; in brcm_pcie_resume_noirq()
1623 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_resume_noirq()
1627 ret = reset_control_reset(pcie->rescal); in brcm_pcie_resume_noirq()
1631 ret = brcm_phy_start(pcie); in brcm_pcie_resume_noirq()
1636 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_resume_noirq()
1639 tmp = readl(base + HARD_DEBUG(pcie)); in brcm_pcie_resume_noirq()
1641 writel(tmp, base + HARD_DEBUG(pcie)); in brcm_pcie_resume_noirq()
1646 ret = brcm_pcie_setup(pcie); in brcm_pcie_resume_noirq()
1650 if (pcie->sr) { in brcm_pcie_resume_noirq()
1651 if (pcie->ep_wakeup_capable) { in brcm_pcie_resume_noirq()
1658 pcie->ep_wakeup_capable = false; in brcm_pcie_resume_noirq()
1660 ret = regulator_bulk_enable(pcie->sr->num_supplies, in brcm_pcie_resume_noirq()
1661 pcie->sr->supplies); in brcm_pcie_resume_noirq()
1669 ret = brcm_pcie_start_link(pcie); in brcm_pcie_resume_noirq()
1673 if (pcie->msi) in brcm_pcie_resume_noirq()
1674 brcm_msi_set_regs(pcie->msi); in brcm_pcie_resume_noirq()
1679 if (pcie->sr) in brcm_pcie_resume_noirq()
1680 regulator_bulk_disable(pcie->sr->num_supplies, pcie->sr->supplies); in brcm_pcie_resume_noirq()
1682 rret = reset_control_rearm(pcie->rescal); in brcm_pcie_resume_noirq()
1684 dev_err(pcie->dev, "failed to rearm 'rescal' reset, err=%d\n", rret); in brcm_pcie_resume_noirq()
1686 clk_disable_unprepare(pcie->clk); in brcm_pcie_resume_noirq()
1690 static void __brcm_pcie_remove(struct brcm_pcie *pcie) in __brcm_pcie_remove() argument
1692 brcm_msi_remove(pcie); in __brcm_pcie_remove()
1693 brcm_pcie_turn_off(pcie); in __brcm_pcie_remove()
1694 if (brcm_phy_stop(pcie)) in __brcm_pcie_remove()
1695 dev_err(pcie->dev, "Could not stop phy\n"); in __brcm_pcie_remove()
1696 if (reset_control_rearm(pcie->rescal)) in __brcm_pcie_remove()
1697 dev_err(pcie->dev, "Could not rearm rescal reset\n"); in __brcm_pcie_remove()
1698 clk_disable_unprepare(pcie->clk); in __brcm_pcie_remove()
1703 struct brcm_pcie *pcie = platform_get_drvdata(pdev); in brcm_pcie_remove() local
1704 struct pci_host_bridge *bridge = pci_host_bridge_from_priv(pcie); in brcm_pcie_remove()
1708 __brcm_pcie_remove(pcie); in brcm_pcie_remove()
1819 { .compatible = "brcm,bcm2711-pcie", .data = &bcm2711_cfg },
1820 { .compatible = "brcm,bcm2712-pcie", .data = &bcm2712_cfg },
1821 { .compatible = "brcm,bcm4908-pcie", .data = &bcm4908_cfg },
1822 { .compatible = "brcm,bcm7211-pcie", .data = &generic_cfg },
1823 { .compatible = "brcm,bcm7216-pcie", .data = &bcm7216_cfg },
1824 { .compatible = "brcm,bcm7278-pcie", .data = &bcm7278_cfg },
1825 { .compatible = "brcm,bcm7425-pcie", .data = &bcm7425_cfg },
1826 { .compatible = "brcm,bcm7435-pcie", .data = &bcm7435_cfg },
1827 { .compatible = "brcm,bcm7445-pcie", .data = &generic_cfg },
1828 { .compatible = "brcm,bcm7712-pcie", .data = &bcm7712_cfg },
1853 struct brcm_pcie *pcie; in brcm_pcie_probe() local
1856 bridge = devm_pci_alloc_host_bridge(&pdev->dev, sizeof(*pcie)); in brcm_pcie_probe()
1866 pcie = pci_host_bridge_priv(bridge); in brcm_pcie_probe()
1867 pcie->dev = &pdev->dev; in brcm_pcie_probe()
1868 pcie->np = np; in brcm_pcie_probe()
1869 pcie->cfg = data; in brcm_pcie_probe()
1871 pcie->base = devm_platform_ioremap_resource(pdev, 0); in brcm_pcie_probe()
1872 if (IS_ERR(pcie->base)) in brcm_pcie_probe()
1873 return PTR_ERR(pcie->base); in brcm_pcie_probe()
1875 pcie->clk = devm_clk_get_optional(&pdev->dev, "sw_pcie"); in brcm_pcie_probe()
1876 if (IS_ERR(pcie->clk)) in brcm_pcie_probe()
1877 return PTR_ERR(pcie->clk); in brcm_pcie_probe()
1880 pcie->gen = (ret < 0) ? 0 : ret; in brcm_pcie_probe()
1882 pcie->ssc = of_property_read_bool(np, "brcm,enable-ssc"); in brcm_pcie_probe()
1884 pcie->rescal = devm_reset_control_get_optional_shared(&pdev->dev, "rescal"); in brcm_pcie_probe()
1885 if (IS_ERR(pcie->rescal)) in brcm_pcie_probe()
1886 return PTR_ERR(pcie->rescal); in brcm_pcie_probe()
1888 pcie->perst_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "perst"); in brcm_pcie_probe()
1889 if (IS_ERR(pcie->perst_reset)) in brcm_pcie_probe()
1890 return PTR_ERR(pcie->perst_reset); in brcm_pcie_probe()
1892 pcie->bridge_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "bridge"); in brcm_pcie_probe()
1893 if (IS_ERR(pcie->bridge_reset)) in brcm_pcie_probe()
1894 return PTR_ERR(pcie->bridge_reset); in brcm_pcie_probe()
1896 pcie->swinit_reset = devm_reset_control_get_optional_exclusive(&pdev->dev, "swinit"); in brcm_pcie_probe()
1897 if (IS_ERR(pcie->swinit_reset)) in brcm_pcie_probe()
1898 return PTR_ERR(pcie->swinit_reset); in brcm_pcie_probe()
1900 ret = clk_prepare_enable(pcie->clk); in brcm_pcie_probe()
1904 pcie->cfg->bridge_sw_init_set(pcie, 0); in brcm_pcie_probe()
1906 if (pcie->swinit_reset) { in brcm_pcie_probe()
1907 ret = reset_control_assert(pcie->swinit_reset); in brcm_pcie_probe()
1909 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1917 ret = reset_control_deassert(pcie->swinit_reset); in brcm_pcie_probe()
1919 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1925 ret = reset_control_reset(pcie->rescal); in brcm_pcie_probe()
1927 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1931 ret = brcm_phy_start(pcie); in brcm_pcie_probe()
1933 reset_control_rearm(pcie->rescal); in brcm_pcie_probe()
1934 clk_disable_unprepare(pcie->clk); in brcm_pcie_probe()
1938 ret = brcm_pcie_setup(pcie); in brcm_pcie_probe()
1942 pcie->hw_rev = readl(pcie->base + PCIE_MISC_REVISION); in brcm_pcie_probe()
1943 if (pcie->cfg->soc_base == BCM4908 && in brcm_pcie_probe()
1944 pcie->hw_rev >= BRCM_PCIE_HW_REV_3_20) { in brcm_pcie_probe()
1945 dev_err(pcie->dev, "hardware revision with unsupported PERST# setup\n"); in brcm_pcie_probe()
1951 struct device_node *msi_np = of_parse_phandle(pcie->np, "msi-parent", 0); in brcm_pcie_probe()
1953 if (msi_np == pcie->np) in brcm_pcie_probe()
1954 ret = brcm_pcie_enable_msi(pcie); in brcm_pcie_probe()
1959 dev_err(pcie->dev, "probe of internal MSI failed"); in brcm_pcie_probe()
1964 bridge->ops = pcie->cfg->soc_base == BCM7425 ? in brcm_pcie_probe()
1966 bridge->sysdata = pcie; in brcm_pcie_probe()
1968 platform_set_drvdata(pdev, pcie); in brcm_pcie_probe()
1971 if (!ret && !brcm_pcie_link_up(pcie)) in brcm_pcie_probe()
1982 __brcm_pcie_remove(pcie); in brcm_pcie_probe()
1998 .name = "brcm-pcie",
2006 MODULE_DESCRIPTION("Broadcom STB PCIe RC driver");