40 /* PARF registers */
267 	void __iomem *parf;			/* DT parf */  member
356 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_base()
358 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +  in qcom_pcie_configure_dbi_base()
373 		writel(lower_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
375 		writel(upper_32_bits(pci->dbi_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
379 			writel(lower_32_bits(pci->atu_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
381 			writel(upper_32_bits(pci->atu_phys_addr), pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
385 		writel(0x0, pcie->parf + PARF_SLV_ADDR_SPACE_SIZE_V2);  in qcom_pcie_configure_dbi_atu_base()
386 		writel(SLV_ADDR_SPACE_SZ, pcie->parf +  in qcom_pcie_configure_dbi_atu_base()
446 	writel(1, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_deinit_2_1_0()
491 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
493 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
504 		       pcie->parf + PARF_PCS_DEEMPH);  in qcom_pcie_post_init_2_1_0()
507 		       pcie->parf + PARF_PCS_SWING);  in qcom_pcie_post_init_2_1_0()
508 		writel(PHY_RX0_EQ(4), pcie->parf + PARF_CONFIG_BITS);  in qcom_pcie_post_init_2_1_0()
513 		val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
516 		writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_1_0()
520 	val = readl(pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
525 	writel(val, pcie->parf + PARF_PHY_REFCLK);  in qcom_pcie_post_init_2_1_0()
610 		u32 val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
613 		writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT);  in qcom_pcie_post_init_1_0_0()
626 	val = readl(pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
628 	writel(val, pcie->parf + PARF_LTSSM);  in qcom_pcie_2_3_2_ltssm_enable()
690 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
692 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_2()
697 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
699 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_2()
701 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
703 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_3_2()
705 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
707 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_post_init_2_3_2()
737 	res->resets[9].id = "parf";  in qcom_pcie_get_resources_2_4_0()
876 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
878 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_3_3()
885 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_3_3()
886 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_3_3()
969 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_init_2_7_0()
972 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
974 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_init_2_7_0()
979 	val = readl(pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
981 	writel(val, pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_init_2_7_0()
983 	val = readl(pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
985 	writel(val, pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_init_2_7_0()
988 	val = readl(pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
990 	writel(val, pcie->parf + PARF_PM_CTRL);  in qcom_pcie_init_2_7_0()
992 	val = readl(pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
994 	writel(val, pcie->parf + PARF_AXI_MSTR_WR_ADDR_HALT_V2);  in qcom_pcie_init_2_7_0()
1011 				pcie->parf + PARF_NO_SNOOP_OVERRIDE);  in qcom_pcie_post_init_2_7_0()
1056 	void __iomem *bdf_to_sid_base = pcie->parf + PARF_BDF_TO_SID_TABLE_N;  in qcom_pcie_config_sid_1_9_0()
1068 	val = readl(pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1070 	writel(val, pcie->parf + PARF_BDF_TO_SID_CFG);  in qcom_pcie_config_sid_1_9_0()
1185 	val = readl(pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1187 	writel(val, pcie->parf + PARF_PHY_CTRL);  in qcom_pcie_post_init_2_9_0()
1191 	writel(DEVICE_TYPE_RC, pcie->parf + PARF_DEVICE_TYPE);  in qcom_pcie_post_init_2_9_0()
1193 		pcie->parf + PARF_MHI_CLOCK_RESET_CTRL);  in qcom_pcie_post_init_2_9_0()
1201 		pcie->parf + PARF_SYS_CTRL);  in qcom_pcie_post_init_2_9_0()
1203 	writel(0, pcie->parf + PARF_Q2A_FLUSH);  in qcom_pcie_post_init_2_9_0()
1219 		writel(0, pcie->parf + PARF_BDF_TO_SID_TABLE_N + (4 * i));  in qcom_pcie_post_init_2_9_0()
1562 	u32 status = readl_relaxed(pcie->parf + PARF_INT_ALL_STATUS);  in qcom_pcie_global_irq_thread()
1564 	writel_relaxed(status, pcie->parf + PARF_INT_ALL_CLEAR);  in qcom_pcie_global_irq_thread()
1628 	pcie->parf = devm_platform_ioremap_resource_byname(pdev, "parf");  in qcom_pcie_probe()
1629 	if (IS_ERR(pcie->parf)) {  in qcom_pcie_probe()
1630 		ret = PTR_ERR(pcie->parf);  in qcom_pcie_probe()
1736 			       pcie->parf + PARF_INT_ALL_MASK);  in qcom_pcie_probe()