Lines Matching +full:pci +full:- +full:phy
1 // SPDX-License-Identifier: GPL-2.0
14 #include <linux/phy/phy.h>
19 #include "../../pci.h"
20 #include "pcie-designware.h"
22 #define PORT_AFR_N_FTS_GEN12_DFT (SZ_128 - 1)
63 struct dw_pcie pci; member
69 struct phy *phy; member
85 writel(val, pcie->app_base + ofs); in pcie_app_wr()
91 pcie_update_bits(pcie->app_base, ofs, mask, val); in pcie_app_wr_mask()
96 return dw_pcie_readl_dbi(&pcie->pci, ofs); in pcie_rc_cfg_rd()
101 dw_pcie_writel_dbi(&pcie->pci, ofs, val); in pcie_rc_cfg_wr()
107 pcie_update_bits(pcie->pci.dbi_base, ofs, mask, val); in pcie_rc_cfg_wr_mask()
124 u8 offset = dw_pcie_find_capability(&pcie->pci, PCI_CAP_ID_EXP); in intel_pcie_link_setup()
132 static void intel_pcie_init_n_fts(struct dw_pcie *pci) in intel_pcie_init_n_fts() argument
134 switch (pci->max_link_speed) { in intel_pcie_init_n_fts()
136 pci->n_fts[1] = PORT_AFR_N_FTS_GEN3; in intel_pcie_init_n_fts()
139 pci->n_fts[1] = PORT_AFR_N_FTS_GEN4; in intel_pcie_init_n_fts()
142 pci->n_fts[1] = PORT_AFR_N_FTS_GEN12_DFT; in intel_pcie_init_n_fts()
145 pci->n_fts[0] = PORT_AFR_N_FTS_GEN12_DFT; in intel_pcie_init_n_fts()
150 struct device *dev = pcie->pci.dev; in intel_pcie_ep_rst_init()
153 pcie->reset_gpio = devm_gpiod_get(dev, "reset", GPIOD_OUT_LOW); in intel_pcie_ep_rst_init()
154 if (IS_ERR(pcie->reset_gpio)) { in intel_pcie_ep_rst_init()
155 ret = PTR_ERR(pcie->reset_gpio); in intel_pcie_ep_rst_init()
156 if (ret != -EPROBE_DEFER) in intel_pcie_ep_rst_init()
169 reset_control_assert(pcie->core_rst); in intel_pcie_core_rst_assert()
175 * One micro-second delay to make sure the reset pulse in intel_pcie_core_rst_deassert()
179 reset_control_deassert(pcie->core_rst); in intel_pcie_core_rst_deassert()
182 * Some SoC core reset also reset PHY, more delay needed in intel_pcie_core_rst_deassert()
190 gpiod_set_value_cansleep(pcie->reset_gpio, 1); in intel_pcie_device_rst_assert()
195 msleep(pcie->rst_intrvl); in intel_pcie_device_rst_deassert()
196 gpiod_set_value_cansleep(pcie->reset_gpio, 0); in intel_pcie_device_rst_deassert()
208 struct dw_pcie *pci = &pcie->pci; in intel_pcie_get_resources() local
209 struct device *dev = pci->dev; in intel_pcie_get_resources()
212 pcie->core_clk = devm_clk_get(dev, NULL); in intel_pcie_get_resources()
213 if (IS_ERR(pcie->core_clk)) { in intel_pcie_get_resources()
214 ret = PTR_ERR(pcie->core_clk); in intel_pcie_get_resources()
215 if (ret != -EPROBE_DEFER) in intel_pcie_get_resources()
220 pcie->core_rst = devm_reset_control_get(dev, NULL); in intel_pcie_get_resources()
221 if (IS_ERR(pcie->core_rst)) { in intel_pcie_get_resources()
222 ret = PTR_ERR(pcie->core_rst); in intel_pcie_get_resources()
223 if (ret != -EPROBE_DEFER) in intel_pcie_get_resources()
228 ret = device_property_read_u32(dev, "reset-assert-ms", in intel_pcie_get_resources()
229 &pcie->rst_intrvl); in intel_pcie_get_resources()
231 pcie->rst_intrvl = RESET_INTERVAL_MS; in intel_pcie_get_resources()
233 pcie->app_base = devm_platform_ioremap_resource_byname(pdev, "app"); in intel_pcie_get_resources()
234 if (IS_ERR(pcie->app_base)) in intel_pcie_get_resources()
235 return PTR_ERR(pcie->app_base); in intel_pcie_get_resources()
237 pcie->phy = devm_phy_get(dev, "pcie"); in intel_pcie_get_resources()
238 if (IS_ERR(pcie->phy)) { in intel_pcie_get_resources()
239 ret = PTR_ERR(pcie->phy); in intel_pcie_get_resources()
240 if (ret != -EPROBE_DEFER) in intel_pcie_get_resources()
241 dev_err(dev, "Couldn't get pcie-phy: %d\n", ret); in intel_pcie_get_resources()
252 struct dw_pcie *pci = &pcie->pci; in intel_pcie_wait_l2() local
254 if (pci->max_link_speed < 3) in intel_pcie_wait_l2()
262 ret = readl_poll_timeout(pcie->app_base + PCIE_APP_PMC, value, in intel_pcie_wait_l2()
266 dev_err(pcie->pci.dev, "PCIe link enter L2 timeout!\n"); in intel_pcie_wait_l2()
273 if (dw_pcie_link_up(&pcie->pci)) in intel_pcie_turn_off()
284 struct dw_pcie *pci = &pcie->pci; in intel_pcie_host_setup() local
289 ret = phy_init(pcie->phy); in intel_pcie_host_setup()
295 ret = clk_prepare_enable(pcie->core_clk); in intel_pcie_host_setup()
297 dev_err(pcie->pci.dev, "Core clock enable failed: %d\n", ret); in intel_pcie_host_setup()
301 pci->atu_base = pci->dbi_base + 0xC0000; in intel_pcie_host_setup()
305 intel_pcie_init_n_fts(pci); in intel_pcie_host_setup()
307 ret = dw_pcie_setup_rc(&pci->pp); in intel_pcie_host_setup()
311 dw_pcie_upconfig_setup(pci); in intel_pcie_host_setup()
316 ret = dw_pcie_wait_for_link(pci); in intel_pcie_host_setup()
327 clk_disable_unprepare(pcie->core_clk); in intel_pcie_host_setup()
330 phy_exit(pcie->phy); in intel_pcie_host_setup()
339 clk_disable_unprepare(pcie->core_clk); in __intel_pcie_remove()
341 phy_exit(pcie->phy); in __intel_pcie_remove()
347 struct dw_pcie_rp *pp = &pcie->pci.pp; in intel_pcie_remove()
363 phy_exit(pcie->phy); in intel_pcie_suspend_noirq()
364 clk_disable_unprepare(pcie->core_clk); in intel_pcie_suspend_noirq()
377 struct dw_pcie *pci = to_dw_pcie_from_pp(pp); in intel_pcie_rc_init() local
378 struct intel_pcie *pcie = dev_get_drvdata(pci->dev); in intel_pcie_rc_init()
392 struct device *dev = &pdev->dev; in intel_pcie_probe()
395 struct dw_pcie *pci; in intel_pcie_probe() local
400 return -ENOMEM; in intel_pcie_probe()
403 pci = &pcie->pci; in intel_pcie_probe()
404 pci->dev = dev; in intel_pcie_probe()
405 pci->use_parent_dt_ranges = true; in intel_pcie_probe()
406 pp = &pci->pp; in intel_pcie_probe()
416 pci->ops = &intel_pcie_ops; in intel_pcie_probe()
417 pp->ops = &intel_pcie_dw_ops; in intel_pcie_probe()
434 { .compatible = "intel,lgm-pcie" },
442 .name = "intel-gw-pcie",