1 // SPDX-License-Identifier: GPL-2.0
3  * PCIe host controller driver for AMD MDB PCIe Bridge
5  * Copyright (C) 2024-2025, Advanced Micro Devices, Inc.
21 #include "pcie-designware.h"
54  * struct amd_mdb_pcie - PCIe port information
56  * @slcr: MDB System Level Control and Status Register (SLCR) base
58  * @mdb_domain: MDB IRQ domain pointer
75 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_intx_irq_mask()
76 	struct dw_pcie_rp *port = &pci->pp;  in amd_mdb_intx_irq_mask()
80 	raw_spin_lock_irqsave(&port->lock, flags);  in amd_mdb_intx_irq_mask()
82 			 AMD_MDB_PCIE_INTR_INTX_ASSERT(data->hwirq));  in amd_mdb_intx_irq_mask()
88 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);  in amd_mdb_intx_irq_mask()
89 	raw_spin_unlock_irqrestore(&port->lock, flags);  in amd_mdb_intx_irq_mask()
95 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_intx_irq_unmask()
96 	struct dw_pcie_rp *port = &pci->pp;  in amd_mdb_intx_irq_unmask()
100 	raw_spin_lock_irqsave(&port->lock, flags);  in amd_mdb_intx_irq_unmask()
102 			 AMD_MDB_PCIE_INTR_INTX_ASSERT(data->hwirq));  in amd_mdb_intx_irq_unmask()
108 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);  in amd_mdb_intx_irq_unmask()
109 	raw_spin_unlock_irqrestore(&port->lock, flags);  in amd_mdb_intx_irq_unmask()
113 	.name		= "AMD MDB INTx",
119  * amd_mdb_pcie_intx_map - Set the handler for the INTx and mark IRQ as valid
131 	irq_set_chip_data(irq, domain->host_data);  in amd_mdb_pcie_intx_map()
148 	val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in dw_pcie_rp_intx()
153 			generic_handle_domain_irq(pcie->intx_domain, i);  in dw_pcie_rp_intx()
176 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_event_irq_mask()
177 	struct dw_pcie_rp *port = &pci->pp;  in amd_mdb_event_irq_mask()
181 	raw_spin_lock_irqsave(&port->lock, flags);  in amd_mdb_event_irq_mask()
182 	val = BIT(d->hwirq);  in amd_mdb_event_irq_mask()
183 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);  in amd_mdb_event_irq_mask()
184 	raw_spin_unlock_irqrestore(&port->lock, flags);  in amd_mdb_event_irq_mask()
190 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_event_irq_unmask()
191 	struct dw_pcie_rp *port = &pci->pp;  in amd_mdb_event_irq_unmask()
195 	raw_spin_lock_irqsave(&port->lock, flags);  in amd_mdb_event_irq_unmask()
196 	val = BIT(d->hwirq);  in amd_mdb_event_irq_unmask()
197 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);  in amd_mdb_event_irq_unmask()
198 	raw_spin_unlock_irqrestore(&port->lock, flags);  in amd_mdb_event_irq_unmask()
202 	.name		= "AMD MDB RC-Event",
212 	irq_set_chip_data(irq, domain->host_data);  in amd_mdb_pcie_event_map()
228 	val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_event()
229 	val &= ~readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_MASK_MISC);  in amd_mdb_pcie_event()
231 		generic_handle_domain_irq(pcie->mdb_domain, i);  in amd_mdb_pcie_event()
232 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_event()
239 	if (pcie->intx_domain) {  in amd_mdb_pcie_free_irq_domains()
240 		irq_domain_remove(pcie->intx_domain);  in amd_mdb_pcie_free_irq_domains()
241 		pcie->intx_domain = NULL;  in amd_mdb_pcie_free_irq_domains()
244 	if (pcie->mdb_domain) {  in amd_mdb_pcie_free_irq_domains()
245 		irq_domain_remove(pcie->mdb_domain);  in amd_mdb_pcie_free_irq_domains()
246 		pcie->mdb_domain = NULL;  in amd_mdb_pcie_free_irq_domains()
256 		       pcie->slcr + AMD_MDB_TLP_IR_DISABLE_MISC);  in amd_mdb_pcie_init_port()
259 	val = readl_relaxed(pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_init_port()
261 	writel_relaxed(val, pcie->slcr + AMD_MDB_TLP_IR_STATUS_MISC);  in amd_mdb_pcie_init_port()
265 		       pcie->slcr + AMD_MDB_TLP_IR_ENABLE_MISC);  in amd_mdb_pcie_init_port()
271  * amd_mdb_pcie_init_irq_domains - Initialize IRQ domain
280 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_pcie_init_irq_domains()
281 	struct dw_pcie_rp *pp = &pci->pp;  in amd_mdb_pcie_init_irq_domains()
282 	struct device *dev = &pdev->dev;  in amd_mdb_pcie_init_irq_domains()
283 	struct device_node *node = dev->of_node;  in amd_mdb_pcie_init_irq_domains()
290 		return -ENODEV;  in amd_mdb_pcie_init_irq_domains()
293 	pcie->mdb_domain = irq_domain_add_linear(pcie_intc_node, 32,  in amd_mdb_pcie_init_irq_domains()
295 	if (!pcie->mdb_domain) {  in amd_mdb_pcie_init_irq_domains()
296 		err = -ENOMEM;  in amd_mdb_pcie_init_irq_domains()
297 		dev_err(dev, "Failed to add MDB domain\n");  in amd_mdb_pcie_init_irq_domains()
301 	irq_domain_update_bus_token(pcie->mdb_domain, DOMAIN_BUS_NEXUS);  in amd_mdb_pcie_init_irq_domains()
303 	pcie->intx_domain = irq_domain_add_linear(pcie_intc_node, PCI_NUM_INTX,  in amd_mdb_pcie_init_irq_domains()
305 	if (!pcie->intx_domain) {  in amd_mdb_pcie_init_irq_domains()
306 		err = -ENOMEM;  in amd_mdb_pcie_init_irq_domains()
312 	irq_domain_update_bus_token(pcie->intx_domain, DOMAIN_BUS_WIRED);  in amd_mdb_pcie_init_irq_domains()
314 	raw_spin_lock_init(&pp->lock);  in amd_mdb_pcie_init_irq_domains()
330 	dev = pcie->pci.dev;  in amd_mdb_pcie_intr_handler()
336 	d = irq_domain_get_irq_data(pcie->mdb_domain, irq);  in amd_mdb_pcie_intr_handler()
337 	if (intr_cause[d->hwirq].str)  in amd_mdb_pcie_intr_handler()
338 		dev_warn(dev, "%s\n", intr_cause[d->hwirq].str);  in amd_mdb_pcie_intr_handler()
340 		dev_warn_once(dev, "Unknown IRQ %ld\n", d->hwirq);  in amd_mdb_pcie_intr_handler()
348 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_setup_irq()
349 	struct dw_pcie_rp *pp = &pci->pp;  in amd_mdb_setup_irq()
350 	struct device *dev = &pdev->dev;  in amd_mdb_setup_irq()
355 	pp->irq = platform_get_irq(pdev, 0);  in amd_mdb_setup_irq()
356 	if (pp->irq < 0)  in amd_mdb_setup_irq()
357 		return pp->irq;  in amd_mdb_setup_irq()
363 		irq = irq_create_mapping(pcie->mdb_domain, i);  in amd_mdb_setup_irq()
365 			dev_err(dev, "Failed to map MDB domain interrupt\n");  in amd_mdb_setup_irq()
366 			return -ENOMEM;  in amd_mdb_setup_irq()
378 	pcie->intx_irq = irq_create_mapping(pcie->mdb_domain,  in amd_mdb_setup_irq()
380 	if (!pcie->intx_irq) {  in amd_mdb_setup_irq()
382 		return -ENXIO;  in amd_mdb_setup_irq()
385 	err = devm_request_irq(dev, pcie->intx_irq, dw_pcie_rp_intx,  in amd_mdb_setup_irq()
394 	err = devm_request_irq(dev, pp->irq, amd_mdb_pcie_event, IRQF_NO_THREAD,  in amd_mdb_setup_irq()
398 			pp->irq, err);  in amd_mdb_setup_irq()
408 	struct dw_pcie *pci = &pcie->pci;  in amd_mdb_add_pcie_port()
409 	struct dw_pcie_rp *pp = &pci->pp;  in amd_mdb_add_pcie_port()
410 	struct device *dev = &pdev->dev;  in amd_mdb_add_pcie_port()
413 	pcie->slcr = devm_platform_ioremap_resource_byname(pdev, "slcr");  in amd_mdb_add_pcie_port()
414 	if (IS_ERR(pcie->slcr))  in amd_mdb_add_pcie_port()
415 		return PTR_ERR(pcie->slcr);  in amd_mdb_add_pcie_port()
427 	pp->ops = &amd_mdb_pcie_host_ops;  in amd_mdb_add_pcie_port()
431 		dev_err(dev, "Failed to initialize host, err=%d\n", err);  in amd_mdb_add_pcie_port()
444 	struct device *dev = &pdev->dev;  in amd_mdb_pcie_probe()
450 		return -ENOMEM;  in amd_mdb_pcie_probe()
452 	pci = &pcie->pci;  in amd_mdb_pcie_probe()
453 	pci->dev = dev;  in amd_mdb_pcie_probe()
462 		.compatible = "amd,versal2-mdb-host",
469 		.name	= "amd-mdb-pcie",