Lines Matching +full:de +full:- +full:assertion
1 // SPDX-License-Identifier: GPL-2.0
17 #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
18 #include <linux/mfd/syscon/imx7-iomuxc-gpr.h>
37 #include "pcie-designware.h"
74 #define to_imx_pcie(x) dev_get_drvdata((x)->dev)
109 #define imx_check_flag(pci, val) (pci->drvdata->flags & val)
166 /* PCIe Port Logic registers (memory-mapped) */
179 /* PHY registers (not memory-mapped) */
216 WARN_ON(imx_pcie->drvdata->variant != IMX8MQ && in imx_pcie_grp_offset()
217 imx_pcie->drvdata->variant != IMX8MQ_EP && in imx_pcie_grp_offset()
218 imx_pcie->drvdata->variant != IMX8MM && in imx_pcie_grp_offset()
219 imx_pcie->drvdata->variant != IMX8MM_EP && in imx_pcie_grp_offset()
220 imx_pcie->drvdata->variant != IMX8MP && in imx_pcie_grp_offset()
221 imx_pcie->drvdata->variant != IMX8MP_EP); in imx_pcie_grp_offset()
222 return imx_pcie->controller_id == 1 ? IOMUXC_GPR16 : IOMUXC_GPR14; in imx_pcie_grp_offset()
227 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
232 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
235 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx95_pcie_init_phy()
245 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_configure_type()
248 if (drvdata->mode == DW_PCIE_EP_TYPE) in imx_pcie_configure_type()
253 id = imx_pcie->controller_id; in imx_pcie_configure_type()
256 if (!drvdata->mode_mask[0]) in imx_pcie_configure_type()
260 if (!drvdata->mode_mask[id]) in imx_pcie_configure_type()
263 mask = drvdata->mode_mask[id]; in imx_pcie_configure_type()
264 val = mode << (ffs(mask) - 1); in imx_pcie_configure_type()
266 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->mode_off[id], mask, val); in imx_pcie_configure_type()
271 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_poll_ack()
287 return -ETIMEDOUT; in pcie_phy_poll_ack()
292 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_wait_ack()
312 /* Read from the 16-bit PCIe PHY control registers (not memory-mapped) */
315 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_read()
341 struct dw_pcie *pci = imx_pcie->pci; in pcie_phy_write()
366 /* wait for ack de-assertion */ in pcie_phy_write()
384 /* wait for ack de-assertion */ in pcie_phy_write()
397 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx8mq_pcie_init_phy()
406 if (imx_pcie->vph && regulator_get_voltage(imx_pcie->vph) > 3000000) in imx8mq_pcie_init_phy()
407 regmap_update_bits(imx_pcie->iomuxc_gpr, in imx8mq_pcie_init_phy()
417 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx_pcie_init_phy()
421 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx_pcie_init_phy()
424 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
426 imx_pcie->tx_deemph_gen1 << 0); in imx_pcie_init_phy()
427 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
429 imx_pcie->tx_deemph_gen2_3p5db << 6); in imx_pcie_init_phy()
430 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
432 imx_pcie->tx_deemph_gen2_6db << 12); in imx_pcie_init_phy()
433 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
435 imx_pcie->tx_swing_full << 18); in imx_pcie_init_phy()
436 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR8, in imx_pcie_init_phy()
438 imx_pcie->tx_swing_low << 25); in imx_pcie_init_phy()
444 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_init_phy()
453 struct device *dev = imx_pcie->pci->dev; in imx7d_pcie_wait_for_phy_pll_lock()
455 if (regmap_read_poll_timeout(imx_pcie->iomuxc_gpr, in imx7d_pcie_wait_for_phy_pll_lock()
469 struct clk_bulk_data *clks = imx_pcie->clks; in imx_setup_phy_mpll()
471 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) in imx_setup_phy_mpll()
474 for (i = 0; i < imx_pcie->num_clks; i++) in imx_setup_phy_mpll()
494 dev_err(imx_pcie->pci->dev, in imx_setup_phy_mpll()
496 return -EINVAL; in imx_setup_phy_mpll()
520 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_IMX_PHY)) in imx_pcie_reset_phy()
547 * make it look like it read all-ones. in imx6q_pcie_abort_handler()
555 val = -1; in imx6q_pcie_abort_handler()
557 regs->uregs[reg] = val; in imx6q_pcie_abort_handler()
558 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
563 regs->uregs[reg] = -1; in imx6q_pcie_abort_handler()
564 regs->ARM_pc += 4; in imx6q_pcie_abort_handler()
578 if (dev->pm_domain) in imx_pcie_attach_pd()
581 imx_pcie->pd_pcie = dev_pm_domain_attach_by_name(dev, "pcie"); in imx_pcie_attach_pd()
582 if (IS_ERR(imx_pcie->pd_pcie)) in imx_pcie_attach_pd()
583 return PTR_ERR(imx_pcie->pd_pcie); in imx_pcie_attach_pd()
585 if (!imx_pcie->pd_pcie) in imx_pcie_attach_pd()
587 link = device_link_add(dev, imx_pcie->pd_pcie, in imx_pcie_attach_pd()
593 return -EINVAL; in imx_pcie_attach_pd()
596 imx_pcie->pd_pcie_phy = dev_pm_domain_attach_by_name(dev, "pcie_phy"); in imx_pcie_attach_pd()
597 if (IS_ERR(imx_pcie->pd_pcie_phy)) in imx_pcie_attach_pd()
598 return PTR_ERR(imx_pcie->pd_pcie_phy); in imx_pcie_attach_pd()
600 link = device_link_add(dev, imx_pcie->pd_pcie_phy, in imx_pcie_attach_pd()
606 return -EINVAL; in imx_pcie_attach_pd()
614 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_enable_ref_clk()
624 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_enable_ref_clk()
632 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_enable_ref_clk()
634 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_enable_ref_clk()
635 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_enable_ref_clk()
645 regmap_update_bits(imx_pcie->iomuxc_gpr, offset, in imx8mm_pcie_enable_ref_clk()
648 regmap_update_bits(imx_pcie->iomuxc_gpr, offset, in imx8mm_pcie_enable_ref_clk()
656 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx7d_pcie_enable_ref_clk()
664 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_clk_enable()
665 struct device *dev = pci->dev; in imx_pcie_clk_enable()
668 ret = clk_bulk_prepare_enable(imx_pcie->num_clks, imx_pcie->clks); in imx_pcie_clk_enable()
672 if (imx_pcie->drvdata->enable_ref_clk) { in imx_pcie_clk_enable()
673 ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); in imx_pcie_clk_enable()
685 clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks); in imx_pcie_clk_enable()
692 if (imx_pcie->drvdata->enable_ref_clk) in imx_pcie_clk_disable()
693 imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); in imx_pcie_clk_disable()
694 clk_bulk_disable_unprepare(imx_pcie->num_clks, imx_pcie->clks); in imx_pcie_clk_disable()
700 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, in imx6sx_pcie_core_reset()
704 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR5, IMX6SX_GPR5_PCIE_BTNRST_RESET, in imx6sx_pcie_core_reset()
711 regmap_update_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_SW_RST, in imx6qp_pcie_core_reset()
724 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_TEST_PD); in imx6q_pcie_core_reset()
725 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR1, IMX6Q_GPR1_PCIE_REF_CLK_EN); in imx6q_pcie_core_reset()
732 struct dw_pcie *pci = imx_pcie->pci; in imx7d_pcie_core_reset()
733 struct device *dev = pci->dev; in imx7d_pcie_core_reset()
747 * The Duty-cycle Corrector calibration must be disabled. in imx7d_pcie_core_reset()
749 * 1. De-assert the G_RST signal by clearing in imx7d_pcie_core_reset()
751 * 2. De-assert DCC_FB_EN by writing data “0x29” to the register in imx7d_pcie_core_reset()
757 * 5. De-assert the CMN_RST signal by clearing register bit in imx7d_pcie_core_reset()
761 if (likely(imx_pcie->phy_base)) { in imx7d_pcie_core_reset()
762 /* De-assert DCC_FB_EN */ in imx7d_pcie_core_reset()
763 writel(PCIE_PHY_CMN_REG4_DCC_FB_EN, imx_pcie->phy_base + PCIE_PHY_CMN_REG4); in imx7d_pcie_core_reset()
766 imx_pcie->phy_base + PCIE_PHY_CMN_REG24); in imx7d_pcie_core_reset()
768 writel(PCIE_PHY_CMN_REG26_ATT_MODE, imx_pcie->phy_base + PCIE_PHY_CMN_REG26); in imx7d_pcie_core_reset()
770 dev_warn(dev, "Unable to apply ERR010728 workaround. DT missing fsl,imx7d-pcie-phy phandle ?\n"); in imx7d_pcie_core_reset()
778 reset_control_assert(imx_pcie->pciephy_reset); in imx_pcie_assert_core_reset()
779 reset_control_assert(imx_pcie->apps_reset); in imx_pcie_assert_core_reset()
781 if (imx_pcie->drvdata->core_reset) in imx_pcie_assert_core_reset()
782 imx_pcie->drvdata->core_reset(imx_pcie, true); in imx_pcie_assert_core_reset()
785 gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 1); in imx_pcie_assert_core_reset()
790 reset_control_deassert(imx_pcie->pciephy_reset); in imx_pcie_deassert_core_reset()
791 reset_control_deassert(imx_pcie->apps_reset); in imx_pcie_deassert_core_reset()
793 if (imx_pcie->drvdata->core_reset) in imx_pcie_deassert_core_reset()
794 imx_pcie->drvdata->core_reset(imx_pcie, false); in imx_pcie_deassert_core_reset()
797 if (imx_pcie->reset_gpiod) { in imx_pcie_deassert_core_reset()
799 gpiod_set_value_cansleep(imx_pcie->reset_gpiod, 0); in imx_pcie_deassert_core_reset()
809 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_wait_for_speed_change()
810 struct device *dev = pci->dev; in imx_pcie_wait_for_speed_change()
823 return -ETIMEDOUT; in imx_pcie_wait_for_speed_change()
829 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_ltssm_enable()
830 u8 offset = dw_pcie_find_capability(imx_pcie->pci, PCI_CAP_ID_EXP); in imx_pcie_ltssm_enable()
833 tmp = dw_pcie_readl_dbi(imx_pcie->pci, offset + PCI_EXP_LNKCAP); in imx_pcie_ltssm_enable()
834 phy_set_speed(imx_pcie->phy, FIELD_GET(PCI_EXP_LNKCAP_SLS, tmp)); in imx_pcie_ltssm_enable()
835 if (drvdata->ltssm_mask) in imx_pcie_ltssm_enable()
836 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, drvdata->ltssm_mask, in imx_pcie_ltssm_enable()
837 drvdata->ltssm_mask); in imx_pcie_ltssm_enable()
839 reset_control_deassert(imx_pcie->apps_reset); in imx_pcie_ltssm_enable()
845 const struct imx_pcie_drvdata *drvdata = imx_pcie->drvdata; in imx_pcie_ltssm_disable()
847 phy_set_speed(imx_pcie->phy, 0); in imx_pcie_ltssm_disable()
848 if (drvdata->ltssm_mask) in imx_pcie_ltssm_disable()
849 regmap_update_bits(imx_pcie->iomuxc_gpr, drvdata->ltssm_off, in imx_pcie_ltssm_disable()
850 drvdata->ltssm_mask, 0); in imx_pcie_ltssm_disable()
852 reset_control_assert(imx_pcie->apps_reset); in imx_pcie_ltssm_disable()
858 struct device *dev = pci->dev; in imx_pcie_start_link()
882 if (pci->max_link_speed > 1) { in imx_pcie_start_link()
887 tmp |= pci->max_link_speed; in imx_pcie_start_link()
899 if (imx_pcie->drvdata->flags & in imx_pcie_start_link()
905 * occurs and we go Gen1 -> yep, Gen1. The difference in imx_pcie_start_link()
939 struct device *dev = pci->dev; in imx_pcie_stop_link()
947 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_add_lut()
948 struct device *dev = pci->dev; in imx_pcie_add_lut()
950 int free = -1; in imx_pcie_add_lut()
955 return -EINVAL; in imx_pcie_add_lut()
958 guard(mutex)(&imx_pcie->lock); in imx_pcie_add_lut()
966 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_add_lut()
968 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, &data1); in imx_pcie_add_lut()
976 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_add_lut()
987 return -ENOSPC; in imx_pcie_add_lut()
993 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA1, data1); in imx_pcie_add_lut()
997 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, data2); in imx_pcie_add_lut()
999 regmap_write(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_ACSCTRL, free); in imx_pcie_add_lut()
1009 guard(mutex)(&imx_pcie->lock); in imx_pcie_remove_lut()
1012 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1014 regmap_read(imx_pcie->iomuxc_gpr, IMX95_PE0_LUT_DATA2, &data2); in imx_pcie_remove_lut()
1016 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1018 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1020 regmap_write(imx_pcie->iomuxc_gpr, in imx_pcie_remove_lut()
1031 struct imx_pcie *imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); in imx_pcie_enable_device()
1038 dev = imx_pcie->pci->dev; in imx_pcie_enable_device()
1041 err_i = of_map_id(dev->of_node, rid, "iommu-map", "iommu-map-mask", in imx_pcie_enable_device()
1051 err_i = -EINVAL; in imx_pcie_enable_device()
1055 err_m = of_map_id(dev->of_node, rid, "msi-map", "msi-map-mask", in imx_pcie_enable_device()
1062 * support it, so return -EINVAL. in imx_pcie_enable_device()
1063 * != 0 NULL msi-map does not exist, use built-in MSI in imx_pcie_enable_device()
1068 return -EINVAL; in imx_pcie_enable_device()
1070 of_node_put(target); /* Find streamID map entry for RID in msi-map */ in imx_pcie_enable_device()
1073 * msi-map iommu-map in imx_pcie_enable_device()
1087 * │ LUT │ 6-bit streamID │ │ in imx_pcie_enable_device()
1089 * └─────┘ 2-bit ctrl ID │ │ in imx_pcie_enable_device()
1101 dev_err(dev, "iommu-map and msi-map entries mismatch!\n"); in imx_pcie_enable_device()
1102 return -EINVAL; in imx_pcie_enable_device()
1119 imx_pcie = to_imx_pcie(to_dw_pcie_from_pp(bridge->sysdata)); in imx_pcie_disable_device()
1126 struct device *dev = pci->dev; in imx_pcie_host_init()
1130 if (imx_pcie->vpcie) { in imx_pcie_host_init()
1131 ret = regulator_enable(imx_pcie->vpcie); in imx_pcie_host_init()
1139 if (pp->bridge && imx_check_flag(imx_pcie, IMX_PCIE_FLAG_HAS_LUT)) { in imx_pcie_host_init()
1140 pp->bridge->enable_device = imx_pcie_enable_device; in imx_pcie_host_init()
1141 pp->bridge->disable_device = imx_pcie_disable_device; in imx_pcie_host_init()
1146 if (imx_pcie->drvdata->init_phy) in imx_pcie_host_init()
1147 imx_pcie->drvdata->init_phy(imx_pcie); in imx_pcie_host_init()
1157 if (imx_pcie->phy) { in imx_pcie_host_init()
1158 ret = phy_init(imx_pcie->phy); in imx_pcie_host_init()
1164 ret = phy_set_mode_ext(imx_pcie->phy, PHY_MODE_PCIE, in imx_pcie_host_init()
1165 imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE ? in imx_pcie_host_init()
1172 ret = phy_power_on(imx_pcie->phy); in imx_pcie_host_init()
1190 phy_power_off(imx_pcie->phy); in imx_pcie_host_init()
1192 phy_exit(imx_pcie->phy); in imx_pcie_host_init()
1196 if (imx_pcie->vpcie) in imx_pcie_host_init()
1197 regulator_disable(imx_pcie->vpcie); in imx_pcie_host_init()
1206 if (imx_pcie->phy) { in imx_pcie_host_exit()
1207 if (phy_power_off(imx_pcie->phy)) in imx_pcie_host_exit()
1208 dev_err(pci->dev, "unable to power off PHY\n"); in imx_pcie_host_exit()
1209 phy_exit(imx_pcie->phy); in imx_pcie_host_exit()
1213 if (imx_pcie->vpcie) in imx_pcie_host_exit()
1214 regulator_disable(imx_pcie->vpcie); in imx_pcie_host_exit()
1227 regmap_set_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); in imx_pcie_pme_turn_off()
1228 regmap_clear_bits(imx_pcie->iomuxc_gpr, IOMUXC_GPR12, IMX6SX_GPR12_PCIE_PM_TURN_OFF); in imx_pcie_pme_turn_off()
1271 dev_err(pci->dev, "UNKNOWN IRQ type\n"); in imx_pcie_ep_raise_irq()
1272 return -EINVAL; in imx_pcie_ep_raise_irq()
1301 * BAR0 | Enable | 64-bit | 1 MB | Programmable Size
1302 * BAR1 | Disable | 32-bit | 64 KB | Fixed Size
1303 * (BAR1 should be disabled if BAR0 is 64-bit)
1304 * BAR2 | Enable | 32-bit | 1 MB | Programmable Size
1305 * BAR3 | Enable | 32-bit | 64 KB | Programmable Size
1306 * BAR4 | Enable | 32-bit | 1 MB | Programmable Size
1307 * BAR5 | Enable | 32-bit | 64 KB | Programmable Size
1321 return imx_pcie->drvdata->epc_features; in imx_pcie_ep_get_features()
1335 struct dw_pcie *pci = imx_pcie->pci; in imx_add_pcie_ep()
1336 struct dw_pcie_rp *pp = &pci->pp; in imx_add_pcie_ep()
1337 struct device *dev = pci->dev; in imx_add_pcie_ep()
1340 ep = &pci->ep; in imx_add_pcie_ep()
1341 ep->ops = &pcie_ep_ops; in imx_add_pcie_ep()
1346 ep->page_size = imx_pcie->drvdata->epc_features->align; in imx_add_pcie_ep()
1361 pci_epc_init_notify(ep->epc); in imx_add_pcie_ep()
1373 struct dw_pcie *pci = imx_pcie->pci; in imx_pcie_msi_save_restore()
1379 imx_pcie->msi_ctrl = val; in imx_pcie_msi_save_restore()
1382 val = imx_pcie->msi_ctrl; in imx_pcie_msi_save_restore()
1393 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx_pcie_suspend_noirq()
1404 imx_pcie->drvdata->enable_ref_clk(imx_pcie, false); in imx_pcie_suspend_noirq()
1406 return dw_pcie_suspend_noirq(imx_pcie->pci); in imx_pcie_suspend_noirq()
1417 if (!(imx_pcie->drvdata->flags & IMX_PCIE_FLAG_SUPPORTS_SUSPEND)) in imx_pcie_resume_noirq()
1421 ret = imx_pcie->drvdata->enable_ref_clk(imx_pcie, true); in imx_pcie_resume_noirq()
1433 ret = dw_pcie_setup_rc(&imx_pcie->pci->pp); in imx_pcie_resume_noirq()
1437 ret = dw_pcie_resume_noirq(imx_pcie->pci); in imx_pcie_resume_noirq()
1453 struct device *dev = &pdev->dev; in imx_pcie_probe()
1457 struct device_node *node = dev->of_node; in imx_pcie_probe()
1463 return -ENOMEM; in imx_pcie_probe()
1467 return -ENOMEM; in imx_pcie_probe()
1469 pci->dev = dev; in imx_pcie_probe()
1470 pci->ops = &dw_pcie_ops; in imx_pcie_probe()
1472 imx_pcie->pci = pci; in imx_pcie_probe()
1473 imx_pcie->drvdata = of_device_get_match_data(dev); in imx_pcie_probe()
1475 mutex_init(&imx_pcie->lock); in imx_pcie_probe()
1477 if (imx_pcie->drvdata->ops) in imx_pcie_probe()
1478 pci->pp.ops = imx_pcie->drvdata->ops; in imx_pcie_probe()
1480 pci->pp.ops = &imx_pcie_host_dw_pme_ops; in imx_pcie_probe()
1483 np = of_parse_phandle(node, "fsl,imx7d-pcie-phy", 0); in imx_pcie_probe()
1492 imx_pcie->phy_base = devm_ioremap_resource(dev, &res); in imx_pcie_probe()
1493 if (IS_ERR(imx_pcie->phy_base)) in imx_pcie_probe()
1494 return PTR_ERR(imx_pcie->phy_base); in imx_pcie_probe()
1498 imx_pcie->reset_gpiod = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_HIGH); in imx_pcie_probe()
1499 if (IS_ERR(imx_pcie->reset_gpiod)) in imx_pcie_probe()
1500 return dev_err_probe(dev, PTR_ERR(imx_pcie->reset_gpiod), in imx_pcie_probe()
1502 gpiod_set_consumer_name(imx_pcie->reset_gpiod, "PCIe reset"); in imx_pcie_probe()
1505 imx_pcie->num_clks = devm_clk_bulk_get_all(dev, &imx_pcie->clks); in imx_pcie_probe()
1506 if (imx_pcie->num_clks < 0) in imx_pcie_probe()
1507 return dev_err_probe(dev, imx_pcie->num_clks, in imx_pcie_probe()
1511 imx_pcie->phy = devm_phy_get(dev, "pcie-phy"); in imx_pcie_probe()
1512 if (IS_ERR(imx_pcie->phy)) in imx_pcie_probe()
1513 return dev_err_probe(dev, PTR_ERR(imx_pcie->phy), in imx_pcie_probe()
1518 imx_pcie->apps_reset = devm_reset_control_get_exclusive(dev, "apps"); in imx_pcie_probe()
1519 if (IS_ERR(imx_pcie->apps_reset)) in imx_pcie_probe()
1520 return dev_err_probe(dev, PTR_ERR(imx_pcie->apps_reset), in imx_pcie_probe()
1525 imx_pcie->pciephy_reset = devm_reset_control_get_exclusive(dev, "pciephy"); in imx_pcie_probe()
1526 if (IS_ERR(imx_pcie->pciephy_reset)) in imx_pcie_probe()
1527 return dev_err_probe(dev, PTR_ERR(imx_pcie->pciephy_reset), in imx_pcie_probe()
1531 switch (imx_pcie->drvdata->variant) { in imx_pcie_probe()
1536 return dev_err_probe(dev, -ENODEV, "no \"linux,pci-domain\" property in devicetree\n"); in imx_pcie_probe()
1538 imx_pcie->controller_id = domain; in imx_pcie_probe()
1544 if (imx_pcie->drvdata->gpr) { in imx_pcie_probe()
1546 imx_pcie->iomuxc_gpr = in imx_pcie_probe()
1547 syscon_regmap_lookup_by_compatible(imx_pcie->drvdata->gpr); in imx_pcie_probe()
1548 if (IS_ERR(imx_pcie->iomuxc_gpr)) in imx_pcie_probe()
1549 return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), in imx_pcie_probe()
1566 imx_pcie->iomuxc_gpr = devm_regmap_init_mmio(dev, off, ®map_config); in imx_pcie_probe()
1567 if (IS_ERR(imx_pcie->iomuxc_gpr)) in imx_pcie_probe()
1568 return dev_err_probe(dev, PTR_ERR(imx_pcie->iomuxc_gpr), in imx_pcie_probe()
1573 if (of_property_read_u32(node, "fsl,tx-deemph-gen1", in imx_pcie_probe()
1574 &imx_pcie->tx_deemph_gen1)) in imx_pcie_probe()
1575 imx_pcie->tx_deemph_gen1 = 0; in imx_pcie_probe()
1577 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-3p5db", in imx_pcie_probe()
1578 &imx_pcie->tx_deemph_gen2_3p5db)) in imx_pcie_probe()
1579 imx_pcie->tx_deemph_gen2_3p5db = 0; in imx_pcie_probe()
1581 if (of_property_read_u32(node, "fsl,tx-deemph-gen2-6db", in imx_pcie_probe()
1582 &imx_pcie->tx_deemph_gen2_6db)) in imx_pcie_probe()
1583 imx_pcie->tx_deemph_gen2_6db = 20; in imx_pcie_probe()
1585 if (of_property_read_u32(node, "fsl,tx-swing-full", in imx_pcie_probe()
1586 &imx_pcie->tx_swing_full)) in imx_pcie_probe()
1587 imx_pcie->tx_swing_full = 127; in imx_pcie_probe()
1589 if (of_property_read_u32(node, "fsl,tx-swing-low", in imx_pcie_probe()
1590 &imx_pcie->tx_swing_low)) in imx_pcie_probe()
1591 imx_pcie->tx_swing_low = 127; in imx_pcie_probe()
1594 pci->max_link_speed = 1; in imx_pcie_probe()
1595 of_property_read_u32(node, "fsl,max-link-speed", &pci->max_link_speed); in imx_pcie_probe()
1597 imx_pcie->vpcie = devm_regulator_get_optional(&pdev->dev, "vpcie"); in imx_pcie_probe()
1598 if (IS_ERR(imx_pcie->vpcie)) { in imx_pcie_probe()
1599 if (PTR_ERR(imx_pcie->vpcie) != -ENODEV) in imx_pcie_probe()
1600 return PTR_ERR(imx_pcie->vpcie); in imx_pcie_probe()
1601 imx_pcie->vpcie = NULL; in imx_pcie_probe()
1604 imx_pcie->vph = devm_regulator_get_optional(&pdev->dev, "vph"); in imx_pcie_probe()
1605 if (IS_ERR(imx_pcie->vph)) { in imx_pcie_probe()
1606 if (PTR_ERR(imx_pcie->vph) != -ENODEV) in imx_pcie_probe()
1607 return PTR_ERR(imx_pcie->vph); in imx_pcie_probe()
1608 imx_pcie->vph = NULL; in imx_pcie_probe()
1617 pci->use_parent_dt_ranges = true; in imx_pcie_probe()
1618 if (imx_pcie->drvdata->mode == DW_PCIE_EP_TYPE) { in imx_pcie_probe()
1623 pci->pp.use_atu_msg = true; in imx_pcie_probe()
1624 ret = dw_pcie_host_init(&pci->pp); in imx_pcie_probe()
1656 .gpr = "fsl,imx6q-iomuxc-gpr",
1670 .gpr = "fsl,imx6q-iomuxc-gpr",
1686 .gpr = "fsl,imx6q-iomuxc-gpr",
1701 .gpr = "fsl,imx7d-iomuxc-gpr",
1712 .gpr = "fsl,imx8mq-iomuxc-gpr",
1725 .gpr = "fsl,imx8mm-iomuxc-gpr",
1735 .gpr = "fsl,imx8mp-iomuxc-gpr",
1762 .gpr = "fsl,imx8mq-iomuxc-gpr",
1776 .gpr = "fsl,imx8mm-iomuxc-gpr",
1787 .gpr = "fsl,imx8mp-iomuxc-gpr",
1814 { .compatible = "fsl,imx6q-pcie", .data = &drvdata[IMX6Q], },
1815 { .compatible = "fsl,imx6sx-pcie", .data = &drvdata[IMX6SX], },
1816 { .compatible = "fsl,imx6qp-pcie", .data = &drvdata[IMX6QP], },
1817 { .compatible = "fsl,imx7d-pcie", .data = &drvdata[IMX7D], },
1818 { .compatible = "fsl,imx8mq-pcie", .data = &drvdata[IMX8MQ], },
1819 { .compatible = "fsl,imx8mm-pcie", .data = &drvdata[IMX8MM], },
1820 { .compatible = "fsl,imx8mp-pcie", .data = &drvdata[IMX8MP], },
1821 { .compatible = "fsl,imx8q-pcie", .data = &drvdata[IMX8Q], },
1822 { .compatible = "fsl,imx95-pcie", .data = &drvdata[IMX95], },
1823 { .compatible = "fsl,imx8mq-pcie-ep", .data = &drvdata[IMX8MQ_EP], },
1824 { .compatible = "fsl,imx8mm-pcie-ep", .data = &drvdata[IMX8MM_EP], },
1825 { .compatible = "fsl,imx8mp-pcie-ep", .data = &drvdata[IMX8MP_EP], },
1826 { .compatible = "fsl,imx8q-pcie-ep", .data = &drvdata[IMX8Q_EP], },
1827 { .compatible = "fsl,imx95-pcie-ep", .data = &drvdata[IMX95_EP], },
1833 .name = "imx6q-pcie",
1845 struct pci_bus *bus = dev->bus; in imx_pcie_quirk()
1846 struct dw_pcie_rp *pp = bus->sysdata; in imx_pcie_quirk()
1849 if (!bus->dev.parent || !bus->dev.parent->parent) in imx_pcie_quirk()
1853 if (bus->dev.parent->parent->driver != &imx_pcie_driver.driver) in imx_pcie_quirk()
1864 if (imx_pcie->drvdata->dbi_length) { in imx_pcie_quirk()
1865 dev->cfg_size = imx_pcie->drvdata->dbi_length; in imx_pcie_quirk()
1866 dev_info(&dev->dev, "Limiting cfg_size to %d\n", in imx_pcie_quirk()
1867 dev->cfg_size); in imx_pcie_quirk()
1881 return -ENODEV; in imx_pcie_init()
1887 * by kernel and since imx6q_pcie_abort_handler() is a no-op, in imx_pcie_init()
1892 "external abort on non-linefetch"); in imx_pcie_init()