Lines Matching +full:0 +full:xf0ffffff
25 {2, 1641, grp_0}, /* ACH 0 */
37 {0, 0, 0}, /* FWCMDQ */
38 {0, 0, 0}, /* BMC */
39 {0, 0, 0}, /* H2D */
43 1651, /* Group 0 */
46 0, /* WP threshold */
165 .ref_rate = {R_BE_TRXPTCL_RESP_1, B_BE_WMAC_RESP_REF_RATE_SEL, 0},
172 0xf},
175 0x0},
226 [RTW89_EFUSE_BLOCK_SYS] = {.offset = 0x00000, .size = 0x310},
227 [RTW89_EFUSE_BLOCK_RF] = {.offset = 0x10000, .size = 0x240},
228 [RTW89_EFUSE_BLOCK_HCI_DIG_PCIE_SDIO] = {.offset = 0x20000, .size = 0x4800},
229 [RTW89_EFUSE_BLOCK_HCI_DIG_USB] = {.offset = 0x30000, .size = 0x890},
230 [RTW89_EFUSE_BLOCK_HCI_PHY_PCIE] = {.offset = 0x40000, .size = 0x200},
231 [RTW89_EFUSE_BLOCK_HCI_PHY_USB3] = {.offset = 0x50000, .size = 0x80},
232 [RTW89_EFUSE_BLOCK_HCI_PHY_USB2] = {.offset = 0x60000, .size = 0x0},
233 [RTW89_EFUSE_BLOCK_ADIE] = {.offset = 0x70000, .size = 0x10},
240 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
241 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
242 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
243 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
244 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
245 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x30, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
246 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
247 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
248 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x2, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
250 0x1, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
252 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_SHARE_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
253 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BTG_PATH_A, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
254 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_SHARE_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
255 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BTG_PATH_B, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
256 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x1a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
257 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA0_B, 0x2a, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
258 rtw89_phy_write32_idx(rtwdev, R_PMAC_GNT, B_PMAC_GNT_P1, 0xc, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
259 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_BT_SHARE, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
260 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_RX_BT_SG0, 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
262 0x0, phy_idx); in rtw8922a_ctrl_btg_bt_rx()
321 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0x02); in rtw8922a_pwr_on_func()
324 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x01, 0x01); in rtw8922a_pwr_on_func()
330 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x40, 0x40); in rtw8922a_pwr_on_func()
336 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x20, 0x20); in rtw8922a_pwr_on_func()
339 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x04, 0x04); in rtw8922a_pwr_on_func()
342 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x08, 0x08); in rtw8922a_pwr_on_func()
345 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x10); in rtw8922a_pwr_on_func()
348 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
351 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xEB, 0xFF); in rtw8922a_pwr_on_func()
354 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x01, 0x01); in rtw8922a_pwr_on_func()
357 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x02, 0x02); in rtw8922a_pwr_on_func()
360 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x80); in rtw8922a_pwr_on_func()
363 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF1, 0, 0x40); in rtw8922a_pwr_on_func()
366 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_XREF_RF2, 0, 0x40); in rtw8922a_pwr_on_func()
369 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL_1, 0x40, 0x60); in rtw8922a_pwr_on_func()
409 return 0; in rtw8922a_pwr_on_func()
417 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x10, 0x10); in rtw8922a_pwr_off_func()
420 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x08); in rtw8922a_pwr_off_func()
423 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x04); in rtw8922a_pwr_off_func()
426 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S0, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
429 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_WL_RFC_S1, 0xC6, 0xFF); in rtw8922a_pwr_off_func()
432 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0x80, 0x80); in rtw8922a_pwr_off_func()
435 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x02); in rtw8922a_pwr_off_func()
438 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x01); in rtw8922a_pwr_off_func()
441 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x02, 0xFF); in rtw8922a_pwr_off_func()
444 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_PLL, 0x00, 0xFF); in rtw8922a_pwr_off_func()
457 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x20); in rtw8922a_pwr_off_func()
463 ret = rtw89_mac_write_xtal_si(rtwdev, XTAL_SI_ANAPAR_WL, 0, 0x40); in rtw8922a_pwr_off_func()
493 rtw89_write32(rtwdev, R_BE_WLLPS_CTRL, 0x0000A1B2); in rtw8922a_pwr_off_func()
496 rtw89_write32(rtwdev, R_BE_UDM1, 0); in rtw8922a_pwr_off_func()
498 return 0; in rtw8922a_pwr_off_func()
512 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_efuse_parsing_tssi()
516 for (j = 0; j < TSSI_CCK_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
518 "[TSSI][EFUSE] path=%d cck[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
528 for (j = 0; j < TSSI_MCS_CH_GROUP_NUM; j++) in rtw8922a_efuse_parsing_tssi()
530 "[TSSI][EFUSE] path=%d mcs[%d]=0x%x\n", in rtw8922a_efuse_parsing_tssi()
571 for (j = 0; j < RTW89_GAIN_OFFSET_NR; j++) { in rtw8922a_efuse_parsing_gain_offset()
573 if (t != 0xff) in rtw8922a_efuse_parsing_gain_offset()
575 if (t != 0x0) in rtw8922a_efuse_parsing_gain_offset()
579 if (t & 0x80) in rtw8922a_efuse_parsing_gain_offset()
580 gain->offset[i][j] = (t ^ 0x7f) + 1; in rtw8922a_efuse_parsing_gain_offset()
592 for (i = 0; i < ETH_ALEN; i += 2, addr += 2) { in rtw8922a_read_efuse_mac_addr()
594 efuse->addr[i] = val & 0xff; in rtw8922a_read_efuse_mac_addr()
604 rtw8922a_read_efuse_mac_addr(rtwdev, 0x3104); in rtw8922a_read_efuse_pci_sdio()
606 ether_addr_copy(efuse->addr, log_map + 0x001A); in rtw8922a_read_efuse_pci_sdio()
608 return 0; in rtw8922a_read_efuse_pci_sdio()
613 rtw8922a_read_efuse_mac_addr(rtwdev, 0x4078); in rtw8922a_read_efuse_usb()
615 return 0; in rtw8922a_read_efuse_usb()
625 efuse->country_code[0] = map->country_code[0]; in rtw8922a_read_efuse_rf()
632 return 0; in rtw8922a_read_efuse_rf()
646 return 0; in rtw8922a_read_efuse()
651 #define THM_TRIM_MAGNITUDE_MASK GENMASK(5, 0)
656 static const u32 thm_trim_addr[RF_PATH_NUM_8922A] = {0x1706, 0x1733}; in rtw8922a_phycap_parsing_thermal_trim()
664 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_thermal_trim()
666 if (pg_th == 0xff) { in rtw8922a_phycap_parsing_thermal_trim()
667 info->thermal_trim[i] = 0; in rtw8922a_phycap_parsing_thermal_trim()
680 "[THERMAL][TRIM] path=%d thermal_trim=0x%x (%d)\n", in rtw8922a_phycap_parsing_thermal_trim()
690 static const u32 pabias_trim_addr[RF_PATH_NUM_8922A] = {0x1707, 0x1734}; in rtw8922a_phycap_parsing_pa_bias_trim()
691 static const u32 check_pa_pad_trim_addr = 0x1700; in rtw8922a_phycap_parsing_pa_bias_trim()
698 if (val != 0xff) in rtw8922a_phycap_parsing_pa_bias_trim()
701 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pa_bias_trim()
705 "[PA_BIAS][TRIM] path=%d pa_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pa_bias_trim()
723 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pa_bias_trim()
724 pabias_2g = FIELD_GET(GENMASK(3, 0), info->pa_bias_trim[i]); in rtw8922a_pa_bias_trim()
728 "[PA_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pa_bias_trim()
739 static const u32 pad_bias_trim_addr[RF_PATH_NUM_8922A] = {0x1708, 0x1735}; in rtw8922a_phycap_parsing_pad_bias_trim()
744 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_phycap_parsing_pad_bias_trim()
748 "[PAD_BIAS][TRIM] path=%d pad_bias_trim=0x%x\n", in rtw8922a_phycap_parsing_pad_bias_trim()
765 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_pad_bias_trim()
766 pad_bias_2g = u8_get_bits(info->pad_bias_trim[i], GENMASK(3, 0)); in rtw8922a_pad_bias_trim()
770 "[PAD_BIAS][TRIM] path=%d 2G=0x%x 5G=0x%x\n", in rtw8922a_pad_bias_trim()
784 return 0; in rtw8922a_read_phycap()
800 u8 txsb20 = 0, txsb40 = 0, txsb80 = 0; in rtw8922a_set_channel_mac()
838 txsb = 0; in rtw8922a_set_channel_mac()
871 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
873 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x41); in rtw8922a_set_channel_mac()
877 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_T1_MASK, 0x3f); in rtw8922a_set_channel_mac()
879 rtw89_write32_mask(rtwdev, reg, B_BE_SIFS_MACTXEN_TB_T1_MASK, 0x3e); in rtw8922a_set_channel_mac()
885 0x1fe4f, 0x1ff5e, 0x2006c, 0x2017b, 0x2028a, 0x20399, 0x204a8, 0x205b6,
886 0x206c5, 0x207d4, 0x208e3, 0x209f2, 0x20b00, 0x20d8a
890 0x2bdac, 0x2bf21, 0x2c095, 0x2c209, 0x2c37e, 0x2c4f2, 0x2c666, 0x2c7db,
891 0x2c94f, 0x2cac3, 0x2cc38, 0x2cdac, 0x2cf21, 0x2d29e
912 return 0; in rtw8922a_ctrl_sco_cck()
923 { .addr = 0x41E8, .mask = 0xFF00},
924 { .addr = 0x41E8, .mask = 0xFF0000},
925 { .addr = 0x41E8, .mask = 0xFF000000},
926 { .addr = 0x41EC, .mask = 0xFF},
927 { .addr = 0x41EC, .mask = 0xFF00},
928 { .addr = 0x41EC, .mask = 0xFF0000},
929 { .addr = 0x41EC, .mask = 0xFF000000},
930 { .addr = 0x41F0, .mask = 0xFF}
934 { .addr = 0x41F4, .mask = 0xFF},
935 { .addr = 0x41F4, .mask = 0xFF00},
936 { .addr = 0x41F4, .mask = 0xFF0000},
937 { .addr = 0x41F4, .mask = 0xFF000000}
941 { .addr = 0x41F0, .mask = 0xFF0000},
942 { .addr = 0x41F0, .mask = 0xFF000000}
946 { .addr = 0x41F0, .mask = 0xFF00}
950 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
951 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
952 { .gain_g = {0x409c, 0x449c}, .gain_a = {0x406C, 0x446C},
953 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
954 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
955 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
956 { .gain_g = {0x40a0, 0x44a0}, .gain_a = {0x4070, 0x4470},
957 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
958 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
959 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
960 { .gain_g = {0x40a4, 0x44a4}, .gain_a = {0x4074, 0x4474},
961 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF0000},
962 { .gain_g = {0x40a8, 0x44a8}, .gain_a = {0x4078, 0x4478},
963 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF},
967 { .gain_g = {0x4054, 0x4454}, .gain_a = {0x4054, 0x4454},
968 .gain_g_mask = 0x7FC0000, .gain_a_mask = 0x1FF},
969 { .gain_g = {0x4058, 0x4458}, .gain_a = {0x4054, 0x4454},
970 .gain_g_mask = 0x1FF, .gain_a_mask = 0x3FE00 },
974 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x4078, 0x4478},
975 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
976 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
977 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
978 { .gain_g = {0x40ac, 0x44ac}, .gain_a = {0x407c, 0x447c},
979 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
980 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
981 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF0000},
982 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x407c, 0x447c},
983 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF000000},
984 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
985 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF},
986 { .gain_g = {0x40b0, 0x44b0}, .gain_a = {0x4080, 0x4480},
987 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF00},
991 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4080, 0x4480},
992 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
993 { .gain_g = {0x40b4, 0x44b4}, .gain_a = {0x4084, 0x4484},
994 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
995 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
996 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
997 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
998 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
999 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4084, 0x4484},
1000 .gain_g_mask = 0xFF0000, .gain_a_mask = 0xFF000000},
1001 { .gain_g = {0x40b8, 0x44b8}, .gain_a = {0x4088, 0x4488},
1002 .gain_g_mask = 0xFF000000, .gain_a_mask = 0xFF},
1003 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1004 .gain_g_mask = 0xFF, .gain_a_mask = 0xFF00},
1005 { .gain_g = {0x40bc, 0x44bc}, .gain_a = {0x4088, 0x4488},
1006 .gain_g_mask = 0xFF00, .gain_a_mask = 0xFF0000},
1023 u32 reg_path_ofst = 0; in rtw8922a_set_rpl_gain()
1030 reg_path_ofst = 0x400; in rtw8922a_set_rpl_gain()
1032 for (i = 0; i < RTW89_BW20_SC_160M; i++) { in rtw8922a_set_rpl_gain()
1039 for (i = 0; i < RTW89_BW20_SC_80M; i++) { in rtw8922a_set_rpl_gain()
1046 for (i = 0; i < RTW89_BW20_SC_40M; i++) { in rtw8922a_set_rpl_gain()
1053 for (i = 0; i < RTW89_BW20_SC_20M; i++) { in rtw8922a_set_rpl_gain()
1077 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1089 for (i = 0; i < TIA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1101 for (i = 0; i < LNA_GAIN_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1113 for (i = 0; i < TIA_LNA_OP1DB_NUM; i++) { in rtw8922a_set_lna_tia_gain()
1141 u8 fraction = value & 0x3; in rtw8922a_set_rx_gain_normal_cck()
1145 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1147 (0x4 - fraction) << 1); in rtw8922a_set_rx_gain_normal_cck()
1151 value + 1 + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1153 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW20, 0); in rtw8922a_set_rx_gain_normal_cck()
1154 rtw89_phy_write32_mask(rtwdev, R_MGAIN_BIAS, B_MGAIN_BIAS_BW40, 0); in rtw8922a_set_rx_gain_normal_cck()
1158 value + 0xdc); in rtw8922a_set_rx_gain_normal_cck()
1166 static const u32 rssi_tb_bias_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1167 static const u32 rssi_tb_ext_comp[2] = {0x4208, 0x4608}; in rtw8922a_set_rx_gain_normal_ofdm()
1168 static const u32 rssi_ofst_addr[2] = {0x40c8, 0x44c8}; in rtw8922a_set_rx_gain_normal_ofdm()
1169 static const u32 rpl_bias_comp[2] = {0x41e8, 0x45e8}; in rtw8922a_set_rx_gain_normal_ofdm()
1170 static const u32 rpl_ext_comp[2] = {0x41f8, 0x45f8}; in rtw8922a_set_rx_gain_normal_ofdm()
1178 rtw89_phy_write32_mask(rtwdev, rssi_ofst_addr[path], 0xff000000, value + 0xF8); in rtw8922a_set_rx_gain_normal_ofdm()
1187 rtw89_phy_write32_mask(rtwdev, rpl_bias_comp[path], 0xff, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1188 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1189 rtw89_phy_write32_mask(rtwdev, rpl_ext_comp[path], 0xff00, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1191 rtw89_phy_write32_mask(rtwdev, rssi_tb_bias_comp[path], 0xff0000, v1); in rtw8922a_set_rx_gain_normal_ofdm()
1192 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff0000, v2); in rtw8922a_set_rx_gain_normal_ofdm()
1193 rtw89_phy_write32_mask(rtwdev, rssi_tb_ext_comp[path], 0xff000000, v3); in rtw8922a_set_rx_gain_normal_ofdm()
1215 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3b13ff, phy_idx); in rtw8922a_set_cck_parameters()
1216 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x1c42de, phy_idx); in rtw8922a_set_cck_parameters()
1217 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0xfdb0ad, phy_idx); in rtw8922a_set_cck_parameters()
1218 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0xf60f6e, phy_idx); in rtw8922a_set_cck_parameters()
1219 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfd8f92, phy_idx); in rtw8922a_set_cck_parameters()
1220 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0x02d011, phy_idx); in rtw8922a_set_cck_parameters()
1221 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0x01c02c, phy_idx); in rtw8922a_set_cck_parameters()
1222 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xfff00a, phy_idx); in rtw8922a_set_cck_parameters()
1224 rtw89_phy_write32_idx(rtwdev, R_PCOEFF01, B_PCOEFF01, 0x3a63ca, phy_idx); in rtw8922a_set_cck_parameters()
1225 rtw89_phy_write32_idx(rtwdev, R_PCOEFF23, B_PCOEFF23, 0x2a833f, phy_idx); in rtw8922a_set_cck_parameters()
1226 rtw89_phy_write32_idx(rtwdev, R_PCOEFF45, B_PCOEFF45, 0x1491f8, phy_idx); in rtw8922a_set_cck_parameters()
1227 rtw89_phy_write32_idx(rtwdev, R_PCOEFF67, B_PCOEFF67, 0x03c0b0, phy_idx); in rtw8922a_set_cck_parameters()
1228 rtw89_phy_write32_idx(rtwdev, R_PCOEFF89, B_PCOEFF89, 0xfccff1, phy_idx); in rtw8922a_set_cck_parameters()
1229 rtw89_phy_write32_idx(rtwdev, R_PCOEFFAB, B_PCOEFFAB, 0xfccfc3, phy_idx); in rtw8922a_set_cck_parameters()
1230 rtw89_phy_write32_idx(rtwdev, R_PCOEFFCD, B_PCOEFFCD, 0xfebfdc, phy_idx); in rtw8922a_set_cck_parameters()
1231 rtw89_phy_write32_idx(rtwdev, R_PCOEFFEF, B_PCOEFFEF, 0xffdff7, phy_idx); in rtw8922a_set_cck_parameters()
1239 static const u32 band_sel[2] = {0x4160, 0x4560}; in rtw8922a_ctrl_ch()
1279 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1280 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1281 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1282 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1283 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1284 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1287 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1288 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1289 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1290 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1291 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1292 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1295 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1296 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1297 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_PRICH, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1298 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1299 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1300 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1303 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1304 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1306 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1307 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1308 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1311 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x2, phy_idx); in rtw8922a_ctrl_bw()
1312 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1314 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1315 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1316 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1319 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_CHBW_BW, 0x3, phy_idx); in rtw8922a_ctrl_bw()
1320 rtw89_phy_write32_idx(rtwdev, R_FC0INV_SBW, B_SMALLBW, 0x0, phy_idx); in rtw8922a_ctrl_bw()
1322 rtw89_phy_write32_idx(rtwdev, R_DAC_CLK, B_DAC_CLK, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1323 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP0, B_GAIN_MAP0_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1324 rtw89_phy_write32_idx(rtwdev, R_GAIN_MAP1, B_GAIN_MAP1_EN, 0x1, phy_idx); in rtw8922a_ctrl_bw()
1335 rtw89_phy_write32_idx(rtwdev, R_FC0, B_BW40_2XFFT, 0, phy_idx); in rtw8922a_ctrl_bw()
1341 return 0; in rtw8922a_spur_freq()
1356 if (spur_freq == 0) { in rtw8922a_set_csi_tone_idx()
1358 0, phy_idx); in rtw8922a_set_csi_tone_idx()
1373 .notch1_idx = {0x41a0, 0xFF},
1374 .notch1_frac_idx = {0x41a0, 0xC00},
1375 .notch1_en = {0x41a0, 0x1000},
1376 .notch2_idx = {0x41ac, 0xFF},
1377 .notch2_frac_idx = {0x41ac, 0xC00},
1378 .notch2_en = {0x41ac, 0x1000},
1381 .notch1_idx = {0x45a0, 0xFF},
1382 .notch1_frac_idx = {0x45a0, 0xC00},
1383 .notch1_en = {0x45a0, 0x1000},
1384 .notch2_idx = {0x45ac, 0xFF},
1385 .notch2_frac_idx = {0x45ac, 0xC00},
1386 .notch2_en = {0x45ac, 0x1000},
1403 if (spur_freq == 0) { in rtw8922a_set_nbi_tone_idx()
1405 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1407 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1443 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1447 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1455 nbi->notch1_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1459 nbi->notch2_en.mask, 0, phy_idx); in rtw8922a_set_nbi_tone_idx()
1475 u32 cr_ofst = 0x0; in rtw8922a_ctrl_afe_dac()
1478 cr_ofst = 0x100; in rtw8922a_ctrl_afe_dac()
1486 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xE); in rtw8922a_ctrl_afe_dac()
1487 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x7); in rtw8922a_ctrl_afe_dac()
1490 rtw89_phy_write32_mask(rtwdev, R_AFEDAC0 + cr_ofst, B_AFEDAC0, 0xD); in rtw8922a_ctrl_afe_dac()
1491 rtw89_phy_write32_mask(rtwdev, R_AFEDAC1 + cr_ofst, B_AFEDAC1, 0x6); in rtw8922a_ctrl_afe_dac()
1499 {0x6990, 0x00000000},
1500 {0x6994, 0x00000000},
1501 {0x6998, 0x00000000},
1502 {0x6820, 0xFFFFFFFE},
1503 {0x6800, 0xC0000FFE},
1504 {0x6808, 0x76543210},
1505 {0x6814, 0xBFBFB000},
1506 {0x6818, 0x0478C009},
1507 {0x6800, 0xC0000FFF},
1508 {0x6820, 0xFFFFFFFF},
1512 {0x6990, 0x00000000},
1513 {0x6994, 0x00000000},
1514 {0x6998, 0x00000000},
1515 {0x6820, 0xFFFFFFFE},
1516 {0x6800, 0xC0000FFE},
1517 {0x6808, 0x76543210},
1518 {0x6814, 0xBFBFB000},
1519 {0x6818, 0x0478C009},
1520 {0x6800, 0xC0000FFF},
1521 {0x6820, 0xFFFFFFFF},
1538 for (i = 0; i < size; i++, reg++) in rtw8922a_bbmcu_cr_init()
1549 u32 rdy = 0; in rtw8922a_bb_preinit()
1554 rtw89_write32_mask(rtwdev, R_BE_DMAC_SYS_CR32B, dmac_sys_mask[phy_idx], 0x7FF9); in rtw8922a_bb_preinit()
1555 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1556 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, bbrst_mask[phy_idx], 0x0); in rtw8922a_bb_preinit()
1557 rtw89_write32_mask(rtwdev, R_BE_FEN_RST_ENABLE, glbrst_mask[phy_idx], 0x1); in rtw8922a_bb_preinit()
1559 rtw89_write32_mask(rtwdev, R_BE_MEM_PWR_CTRL, B_BE_MEM_BBMCU0_DS_V1, 0); in rtw8922a_bb_preinit()
1573 rtw89_phy_set_phy_regs(rtwdev, R_TXFCTR, B_TXFCTR_THD, 0x200); in rtw8922a_bb_postinit()
1574 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_EHT_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1575 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_HE_RATE_TH, 0xA); in rtw8922a_bb_postinit()
1576 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_HT_VHT_TH, 0xAAA); in rtw8922a_bb_postinit()
1577 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE, B_EHT_MCS14, 0x1); in rtw8922a_bb_postinit()
1578 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE2, B_EHT_MCS15, 0x1); in rtw8922a_bb_postinit()
1579 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_EHTTB_EN, 0x0); in rtw8922a_bb_postinit()
1580 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEERSU_EN, 0x0); in rtw8922a_bb_postinit()
1581 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_HEMU_EN, 0x0); in rtw8922a_bb_postinit()
1582 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE3, B_TB_EN, 0x0); in rtw8922a_bb_postinit()
1583 rtw89_phy_set_phy_regs(rtwdev, R_SU_PUNC, B_SU_PUNC_EN, 0x1); in rtw8922a_bb_postinit()
1584 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_HWGEN_EN, 0x1); in rtw8922a_bb_postinit()
1585 rtw89_phy_set_phy_regs(rtwdev, R_BEDGE5, B_PWROFST_COMP, 0x1); in rtw8922a_bb_postinit()
1586 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_BY_SLOPE, 0x1); in rtw8922a_bb_postinit()
1587 rtw89_phy_set_phy_regs(rtwdev, R_MAG_A, B_MGA_AEND, 0xe0); in rtw8922a_bb_postinit()
1588 rtw89_phy_set_phy_regs(rtwdev, R_MAG_AB, B_MAG_AB, 0xe0c000); in rtw8922a_bb_postinit()
1589 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_A, 0x3FE0); in rtw8922a_bb_postinit()
1590 rtw89_phy_set_phy_regs(rtwdev, R_SLOPE, B_SLOPE_B, 0x3FE0); in rtw8922a_bb_postinit()
1591 rtw89_phy_set_phy_regs(rtwdev, R_SC_CORNER, B_SC_CORNER, 0x200); in rtw8922a_bb_postinit()
1592 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x0, phy_idx); in rtw8922a_bb_postinit()
1593 rtw89_phy_write32_idx(rtwdev, R_UDP_COEEF, B_UDP_COEEF, 0x1, phy_idx); in rtw8922a_bb_postinit()
1603 B_RXCCA_BE1_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1604 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x0, phy_idx); in rtw8922a_bb_reset_en()
1606 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1607 rtw89_phy_write32_idx(rtwdev, R_PD_CTRL, B_PD_HIT_DIS, 0x1, phy_idx); in rtw8922a_bb_reset_en()
1609 rtw89_phy_write32_idx(rtwdev, R_RSTB_ASYNC, B_RSTB_ASYNC_ALL, 0, phy_idx); in rtw8922a_bb_reset_en()
1618 {0x11A00, 0x21C86900}, in rtw8922a_ctrl_tx_path_tmac()
1619 {0x11A04, 0x00E4E433}, in rtw8922a_ctrl_tx_path_tmac()
1620 {0x11A08, 0x39390CC9}, in rtw8922a_ctrl_tx_path_tmac()
1621 {0x11A0C, 0x4E433240}, in rtw8922a_ctrl_tx_path_tmac()
1622 {0x11A10, 0x90CC900E}, in rtw8922a_ctrl_tx_path_tmac()
1623 {0x11A14, 0x00240393}, in rtw8922a_ctrl_tx_path_tmac()
1624 {0x11A18, 0x201C8600}, in rtw8922a_ctrl_tx_path_tmac()
1626 int ret = 0; in rtw8922a_ctrl_tx_path_tmac()
1630 rtw89_phy_write32_idx(rtwdev, R_MAC_SEL, B_MAC_SEL, 0x0, phy_idx); in rtw8922a_ctrl_tx_path_tmac()
1633 return 0; in rtw8922a_ctrl_tx_path_tmac()
1636 path_com_cr[0].data = 0x21C82900; in rtw8922a_ctrl_tx_path_tmac()
1637 path_com_cr[1].data = 0x00E4E431; in rtw8922a_ctrl_tx_path_tmac()
1638 path_com_cr[2].data = 0x39390C49; in rtw8922a_ctrl_tx_path_tmac()
1639 path_com_cr[3].data = 0x4E431240; in rtw8922a_ctrl_tx_path_tmac()
1640 path_com_cr[4].data = 0x90C4900E; in rtw8922a_ctrl_tx_path_tmac()
1641 path_com_cr[6].data = 0x201C8200; in rtw8922a_ctrl_tx_path_tmac()
1643 path_com_cr[0].data = 0x21C04900; in rtw8922a_ctrl_tx_path_tmac()
1644 path_com_cr[1].data = 0x00E4E032; in rtw8922a_ctrl_tx_path_tmac()
1645 path_com_cr[2].data = 0x39380C89; in rtw8922a_ctrl_tx_path_tmac()
1646 path_com_cr[3].data = 0x4E032240; in rtw8922a_ctrl_tx_path_tmac()
1647 path_com_cr[4].data = 0x80C8900E; in rtw8922a_ctrl_tx_path_tmac()
1648 path_com_cr[6].data = 0x201C0400; in rtw8922a_ctrl_tx_path_tmac()
1650 path_com_cr[0].data = 0x21C86900; in rtw8922a_ctrl_tx_path_tmac()
1651 path_com_cr[1].data = 0x00E4E433; in rtw8922a_ctrl_tx_path_tmac()
1652 path_com_cr[2].data = 0x39390CC9; in rtw8922a_ctrl_tx_path_tmac()
1653 path_com_cr[3].data = 0x4E433240; in rtw8922a_ctrl_tx_path_tmac()
1654 path_com_cr[4].data = 0x90CC900E; in rtw8922a_ctrl_tx_path_tmac()
1655 path_com_cr[6].data = 0x201C8600; in rtw8922a_ctrl_tx_path_tmac()
1660 for (i = 0; i < ARRAY_SIZE(path_com_cr); i++) { in rtw8922a_ctrl_tx_path_tmac()
1676 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_HTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1677 rtw89_phy_write32_idx(rtwdev, R_BRK_R, B_VHTMCS_LMT, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1680 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1681 rtw89_phy_write32_idx(rtwdev, R_BRK_HE, B_TB_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1682 rtw89_phy_write32_idx(rtwdev, R_BRK_EHT, B_RXEHT_NSS_MAX, 0, phy_idx); in rtw8922a_cfg_rx_nss_limit()
1683 rtw89_phy_write32_idx(rtwdev, R_BRK_RXEHT, B_RXEHTTB_NSS_MAX, 0, in rtw8922a_cfg_rx_nss_limit()
1703 return 0; in rtw8922a_cfg_rx_nss_limit()
1712 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1713 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1715 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1716 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1719 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x0); in rtw8922a_tssi_reset()
1720 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTA, B_TXPWR_RSTA, 0x1); in rtw8922a_tssi_reset()
1721 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x0); in rtw8922a_tssi_reset()
1722 rtw89_phy_write32_mask(rtwdev, R_TXPWR_RSTB, B_TXPWR_RSTB, 0x1); in rtw8922a_tssi_reset()
1732 /* Set to 0 first to avoid abnormal EDCCA report */ in rtw8922a_ctrl_rx_path_tmac()
1733 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x0, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1736 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x1, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1741 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x2, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1746 rtw89_phy_write32_idx(rtwdev, R_ANT_CHBW, B_ANT_RX_SG0, 0x3, phy_idx); in rtw8922a_ctrl_rx_path_tmac()
1754 return 0; in rtw8922a_ctrl_rx_path_tmac()
1759 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1760 0x0BB80708, 0x17701194, 0x02020100, 0x03030303, 0x01000303,
1761 0x05030302, 0x06060605, 0x06050300, 0x0A090807, 0x02000B0B,
1762 0x09080604, 0x0D0D0C0B, 0x08060400, 0x110F0C0B, 0x05001111,
1763 0x0D0C0907, 0x12121210},
1764 {0x012C0096, 0x044C02BC, 0x00322710, 0x015E0096, 0x03C8028A,
1765 0x0BB80708, 0x17701194, 0x04030201, 0x05050505, 0x01000505,
1766 0x07060504, 0x09090908, 0x09070400, 0x0E0D0C0B, 0x03000E0E,
1767 0x0D0B0907, 0x1010100F, 0x0B080500, 0x1512100D, 0x05001515,
1768 0x100D0B08, 0x15151512},
1781 digital_pwr_comp = rtw8922a_digital_pwr_comp_val[0]; in rtw8922a_set_digital_pwr_comp()
1786 for (i = 0; i < DIGITAL_PWR_COMP_REG_NUM; i++, addr += 4) { in rtw8922a_set_digital_pwr_comp()
1787 val = enable ? digital_pwr_comp[i] : 0; in rtw8922a_set_digital_pwr_comp()
1816 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x1); in rtw8922a_ctrl_mlo()
1817 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x0); in rtw8922a_ctrl_mlo()
1820 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_ctrl_mlo()
1821 rtw89_phy_write32_mask(rtwdev, R_DBCC_FA, B_DBCC_FA, 0x1); in rtw8922a_ctrl_mlo()
1827 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); in rtw8922a_ctrl_mlo()
1833 chan0 = rtw89_mgnt_chan_get(rtwdev, 0); in rtw8922a_ctrl_mlo()
1840 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_ctrl_mlo()
1843 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1844 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_ctrl_mlo()
1845 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_ctrl_mlo()
1846 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_ctrl_mlo()
1848 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_ctrl_mlo()
1849 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_ctrl_mlo()
1850 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_ctrl_mlo()
1851 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_ctrl_mlo()
1853 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x7BAB); in rtw8922a_ctrl_mlo()
1854 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3BAB); in rtw8922a_ctrl_mlo()
1855 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x3AAB); in rtw8922a_ctrl_mlo()
1857 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x180); in rtw8922a_ctrl_mlo()
1858 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x0); in rtw8922a_ctrl_mlo()
1861 return 0; in rtw8922a_ctrl_mlo()
1871 rtw89_write32_mask(rtwdev, R_BE_PWR_BOOST, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1874 rtw89_write32_mask(rtwdev, reg, B_BE_PWR_CTRL_SEL, 0); in rtw8922a_bb_sethw()
1884 rtw89_phy_write32_idx(rtwdev, R_RXCCA_BE1, B_RXCCA_BE1_DIS, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1887 0, phy_idx); in rtw8922a_ctrl_cck_en()
1890 rtw89_phy_write32_idx(rtwdev, R_UPD_CLK_ADC, B_ENABLE_CCK, 0, phy_idx); in rtw8922a_ctrl_cck_en()
1923 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1924 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0x6180); in rtw8922a_pre_set_channel_bb()
1925 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1926 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xABA9); in rtw8922a_pre_set_channel_bb()
1927 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEBA9); in rtw8922a_pre_set_channel_bb()
1928 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEAA9); in rtw8922a_pre_set_channel_bb()
1930 rtw89_phy_write32_mask(rtwdev, R_DBCC, B_DBCC_EN, 0x0); in rtw8922a_pre_set_channel_bb()
1931 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xBBAB); in rtw8922a_pre_set_channel_bb()
1932 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xAFFF); in rtw8922a_pre_set_channel_bb()
1933 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEFFF); in rtw8922a_pre_set_channel_bb()
1934 rtw89_phy_write32_mask(rtwdev, R_EMLSR, B_EMLSR_PARM, 0xEEFF); in rtw8922a_pre_set_channel_bb()
1963 u32 path_ofst = (path == RF_PATH_B) ? 0x100 : 0x0; in rtw8922a_dfs_en_idx()
1966 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 1, in rtw8922a_dfs_en_idx()
1969 rtw89_phy_write32_idx(rtwdev, 0x2800 + path_ofst, BIT(1), 0, in rtw8922a_dfs_en_idx()
1989 val &= ~0x1; in rtw8922a_adc_en_path()
1991 val &= ~0x2; in rtw8922a_adc_en_path()
1994 val |= 0x1; in rtw8922a_adc_en_path()
1996 val |= 0x2; in rtw8922a_adc_en_path()
2063 memset(rfk_mcc, 0, sizeof(*rfk_mcc)); in rtw8922a_rfk_init()
2091 for (path = 0; path < RF_PATH_NUM_8922A; path++) { in _wait_rx_mode()
2096 2, 5000, false, rtwdev, path, 0x00, in _wait_rx_mode()
2148 s16 ref_ofdm = 0; in rtw8922a_set_txpwr_ref()
2149 s16 ref_cck = 0; in rtw8922a_set_txpwr_ref()
2176 static const u32 path_ofst[] = {0x0, 0x100}; in rtw8922a_set_txpwr_diff()
2178 static const s16 tssi_k_base = 0x12; in rtw8922a_set_txpwr_diff()
2183 s16 pwr_ref = 0; in rtw8922a_set_txpwr_diff()
2192 ofst_dec[RF_PATH_A] = pwr_ofst > 0 ? pwr_ref : pwr_ref_ofst; in rtw8922a_set_txpwr_diff()
2193 ofst_dec[RF_PATH_B] = pwr_ofst > 0 ? pwr_ref_ofst : pwr_ref; in rtw8922a_set_txpwr_diff()
2194 tssi_k[RF_PATH_A] = pwr_ofst > 0 ? tssi_k_base : tssi_k_ofst; in rtw8922a_set_txpwr_diff()
2195 tssi_k[RF_PATH_B] = pwr_ofst > 0 ? tssi_k_ofst : tssi_k_base; in rtw8922a_set_txpwr_diff()
2197 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_set_txpwr_diff()
2200 rtw89_phy_write32_mask(rtwdev, txpwr_ref[0].addr + path_ofst[i], in rtw8922a_set_txpwr_diff()
2201 txpwr_ref[0].mask, ofst_dec[i]); in rtw8922a_set_txpwr_diff()
2212 u8 ctrl = en ? 0x1 : 0x0; in rtw8922a_bb_tx_triangular()
2230 if (tx_shape_idx == 0) in rtw8922a_set_tx_shape()
2272 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2274 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2276 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2277 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2278 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2279 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2280 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2281 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2282 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x3, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2284 0xf, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2286 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2287 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2288 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x80, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2289 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x8080, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2290 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2291 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x34, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2293 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_A, B_FORCE_FIR_A, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2295 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2297 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2298 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_A, B_BT_TRK_OFF_A, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2299 rtw89_phy_write32_idx(rtwdev, R_OP1DB_A, B_OP1DB_A, 0x1a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2300 rtw89_phy_write32_idx(rtwdev, R_OP1DB1_A, B_TIA10_A, 0x2a2a, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2301 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_A, B_LNA_IBADC_A, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2302 rtw89_phy_write32_idx(rtwdev, R_BKOFF_A, B_BKOFF_IBADC_A, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2303 rtw89_phy_write32_idx(rtwdev, R_FORCE_FIR_B, B_FORCE_FIR_B, 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2305 0x0, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2307 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2308 rtw89_phy_write32_idx(rtwdev, R_BT_SHARE_B, B_BT_TRK_OFF_B, 0x1, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2309 rtw89_phy_write32_idx(rtwdev, R_LNA_OP, B_LNA6, 0x20, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2310 rtw89_phy_write32_idx(rtwdev, R_LNA_TIA, B_TIA10_B, 0x2a30, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2311 rtw89_phy_write32_idx(rtwdev, R_BACKOFF_B, B_LNA_IBADC_B, 0x7a6, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2312 rtw89_phy_write32_idx(rtwdev, R_BKOFF_B, B_BKOFF_IBADC_B, 0x26, phy_idx); in rtw8922a_ctrl_nbtg_bt_tx()
2353 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2354 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x0); in rtw8922a_get_thermal()
2355 rtw89_write_rf(rtwdev, rf_path, RR_TM, RR_TM_TRI, 0x1); in rtw8922a_get_thermal()
2362 return clamp_t(int, th, 0, U8_MAX); in rtw8922a_get_thermal()
2372 module->bt_solo = 0; in rtw8922a_btc_set_rfe()
2374 module->wa_type = 0; in rtw8922a_btc_set_rfe()
2379 module->ant.diversity = 0; in rtw8922a_btc_set_rfe()
2388 if (module->rfe_type == 0) { in rtw8922a_btc_set_rfe()
2395 if (module->kt_ver == 0) in rtw8922a_btc_set_rfe()
2438 /* if GNT_WL=0 && BT=SS_group --> WL Tx/Rx = THRU */ in rtw8922a_btc_init_cfg()
2439 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_SS_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2441 /* if GNT_WL=0 && BT=Rx_group --> WL-Rx = THRU + WL-Tx = MASK */ in rtw8922a_btc_init_cfg()
2442 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_RX_GROUP, 0x5df); in rtw8922a_btc_init_cfg()
2444 /* if GNT_WL = 0 && BT = Tx_group --> in rtw8922a_btc_init_cfg()
2445 * Shared-Ant && BTG-path:WL mask(0x55f), others:WL THRU(0x5ff) in rtw8922a_btc_init_cfg()
2448 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x55f); in rtw8922a_btc_init_cfg()
2450 rtw8922a_set_trx_mask(rtwdev, path, BTC_BT_TX_GROUP, 0x5ff); in rtw8922a_btc_init_cfg()
2452 rtw89_write_rf(rtwdev, path, RR_LUTWE, RFREG_MASK, 0); in rtw8922a_btc_init_cfg()
2464 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_0, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2466 rtw89_write32(rtwdev, R_BTC_ZB_COEX_TBL_1, 0xda5a5a5a); in rtw8922a_btc_init_cfg()
2468 rtw89_write32(rtwdev, R_BTC_ZB_BREAK_TBL, 0xf0ffffff); in rtw8922a_btc_init_cfg()
2475 u16 ctrl_all_time = u32_get_bits(txpwr_val, GENMASK(15, 0)); in rtw8922a_btc_set_wl_txpwr_ctrl()
2479 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2481 B_BE_FORCE_PWR_BY_RATE_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2483 B_BE_FORCE_PWR_BY_RATE_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2489 B_BE_FORCE_PWR_BY_RATE_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2494 case 0xffff: in rtw8922a_btc_set_wl_txpwr_ctrl()
2496 B_BE_PWR_BT_EN, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2498 B_BE_PWR_BT_VAL, 0x0); in rtw8922a_btc_set_wl_txpwr_ctrl()
2504 B_BE_PWR_BT_EN, 0x1); in rtw8922a_btc_set_wl_txpwr_ctrl()
2512 return clamp_t(s8, val, -100, 0) + 100; in rtw8922a_btc_get_bt_rssi()
2516 {255, 0, 0, 7}, /* 0 -> original */
2517 {255, 2, 0, 7}, /* 1 -> for BT-connected ACI issue && BTG co-rx */
2518 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2519 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2520 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2521 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2522 {6, 1, 0, 7},
2523 {13, 1, 0, 7},
2524 {13, 1, 0, 7}
2528 {255, 0, 0, 7}, /* 0 -> original */
2529 {255, 2, 0, 7}, /* 1 -> reserved for shared-antenna */
2530 {255, 0, 0, 7}, /* 2 ->reserved for shared-antenna */
2531 {255, 0, 0, 7}, /* 3- >reserved for shared-antenna */
2532 {255, 0, 0, 7}, /* 4 ->reserved for shared-antenna */
2533 {255, 1, 0, 7}, /* the below id is for non-shared-antenna free-run */
2534 {255, 1, 0, 7},
2535 {255, 1, 0, 7},
2536 {255, 1, 0, 7}
2543 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe300),
2544 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe320),
2545 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe324),
2546 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe328),
2547 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe32c),
2548 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe330),
2549 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe334),
2550 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe338),
2551 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe344),
2552 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe348),
2553 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe34c),
2554 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0xe350),
2555 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a2c),
2556 RTW89_DEF_FBTC_MREG(REG_MAC, 4, 0x11a50),
2557 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x980),
2558 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x660),
2559 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x1660),
2560 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x418c),
2561 RTW89_DEF_FBTC_MREG(REG_BB, 4, 0x518c),
2574 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2575 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2576 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2577 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2578 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2580 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2581 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2582 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2583 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x01018); in rtw8922a_btc_wl_s1_standby()
2584 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2586 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2587 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2588 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2589 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2590 rtw89_write_rf(rtwdev, RF_PATH_B, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2592 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x80000); in rtw8922a_btc_wl_s1_standby()
2593 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWA, RFREG_MASK, 0x1); in rtw8922a_btc_wl_s1_standby()
2594 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD1, RFREG_MASK, 0x0c110); in rtw8922a_btc_wl_s1_standby()
2595 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWD0, RFREG_MASK, 0x09018); in rtw8922a_btc_wl_s1_standby()
2596 rtw89_write_rf(rtwdev, RF_PATH_A, RR_LUTWE, RFREG_MASK, 0x00000); in rtw8922a_btc_wl_s1_standby()
2612 if (chan_idx == 0) in rtw8922a_fill_freq_with_ppdu()
2631 for (path = 0; path < rtwdev->chip->rf_path_num; path++) { in rtw8922a_query_ppdu()
2643 static const u8 bw_compensate[] = {0, 0, 0, 6, 12, 18, 0}; in rtw8922a_convert_rpl_to_rssi()
2645 u8 compensate = 0; in rtw8922a_convert_rpl_to_rssi()
2652 for (i = 0; i < RF_PATH_NUM_8922A; i++) { in rtw8922a_convert_rpl_to_rssi()
2654 rssi[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2655 phy_ppdu->rpl_path[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2656 phy_ppdu->rpl_fd[i] = 0; in rtw8922a_convert_rpl_to_rssi()
2675 if (desc_info->rssi <= 0x1 || (desc_info->rssi >> 2) > MAX_RSSI) in rtw8922a_phy_rpt_to_rssi()
2685 rtw89_write32(rtwdev, R_BE_DMAC_SYS_CR32B, 0x7FF97FF9); in rtw8922a_mac_enable_bb_rf()
2687 return 0; in rtw8922a_mac_enable_bb_rf()
2695 return 0; in rtw8922a_mac_disable_bb_rf()
2787 .dle_scc_rsvd_size = 0,
2790 .rsvd_ple_ofst = 0x8f800,
2795 .rf_base_addr = {0xe000, 0xf000},
2796 .thermal_th = {0xad, 0xb4},
2843 .physical_efuse_size = 0x1300,
2844 .logical_efuse_size = 0x70000,
2845 .limit_efuse_size = 0x40000,
2846 .dav_phy_efuse_size = 0,
2847 .dav_log_efuse_size = 0,
2849 .phycap_addr = 0x1700,
2850 .phycap_size = 0x38,
2851 .para_ver = 0xf,
2852 .wlcx_desired = 0x07110000,
2853 .btcx_desired = 0x7,
2854 .scbd = 0x1,
2855 .mailbox = 0x1,
2870 .low_power_hci_modes = 0,
2887 .dcfo_comp_sft = 0,
2896 .dma_ch_mask = 0,
2907 .fw_min_ver_code = RTW89_FW_VER_CODE(0, 35, 54, 0),