Lines Matching +full:0 +full:x51
55 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8822b_read_efuse()
56 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8822b_read_efuse()
58 efuse->country_code[0] = map->country_code[0]; in rtw8822b_read_efuse()
61 efuse->regd = map->rf_board_option & 0x7; in rtw8822b_read_efuse()
65 for (i = 0; i < 4; i++) in rtw8822b_read_efuse()
83 return 0; in rtw8822b_read_efuse()
89 rtw_write32_mask(rtwdev, 0x64, BIT(29) | BIT(28), 0x3); in rtw8822b_phy_rfe_init()
90 rtw_write32_mask(rtwdev, 0x4c, BIT(26) | BIT(25), 0x0); in rtw8822b_phy_rfe_init()
91 rtw_write32_mask(rtwdev, 0x40, BIT(2), 0x1); in rtw8822b_phy_rfe_init()
94 rtw_write32_mask(rtwdev, 0x1990, 0x3f, 0x30); in rtw8822b_phy_rfe_init()
95 rtw_write32_mask(rtwdev, 0x1990, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
98 rtw_write32_mask(rtwdev, 0x974, 0x3f, 0x3f); in rtw8822b_phy_rfe_init()
99 rtw_write32_mask(rtwdev, 0x974, (BIT(11) | BIT(10)), 0x3); in rtw8822b_phy_rfe_init()
104 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
105 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
106 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
107 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
112 u8 i = 0; in rtw8822b_get_swing_index()
115 swing = rtw_read32_mask(rtwdev, 0xc1c, 0xffe00000); in rtw8822b_get_swing_index()
116 for (i = 0; i < RTW_TXSCALE_SIZE; i++) { in rtw8822b_get_swing_index()
138 dm_info->delta_power_index[path] = 0; in rtw8822b_pwrtrack_init()
149 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8822b_phy_bf_init()
170 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8822b_phy_set_param()
171 rtw_write32_mask(rtwdev, 0x24, 0x7e000000, crystal_cap); in rtw8822b_phy_set_param()
172 rtw_write32_mask(rtwdev, 0x28, 0x7e, crystal_cap); in rtw8822b_phy_set_param()
188 #define WLAN_SLOT_TIME 0x09
189 #define WLAN_PIFS_TIME 0x19
190 #define WLAN_SIFS_CCK_CONT_TX 0xA
191 #define WLAN_SIFS_OFDM_CONT_TX 0xE
192 #define WLAN_SIFS_CCK_TRX 0x10
193 #define WLAN_SIFS_OFDM_TRX 0x10
194 #define WLAN_VO_TXOP_LIMIT 0x186 /* unit : 32us */
195 #define WLAN_VI_TXOP_LIMIT 0x3BC /* unit : 32us */
196 #define WLAN_RDG_NAV 0x05
197 #define WLAN_TXOP_NAV 0x1B
198 #define WLAN_CCK_RX_TSF 0x30
199 #define WLAN_OFDM_RX_TSF 0x30
200 #define WLAN_TBTT_PROHIBIT 0x04 /* unit : 32us */
201 #define WLAN_TBTT_HOLD_TIME 0x064 /* unit : 32us */
202 #define WLAN_DRV_EARLY_INT 0x04
203 #define WLAN_BCN_DMA_TIME 0x02
205 #define WLAN_RX_FILTER0 0x0FFFFFFF
206 #define WLAN_RX_FILTER2 0xFFFF
207 #define WLAN_RCR_CFG 0xE400220E
211 #define WLAN_AMPDU_MAX_TIME 0x70
212 #define WLAN_RTS_LEN_TH 0xFF
213 #define WLAN_RTS_TX_TIME_TH 0x08
214 #define WLAN_MAX_AGG_PKT_LIMIT 0x20
215 #define WLAN_RTS_MAX_AGG_PKT_LIMIT 0x20
216 #define FAST_EDCA_VO_TH 0x06
217 #define FAST_EDCA_VI_TH 0x06
218 #define FAST_EDCA_BE_TH 0x06
219 #define FAST_EDCA_BK_TH 0x06
220 #define WLAN_BAR_RETRY_LIMIT 0x01
221 #define WLAN_RA_TRY_RATE_AGG_LIMIT 0x08
223 #define WLAN_TX_FUNC_CFG1 0x30
224 #define WLAN_TX_FUNC_CFG2 0x30
225 #define WLAN_MAC_OPT_NORM_FUNC1 0x98
226 #define WLAN_MAC_OPT_LB_FUNC1 0x80
227 #define WLAN_MAC_OPT_FUNC2 0xb0810041
260 rtw_write16(rtwdev, REG_TXPAUSE, 0x0000); in rtw8822b_mac_init()
287 return 0; in rtw8822b_mac_init()
295 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x705770); in rtw8822b_set_channel_rfe_efem()
296 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_efem()
297 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(4), 0); in rtw8822b_set_channel_rfe_efem()
299 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x177517); in rtw8822b_set_channel_rfe_efem()
300 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_efem()
301 rtw_write32s_mask(rtwdev, REG_RFECTL, BIT(5), 0); in rtw8822b_set_channel_rfe_efem()
304 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_efem()
309 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_efem()
312 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_efem()
315 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_efem()
325 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x745774); in rtw8822b_set_channel_rfe_ifem()
326 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x57); in rtw8822b_set_channel_rfe_ifem()
329 rtw_write32s_mask(rtwdev, REG_RFESEL0, 0xffffff, 0x477547); in rtw8822b_set_channel_rfe_ifem()
330 rtw_write32s_mask(rtwdev, REG_RFESEL8, MASKBYTE1, 0x75); in rtw8822b_set_channel_rfe_ifem()
333 rtw_write32s_mask(rtwdev, REG_RFEINV, BIT(11) | BIT(10) | 0x3f, 0x0); in rtw8822b_set_channel_rfe_ifem()
339 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa501); in rtw8822b_set_channel_rfe_ifem()
342 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa500); in rtw8822b_set_channel_rfe_ifem()
345 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa005); in rtw8822b_set_channel_rfe_ifem()
348 rtw_write32s_mask(rtwdev, REG_TRSW, MASKLWORD, 0xa5a5); in rtw8822b_set_channel_rfe_ifem()
367 {0x75C97010, 0x75C97010, 0x75C97010, 0x75C97010}, /*Reg82C*/
368 {0x79a0eaaa, 0x79A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
369 {0x87765541, 0x87746341, 0x87765541, 0x87746341}, /*Reg838*/
373 {0x75B86010, 0x75B76010, 0x75B86010, 0x75B76010}, /*Reg82C*/
374 {0x79A0EAA8, 0x79A0EAAC, 0x79A0EAA8, 0x79a0eaaa}, /*Reg830*/
375 {0x87766451, 0x87766431, 0x87766451, 0x87766431}, /*Reg838*/
379 {0x75da8010, 0x75da8010, 0x75da8010, 0x75da8010}, /*Reg82C*/
380 {0x79a0eaaa, 0x97A0EAAC, 0x79a0eaaa, 0x79a0eaaa}, /*Reg830*/
381 {0x87765541, 0x86666341, 0x87765561, 0x86666361}, /*Reg838*/
476 reg830 = 0x79a0ea28; in rtw8822b_set_channel_cca()
484 rtw_write32_mask(rtwdev, REG_L1WT, MASKDWORD, 0x9194b2b9); in rtw8822b_set_channel_cca()
487 rtw_write32_mask(rtwdev, REG_CCA2ND, 0xf0, 0x4); in rtw8822b_set_channel_cca()
490 static const u8 low_band[15] = {0x7, 0x6, 0x6, 0x5, 0x0, 0x0, 0x7, 0xff, 0x6,
491 0x5, 0x0, 0x0, 0x7, 0x6, 0x6};
492 static const u8 middle_band[23] = {0x6, 0x5, 0x0, 0x0, 0x7, 0x6, 0x6, 0xff, 0x0,
493 0x0, 0x7, 0x6, 0x6, 0x5, 0x0, 0xff, 0x7, 0x6,
494 0x6, 0x5, 0x0, 0x0, 0x7};
495 static const u8 high_band[15] = {0x5, 0x5, 0x0, 0x7, 0x7, 0x6, 0x5, 0xff, 0x0,
496 0x7, 0x7, 0x6, 0x5, 0x5, 0x0};
501 #define RF18_BAND_2G (0) in rtw8822b_set_channel_rf()
516 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8822b_set_channel_rf()
544 rf_reg_be = 0x0; in rtw8822b_set_channel_rf()
556 /* need to set 0xdf[18]=1 before writing RF18 when channel 144 */ in rtw8822b_set_channel_rf()
558 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x1); in rtw8822b_set_channel_rf()
560 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(18), 0x0); in rtw8822b_set_channel_rf()
562 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
564 rtw_write_rf(rtwdev, RF_PATH_B, 0x18, RFREG_MASK, rf_reg18); in rtw8822b_set_channel_rf()
566 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8822b_set_channel_rf()
580 igi = rtw_read32_mask(rtwdev, REG_RXIGI_A, 0x7f); in rtw8822b_toggle_igi()
581 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi - 2); in rtw8822b_toggle_igi()
582 rtw_write32_mask(rtwdev, REG_RXIGI_A, 0x7f, igi); in rtw8822b_toggle_igi()
583 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi - 2); in rtw8822b_toggle_igi()
584 rtw_write32_mask(rtwdev, REG_RXIGI_B, 0x7f, igi); in rtw8822b_toggle_igi()
586 rtw_write32_mask(rtwdev, REG_RXPSEL, MASKBYTE0, 0x0); in rtw8822b_toggle_igi()
595 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
596 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x0); in rtw8822b_set_channel_rxdfir()
597 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
600 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
601 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8822b_set_channel_rxdfir()
602 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8822b_set_channel_rxdfir()
605 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
606 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8822b_set_channel_rxdfir()
607 rtw_write32s_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8822b_set_channel_rxdfir()
619 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8822b_set_channel_bb()
620 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8822b_set_channel_bb()
621 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8822b_set_channel_bb()
622 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8822b_set_channel_bb()
624 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x0); in rtw8822b_set_channel_bb()
625 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8822b_set_channel_bb()
627 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x00006577); in rtw8822b_set_channel_bb()
628 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8822b_set_channel_bb()
630 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x384f6577); in rtw8822b_set_channel_bb()
631 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x1525); in rtw8822b_set_channel_bb()
634 rtw_write32_mask(rtwdev, REG_RFEINV, 0x300, 0x2); in rtw8822b_set_channel_bb()
636 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8822b_set_channel_bb()
637 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8822b_set_channel_bb()
638 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8822b_set_channel_bb()
639 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 34); in rtw8822b_set_channel_bb()
642 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x1); in rtw8822b_set_channel_bb()
644 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x2); in rtw8822b_set_channel_bb()
646 rtw_write32_mask(rtwdev, REG_ACGG2TBL, 0x1f, 0x3); in rtw8822b_set_channel_bb()
649 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8822b_set_channel_bb()
651 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8822b_set_channel_bb()
653 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8822b_set_channel_bb()
655 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8822b_set_channel_bb()
657 rtw_write32_mask(rtwdev, 0xcbc, 0x300, 0x1); in rtw8822b_set_channel_bb()
664 val32 &= 0xFFCFFC00; in rtw8822b_set_channel_bb()
668 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
677 val32 &= 0xFF3FF300; in rtw8822b_set_channel_bb()
678 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_40); in rtw8822b_set_channel_bb()
681 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
685 val32 &= 0xFCEFCF00; in rtw8822b_set_channel_bb()
686 val32 |= (((primary_ch_idx & 0xf) << 2) | RTW_CHANNEL_WIDTH_80); in rtw8822b_set_channel_bb()
689 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8822b_set_channel_bb()
692 rtw_write32_mask(rtwdev, REG_L1PKWT, 0x0000f000, 0x6); in rtw8822b_set_channel_bb()
693 rtw_write32_mask(rtwdev, REG_ADC40, BIT(10), 0x1); in rtw8822b_set_channel_bb()
698 val32 &= 0xEFEEFE00; in rtw8822b_set_channel_bb()
702 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
703 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
707 val32 &= 0xEFFEFF00; in rtw8822b_set_channel_bb()
711 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8822b_set_channel_bb()
712 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8822b_set_channel_bb()
754 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
756 rtw_write32_mask(rtwdev, REG_AGCTR_A, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
759 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x3231); in rtw8822b_config_trx_mode()
761 rtw_write32_mask(rtwdev, REG_AGCTR_B, MASKLWORD, 0x1111); in rtw8822b_config_trx_mode()
763 rtw_write32_mask(rtwdev, REG_CDDTXP, (BIT(19) | BIT(18)), 0x3); in rtw8822b_config_trx_mode()
764 rtw_write32_mask(rtwdev, REG_TXPSEL, (BIT(29) | BIT(28)), 0x1); in rtw8822b_config_trx_mode()
765 rtw_write32_mask(rtwdev, REG_TXPSEL, BIT(30), 0x1); in rtw8822b_config_trx_mode()
768 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x001); in rtw8822b_config_trx_mode()
769 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x8); in rtw8822b_config_trx_mode()
771 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x002); in rtw8822b_config_trx_mode()
772 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0x4); in rtw8822b_config_trx_mode()
776 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x01); in rtw8822b_config_trx_mode()
778 rtw_write32_mask(rtwdev, REG_TXPSEL1, 0xfff0, 0x43); in rtw8822b_config_trx_mode()
785 rtw_write32_mask(rtwdev, REG_CDDTXP, 0xfff00000, 0x043); in rtw8822b_config_trx_mode()
786 rtw_write32_mask(rtwdev, REG_ADCINI, 0xf0000000, 0xc); in rtw8822b_config_trx_mode()
790 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(22), 0x0); in rtw8822b_config_trx_mode()
791 rtw_write32_mask(rtwdev, REG_RXDESC, BIT(18), 0x0); in rtw8822b_config_trx_mode()
794 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x0); in rtw8822b_config_trx_mode()
796 rtw_write32_mask(rtwdev, REG_ADCINI, 0x0f000000, 0x5); in rtw8822b_config_trx_mode()
802 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x0); in rtw8822b_config_trx_mode()
803 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x0); in rtw8822b_config_trx_mode()
804 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x0); in rtw8822b_config_trx_mode()
806 rtw_write32_mask(rtwdev, REG_ANTWT, BIT(16), 0x1); in rtw8822b_config_trx_mode()
807 rtw_write32_mask(rtwdev, REG_HTSTFWT, BIT(28), 0x1); in rtw8822b_config_trx_mode()
808 rtw_write32_mask(rtwdev, REG_MRC, BIT(23), 0x1); in rtw8822b_config_trx_mode()
811 for (counter = 100; counter > 0; counter--) { in rtw8822b_config_trx_mode()
814 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
815 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
818 rf_reg33 = rtw_read_rf(rtwdev, RF_PATH_A, 0x33, RFREG_MASK); in rtw8822b_config_trx_mode()
820 if (rf_reg33 == 0x00001) in rtw8822b_config_trx_mode()
824 if (WARN(counter <= 0, "write RF mode table fail\n")) in rtw8822b_config_trx_mode()
827 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x80000); in rtw8822b_config_trx_mode()
828 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x00001); in rtw8822b_config_trx_mode()
829 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD1, RFREG_MASK, 0x00034); in rtw8822b_config_trx_mode()
830 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x4080c); in rtw8822b_config_trx_mode()
831 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
832 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE, RFREG_MASK, 0x00000); in rtw8822b_config_trx_mode()
862 u8 evm_dbm = 0; in query_phy_status_page1()
899 for (path = 0; path <= rtwdev->hal.rf_path_num; path++) { in query_phy_status_page1()
907 if (rx_evm < 0) { in query_phy_status_page1()
909 evm_dbm = 0; in query_phy_status_page1()
922 page = *phy_status & 0xf; in query_phy_status()
925 case 0: in query_phy_status()
942 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8822b_set_tx_power_index_by_rate()
946 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8822b_set_tx_power_index_by_rate()
949 shift = rate & 0x3; in rtw8822b_set_tx_power_index_by_rate()
951 if (shift == 0x3) { in rtw8822b_set_tx_power_index_by_rate()
952 rate_idx = rate & 0xfc; in rtw8822b_set_tx_power_index_by_rate()
955 *phy_pwr_idx = 0; in rtw8822b_set_tx_power_index_by_rate()
963 u32 phy_pwr_idx = 0; in rtw8822b_set_tx_power_index()
966 for (path = 0; path < hal->rf_path_num; path++) { in rtw8822b_set_tx_power_index()
967 for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++) in rtw8822b_set_tx_power_index()
991 rtw_dbg(rtwdev, RTW_DBG_PHY, "config RF path, tx=0x%x rx=0x%x\n", in rtw8822b_set_antenna()
995 rtw_warn(rtwdev, "unsupported tx path 0x%x\n", antenna_tx); in rtw8822b_set_antenna()
1000 rtw_warn(rtwdev, "unsupported rx path 0x%x\n", antenna_rx); in rtw8822b_set_antenna()
1009 return 0; in rtw8822b_set_antenna()
1030 cck_enable = rtw_read32(rtwdev, 0x808) & BIT(28); in rtw8822b_false_alarm_statistics()
1031 cck_fa_cnt = rtw_read16(rtwdev, 0xa5c); in rtw8822b_false_alarm_statistics()
1032 ofdm_fa_cnt = rtw_read16(rtwdev, 0xf48); in rtw8822b_false_alarm_statistics()
1037 dm_info->total_fa_cnt += cck_enable ? cck_fa_cnt : 0; in rtw8822b_false_alarm_statistics()
1039 crc32_cnt = rtw_read32(rtwdev, 0xf04); in rtw8822b_false_alarm_statistics()
1040 dm_info->cck_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1041 dm_info->cck_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1042 crc32_cnt = rtw_read32(rtwdev, 0xf14); in rtw8822b_false_alarm_statistics()
1043 dm_info->ofdm_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1044 dm_info->ofdm_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1045 crc32_cnt = rtw_read32(rtwdev, 0xf10); in rtw8822b_false_alarm_statistics()
1046 dm_info->ht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1047 dm_info->ht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1048 crc32_cnt = rtw_read32(rtwdev, 0xf0c); in rtw8822b_false_alarm_statistics()
1049 dm_info->vht_ok_cnt = crc32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1050 dm_info->vht_err_cnt = (crc32_cnt & 0xffff0000) >> 16; in rtw8822b_false_alarm_statistics()
1052 cca32_cnt = rtw_read32(rtwdev, 0xf08); in rtw8822b_false_alarm_statistics()
1053 dm_info->ofdm_cca_cnt = ((cca32_cnt & 0xffff0000) >> 16); in rtw8822b_false_alarm_statistics()
1056 cca32_cnt = rtw_read32(rtwdev, 0xfcc); in rtw8822b_false_alarm_statistics()
1057 dm_info->cck_cca_cnt = cca32_cnt & 0xffff; in rtw8822b_false_alarm_statistics()
1061 rtw_write32_set(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1062 rtw_write32_clr(rtwdev, 0x9a4, BIT(17)); in rtw8822b_false_alarm_statistics()
1063 rtw_write32_clr(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1064 rtw_write32_set(rtwdev, 0xa2c, BIT(15)); in rtw8822b_false_alarm_statistics()
1065 rtw_write32_set(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1066 rtw_write32_clr(rtwdev, 0xb58, BIT(0)); in rtw8822b_false_alarm_statistics()
1072 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8822b_do_iqk()
1079 for (counter = 0; counter < 300; counter++) { in rtw8822b_do_iqk()
1081 if (rf_reg == 0xabcde) in rtw8822b_do_iqk()
1085 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8822b_do_iqk()
1088 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8822b_do_iqk()
1090 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8822b_do_iqk()
1105 /* 0x790[5:0]=0x5 */ in rtw8822b_coex_cfg_init()
1106 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8822b_coex_cfg_init()
1109 rtw_write8(rtwdev, REG_BT_STAT_CTRL, 0x1); in rtw8822b_coex_cfg_init()
1130 u8 regval = 0; in rtw8822b_coex_cfg_ant_switch()
1146 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1147 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1148 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1149 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1151 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x77); in rtw8822b_coex_cfg_ant_switch()
1154 if (coex_rfe->rfe_module_type != 0x4 && in rtw8822b_coex_cfg_ant_switch()
1155 coex_rfe->rfe_module_type != 0x2) in rtw8822b_coex_cfg_ant_switch()
1156 regval = 0x3; in rtw8822b_coex_cfg_ant_switch()
1158 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1160 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1162 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8822b_coex_cfg_ant_switch()
1168 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1169 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1170 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1171 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1173 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x66); in rtw8822b_coex_cfg_ant_switch()
1175 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1179 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1180 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1181 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1182 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1183 rtw_write8_mask(rtwdev, REG_RFE_CTRL8, BIT_MASK_RFE_SEL89, 0x88); in rtw8822b_coex_cfg_ant_switch()
1186 /* 0x4c[23] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1187 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x1); in rtw8822b_coex_cfg_ant_switch()
1189 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8822b_coex_cfg_ant_switch()
1193 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1194 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1195 /* 0x4c[24] = 1 */ in rtw8822b_coex_cfg_ant_switch()
1196 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x1); in rtw8822b_coex_cfg_ant_switch()
1199 /* 0x4c[23] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1200 rtw_write8_mask(rtwdev, REG_LED_CFG + 2, BIT_DPDT_SEL_EN >> 16, 0x0); in rtw8822b_coex_cfg_ant_switch()
1201 /* 0x4c[24] = 0 */ in rtw8822b_coex_cfg_ant_switch()
1202 rtw_write8_mask(rtwdev, REG_LED_CFG + 3, BIT_DPDT_WL_SEL >> 24, 0x0); in rtw8822b_coex_cfg_ant_switch()
1213 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 2, BIT_BTGP_SPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1214 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 3, BIT_BTGP_JTAG_EN >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1215 rtw_write8_mask(rtwdev, REG_GPIO_MUXCFG + 2, BIT_FSPI_EN >> 16, 0); in rtw8822b_coex_cfg_gnt_debug()
1216 rtw_write8_mask(rtwdev, REG_PAD_CTRL1 + 1, BIT_LED1DIS >> 8, 0); in rtw8822b_coex_cfg_gnt_debug()
1217 rtw_write8_mask(rtwdev, REG_SYS_SDIO_CTRL + 3, BIT_DBG_GNT_WL_BT >> 24, 0); in rtw8822b_coex_cfg_gnt_debug()
1228 coex_rfe->ant_switch_polarity = 0; in rtw8822b_coex_cfg_rfe_type()
1230 if (coex_rfe->rfe_module_type == 0x12 || in rtw8822b_coex_cfg_rfe_type()
1231 coex_rfe->rfe_module_type == 0x15 || in rtw8822b_coex_cfg_rfe_type()
1232 coex_rfe->rfe_module_type == 0x16) in rtw8822b_coex_cfg_rfe_type()
1254 rtw_write8(rtwdev, REG_RFE_CTRL_E, 0xff); in rtw8822b_coex_cfg_rfe_type()
1255 rtw_write8_mask(rtwdev, REG_RFESEL_CTRL + 1, 0x3, 0x0); in rtw8822b_coex_cfg_rfe_type()
1256 rtw_write8_mask(rtwdev, REG_RFE_INV16, BIT_RFE_BUF_EN, 0x0); in rtw8822b_coex_cfg_rfe_type()
1259 rtw_coex_write_indirect_reg(rtwdev, LTE_COEX_CTRL, BIT_LTE_COEX_EN, 0); in rtw8822b_coex_cfg_rfe_type()
1262 rtw_coex_write_indirect_reg(rtwdev, LTE_WL_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1265 rtw_coex_write_indirect_reg(rtwdev, LTE_BT_TRX_CTRL, MASKLWORD, 0xffff); in rtw8822b_coex_cfg_rfe_type()
1272 static const u16 reg_addr[] = {0xc58, 0xe58}; in rtw8822b_coex_cfg_wl_tx_power()
1273 static const u8 wl_tx_power[] = {0xd8, 0xd4, 0xd0, 0xcc, 0xc8}; in rtw8822b_coex_cfg_wl_tx_power()
1286 for (i = 0; i < ARRAY_SIZE(reg_addr); i++) in rtw8822b_coex_cfg_wl_tx_power()
1287 rtw_write8_mask(rtwdev, reg_addr[i], 0xff, pwr); in rtw8822b_coex_cfg_wl_tx_power()
1296 0xff000003, 0xbd120003, 0xbe100003, 0xbf080003, 0xbf060003, in rtw8822b_coex_cfg_wl_rx_gain()
1297 0xbf050003, 0xbc140003, 0xbb160003, 0xba180003, 0xb91a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1298 0xb81c0003, 0xb71e0003, 0xb4200003, 0xb5220003, 0xb4240003, in rtw8822b_coex_cfg_wl_rx_gain()
1299 0xb3260003, 0xb2280003, 0xb12a0003, 0xb02c0003, 0xaf2e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1300 0xae300003, 0xad320003, 0xac340003, 0xab360003, 0x8d380003, in rtw8822b_coex_cfg_wl_rx_gain()
1301 0x8c3a0003, 0x8b3c0003, 0x8a3e0003, 0x6e400003, 0x6d420003, in rtw8822b_coex_cfg_wl_rx_gain()
1302 0x6c440003, 0x6b460003, 0x6a480003, 0x694a0003, 0x684c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1303 0x674e0003, 0x66500003, 0x65520003, 0x64540003, 0x64560003, in rtw8822b_coex_cfg_wl_rx_gain()
1304 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1309 0xff000003, 0xf4120003, 0xf5100003, 0xf60e0003, 0xf70c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1310 0xf80a0003, 0xf3140003, 0xf2160003, 0xf1180003, 0xf01a0003, in rtw8822b_coex_cfg_wl_rx_gain()
1311 0xef1c0003, 0xee1e0003, 0xed200003, 0xec220003, 0xeb240003, in rtw8822b_coex_cfg_wl_rx_gain()
1312 0xea260003, 0xe9280003, 0xe82a0003, 0xe72c0003, 0xe62e0003, in rtw8822b_coex_cfg_wl_rx_gain()
1313 0xe5300003, 0xc8320003, 0xc7340003, 0xc6360003, 0xc5380003, in rtw8822b_coex_cfg_wl_rx_gain()
1314 0xc43a0003, 0xc33c0003, 0xc23e0003, 0xc1400003, 0xc0420003, in rtw8822b_coex_cfg_wl_rx_gain()
1315 0xa5440003, 0xa4460003, 0xa3480003, 0xa24a0003, 0xa14c0003, in rtw8822b_coex_cfg_wl_rx_gain()
1316 0x834e0003, 0x82500003, 0x81520003, 0x80540003, 0x65560003, in rtw8822b_coex_cfg_wl_rx_gain()
1317 0x007e0403 in rtw8822b_coex_cfg_wl_rx_gain()
1328 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_on); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1332 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1333 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1334 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x1); in rtw8822b_coex_cfg_wl_rx_gain()
1335 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x3f); in rtw8822b_coex_cfg_wl_rx_gain()
1338 for (i = 0; i < ARRAY_SIZE(wl_rx_low_gain_off); i++) in rtw8822b_coex_cfg_wl_rx_gain()
1339 rtw_write32(rtwdev, 0x81c, wl_rx_low_gain_off[i]); in rtw8822b_coex_cfg_wl_rx_gain()
1342 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1343 rtw_write_rf(rtwdev, RF_PATH_A, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1344 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCK, 0x3f, 0x4); in rtw8822b_coex_cfg_wl_rx_gain()
1345 rtw_write_rf(rtwdev, RF_PATH_B, RF_RCKD, 0x2, 0x0); in rtw8822b_coex_cfg_wl_rx_gain()
1356 u8 swing_lower_bound = 0; in rtw8822b_txagc_swing_offset()
1357 u8 max_tx_pwr_idx_offset = 0xf; in rtw8822b_txagc_swing_offset()
1358 s8 agc_index = 0; in rtw8822b_txagc_swing_offset()
1363 if (delta_pwr_idx >= 0) { in rtw8822b_txagc_swing_offset()
1381 agc_index = 0; in rtw8822b_txagc_swing_offset()
1400 reg1 = 0xc94; in rtw8822b_pwrtrack_set_pwr()
1401 reg2 = 0xc1c; in rtw8822b_pwrtrack_set_pwr()
1403 reg1 = 0xe94; in rtw8822b_pwrtrack_set_pwr()
1404 reg2 = 0xe1c; in rtw8822b_pwrtrack_set_pwr()
1467 if (rtwdev->efuse.thermal_meter[RF_PATH_A] == 0xff) in rtw8822b_phy_pwrtrack()
1470 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8822b_phy_pwrtrack()
1480 for (path = 0; path < rtwdev->hal.rf_path_num; path++) in rtw8822b_phy_pwrtrack()
1493 if (efuse->power_track_type != 0) in rtw8822b_pwr_track()
1498 GENMASK(17, 16), 0x03); in rtw8822b_pwr_track()
1547 rtw_write32_mask(rtwdev, REG_EDCCA_POW_MA, BIT_MA_LEVEL, 0); in rtw8822b_adaptivity_init()
1559 igi = dm_info->igi_history[0]; in rtw8822b_adaptivity()
1599 {0x0086,
1603 RTW_PWR_CMD_WRITE, BIT(0), 0},
1604 {0x0086,
1609 {0x004A,
1613 RTW_PWR_CMD_WRITE, BIT(0), 0},
1614 {0x0005,
1618 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1619 {0x0300,
1623 RTW_PWR_CMD_WRITE, 0xFF, 0},
1624 {0x0301,
1628 RTW_PWR_CMD_WRITE, 0xFF, 0},
1629 {0xFFFF,
1632 0,
1633 RTW_PWR_CMD_END, 0, 0},
1637 {0x0012,
1641 RTW_PWR_CMD_WRITE, BIT(1), 0},
1642 {0x0012,
1646 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1647 {0x0020,
1651 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1652 {0x0001,
1657 {0x0000,
1661 RTW_PWR_CMD_WRITE, BIT(5), 0},
1662 {0x0005,
1666 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1667 {0x0075,
1671 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1672 {0x0006,
1677 {0x0075,
1681 RTW_PWR_CMD_WRITE, BIT(0), 0},
1682 {0xFF1A,
1686 RTW_PWR_CMD_WRITE, 0xFF, 0},
1687 {0x0006,
1691 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1692 {0x0005,
1696 RTW_PWR_CMD_WRITE, BIT(7), 0},
1697 {0x0005,
1701 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1702 {0x10C3,
1706 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1707 {0x0005,
1711 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1712 {0x0005,
1716 RTW_PWR_CMD_POLLING, BIT(0), 0},
1717 {0x0020,
1722 {0x10A8,
1726 RTW_PWR_CMD_WRITE, 0xFF, 0},
1727 {0x10A9,
1731 RTW_PWR_CMD_WRITE, 0xFF, 0xef},
1732 {0x10AA,
1736 RTW_PWR_CMD_WRITE, 0xFF, 0x0c},
1737 {0x0068,
1742 {0x0029,
1746 RTW_PWR_CMD_WRITE, 0xFF, 0xF9},
1747 {0x0024,
1751 RTW_PWR_CMD_WRITE, BIT(2), 0},
1752 {0x0074,
1757 {0x00AF,
1762 {0xFFFF,
1765 0,
1766 RTW_PWR_CMD_END, 0, 0},
1770 {0x0003,
1774 RTW_PWR_CMD_WRITE, BIT(2), 0},
1775 {0x0093,
1779 RTW_PWR_CMD_WRITE, BIT(3), 0},
1780 {0x001F,
1784 RTW_PWR_CMD_WRITE, 0xFF, 0},
1785 {0x00EF,
1789 RTW_PWR_CMD_WRITE, 0xFF, 0},
1790 {0xFF1A,
1794 RTW_PWR_CMD_WRITE, 0xFF, 0x30},
1795 {0x0049,
1799 RTW_PWR_CMD_WRITE, BIT(1), 0},
1800 {0x0006,
1804 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1805 {0x0002,
1809 RTW_PWR_CMD_WRITE, BIT(1), 0},
1810 {0x10C3,
1814 RTW_PWR_CMD_WRITE, BIT(0), 0},
1815 {0x0005,
1820 {0x0005,
1824 RTW_PWR_CMD_POLLING, BIT(1), 0},
1825 {0x0020,
1829 RTW_PWR_CMD_WRITE, BIT(3), 0},
1830 {0x0000,
1835 {0xFFFF,
1838 0,
1839 RTW_PWR_CMD_END, 0, 0},
1843 {0x0005,
1848 {0x0007,
1852 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1853 {0x0067,
1857 RTW_PWR_CMD_WRITE, BIT(5), 0},
1858 {0x0005,
1863 {0x004A,
1867 RTW_PWR_CMD_WRITE, BIT(0), 0},
1868 {0x0067,
1872 RTW_PWR_CMD_WRITE, BIT(5), 0},
1873 {0x0067,
1877 RTW_PWR_CMD_WRITE, BIT(4), 0},
1878 {0x004F,
1882 RTW_PWR_CMD_WRITE, BIT(0), 0},
1883 {0x0067,
1887 RTW_PWR_CMD_WRITE, BIT(1), 0},
1888 {0x0046,
1893 {0x0067,
1897 RTW_PWR_CMD_WRITE, BIT(2), 0},
1898 {0x0046,
1903 {0x0062,
1908 {0x0081,
1912 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1913 {0x0005,
1918 {0x0086,
1922 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1923 {0x0086,
1927 RTW_PWR_CMD_POLLING, BIT(1), 0},
1928 {0x0090,
1932 RTW_PWR_CMD_WRITE, BIT(1), 0},
1933 {0x0044,
1937 RTW_PWR_CMD_WRITE, 0xFF, 0},
1938 {0x0040,
1942 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1943 {0x0041,
1947 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1948 {0x0042,
1952 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1953 {0xFFFF,
1956 0,
1957 RTW_PWR_CMD_END, 0, 0},
1973 {0xFFFF, 0x00,
1980 {0x0001, 0xA841,
1984 {0xFFFF, 0x0000,
1991 {0x0001, 0xA841,
1995 {0x0002, 0x60C6,
1999 {0x0008, 0x3596,
2003 {0x0009, 0x321C,
2007 {0x000A, 0x9623,
2011 {0x0020, 0x94FF,
2015 {0x0021, 0xFFCF,
2019 {0x0026, 0xC006,
2023 {0x0029, 0xFF0E,
2027 {0x002A, 0x1840,
2031 {0xFFFF, 0x0000,
2038 {0x0001, 0xA841,
2042 {0x0002, 0x60C6,
2046 {0x0008, 0x3597,
2050 {0x0009, 0x321C,
2054 {0x000A, 0x9623,
2058 {0x0020, 0x94FF,
2062 {0x0021, 0xFFCF,
2066 {0x0026, 0xC006,
2070 {0x0029, 0xFF0E,
2074 {0x002A, 0x3040,
2078 {0xFFFF, 0x0000,
2096 [0] = { .addr = 0xc50, .mask = 0x7f },
2097 [1] = { .addr = 0xe50, .mask = 0x7f },
2109 {64, 64, 0, 0, 1},
2110 {64, 64, 64, 0, 1},
2183 {0xffffffff, 0xffffffff}, /* case-0 */
2184 {0x55555555, 0x55555555},
2185 {0x66555555, 0x66555555},
2186 {0xaaaaaaaa, 0xaaaaaaaa},
2187 {0x5a5a5a5a, 0x5a5a5a5a},
2188 {0xfafafafa, 0xfafafafa}, /* case-5 */
2189 {0x6a5a5555, 0xaaaaaaaa},
2190 {0x6a5a56aa, 0x6a5a56aa},
2191 {0x6a5a5a5a, 0x6a5a5a5a},
2192 {0x66555555, 0x5a5a5a5a},
2193 {0x66555555, 0x6a5a5a5a}, /* case-10 */
2194 {0x66555555, 0xfafafafa},
2195 {0x66555555, 0x5a5a5aaa},
2196 {0x66555555, 0x6aaa5aaa},
2197 {0x66555555, 0xaaaa5aaa},
2198 {0x66555555, 0xaaaaaaaa}, /* case-15 */
2199 {0xffff55ff, 0xfafafafa},
2200 {0xffff55ff, 0x6afa5afa},
2201 {0xaaffffaa, 0xfafafafa},
2202 {0xaa5555aa, 0x5a5a5a5a},
2203 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
2204 {0xaa5555aa, 0xaaaaaaaa},
2205 {0xffffffff, 0x5a5a5a5a},
2206 {0xffffffff, 0x5a5a5a5a},
2207 {0xffffffff, 0x55555555},
2208 {0xffffffff, 0x6a5a5aaa}, /* case-25 */
2209 {0x55555555, 0x5a5a5a5a},
2210 {0x55555555, 0xaaaaaaaa},
2211 {0x55555555, 0x6a5a6a5a},
2212 {0x66556655, 0x66556655},
2213 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
2214 {0xffffffff, 0x5aaa5aaa},
2215 {0x56555555, 0x5a5a5aaa},
2220 {0xffffffff, 0xffffffff}, /* case-100 */
2221 {0x55555555, 0x55555555},
2222 {0x66555555, 0x66555555},
2223 {0xaaaaaaaa, 0xaaaaaaaa},
2224 {0x5a5a5a5a, 0x5a5a5a5a},
2225 {0xfafafafa, 0xfafafafa}, /* case-105 */
2226 {0x5afa5afa, 0x5afa5afa},
2227 {0x55555555, 0xfafafafa},
2228 {0x66555555, 0xfafafafa},
2229 {0x66555555, 0x5a5a5a5a},
2230 {0x66555555, 0x6a5a5a5a}, /* case-110 */
2231 {0x66555555, 0xaaaaaaaa},
2232 {0xffff55ff, 0xfafafafa},
2233 {0xffff55ff, 0x5afa5afa},
2234 {0xffff55ff, 0xaaaaaaaa},
2235 {0xffff55ff, 0xffff55ff}, /* case-115 */
2236 {0xaaffffaa, 0x5afa5afa},
2237 {0xaaffffaa, 0xaaaaaaaa},
2238 {0xffffffff, 0xfafafafa},
2239 {0xffffffff, 0x5afa5afa},
2240 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
2241 {0x55ff55ff, 0x5afa5afa},
2242 {0x55ff55ff, 0xaaaaaaaa},
2243 {0x55ff55ff, 0x55ff55ff}
2248 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
2249 { {0x61, 0x45, 0x03, 0x11, 0x11} },
2250 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2251 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2252 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2253 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-5 */
2254 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2255 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2256 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2257 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2258 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
2259 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2260 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2261 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2262 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2263 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
2264 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2265 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2266 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2267 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2268 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
2269 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
2270 { {0x51, 0x0c, 0x03, 0x10, 0x54} },
2271 { {0x55, 0x08, 0x03, 0x10, 0x54} },
2272 { {0x65, 0x10, 0x03, 0x11, 0x10} },
2273 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
2274 { {0x51, 0x08, 0x03, 0x10, 0x50} },
2275 { {0x61, 0x08, 0x03, 0x11, 0x11} }
2280 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-100 */
2281 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-101 */
2282 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
2283 { {0x61, 0x30, 0x03, 0x11, 0x11} },
2284 { {0x61, 0x20, 0x03, 0x11, 0x11} },
2285 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
2286 { {0x61, 0x45, 0x03, 0x11, 0x10} },
2287 { {0x61, 0x3a, 0x03, 0x11, 0x10} },
2288 { {0x61, 0x30, 0x03, 0x11, 0x10} },
2289 { {0x61, 0x20, 0x03, 0x11, 0x10} },
2290 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
2291 { {0x61, 0x08, 0x03, 0x11, 0x14} },
2292 { {0x61, 0x08, 0x03, 0x10, 0x14} },
2293 { {0x51, 0x08, 0x03, 0x10, 0x54} },
2294 { {0x51, 0x08, 0x03, 0x10, 0x55} },
2295 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
2296 { {0x51, 0x45, 0x03, 0x10, 0x50} },
2297 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
2298 { {0x51, 0x30, 0x03, 0x10, 0x50} },
2299 { {0x51, 0x20, 0x03, 0x10, 0x50} },
2300 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-120 */
2301 { {0x51, 0x08, 0x03, 0x10, 0x50} }
2310 {0, 0, false, 7}, /* for normal */
2311 {0, 16, false, 7}, /* for WL-CPT */
2312 {4, 0, true, 1},
2319 {0, 0, false, 7}, /* for normal */
2320 {0, 16, false, 7}, /* for WL-CPT */
2321 {4, 0, true, 1},
2352 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2355 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2358 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2365 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2368 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2371 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2378 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2381 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2384 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2391 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2394 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2397 { 0, 1, 2, 2, 3, 4, 5, 5, 6, 7,
2403 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2409 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2415 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2421 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2427 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2433 0, 0, 1, 1, 2, 2, 3, 3, 4, 4,
2439 0, 1, 1, 1, 2, 2, 3, 3, 3, 4,
2445 0, 1, 1, 2, 2, 3, 3, 4, 4, 5,
2474 [2] = RTW_DEF_RFE(8822b, 2, 2, 0),
2475 [3] = RTW_DEF_RFE(8822b, 3, 0, 0),
2476 [5] = RTW_DEF_RFE(8822b, 5, 5, 0),
2480 {0xcb0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2481 {0xcb4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2482 {0xcba, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2483 {0xcbd, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2484 {0xc58, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2485 {0xcbd, BIT(0), RTW_REG_DOMAIN_MAC8},
2486 {0, 0, RTW_REG_DOMAIN_NL},
2487 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2488 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2489 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2490 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2491 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
2492 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
2493 {0, 0, RTW_REG_DOMAIN_NL},
2494 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
2495 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
2496 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
2497 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
2498 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_B},
2499 {0, 0, RTW_REG_DOMAIN_NL},
2500 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
2501 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2502 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
2503 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
2507 [EDCCA_TH_L2H_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE0}, .offset = 0},
2508 [EDCCA_TH_H2L_IDX] = {{.addr = 0x8a4, .mask = MASKBYTE1}, .offset = 0},
2529 .max_power_index = 0x3f,
2530 .csi_buf_pg_num = 0,
2533 .dig_min = 0x1c,
2541 .sys_func_en = 0xDC,
2550 .rf_base_addr = {0x2800, 0x2c00},
2551 .rf_sipi_addr = {0xc90, 0xe90},
2569 .coex_para_ver = 0x20070206,
2570 .bt_desired_ver = 0x6,
2592 .bt_afh_span_bw20 = 0x24,
2593 .bt_afh_span_bw40 = 0x36,
2600 .fw_fifo_addr = {0x780, 0x700, 0x780, 0x660, 0x650, 0x680},