Lines Matching +full:0 +full:x51
57 efuse->rfe_option = map->rfe_option & 0x1f; in rtw8821c_read_efuse()
62 efuse->lna_type_2g = map->lna_type_2g[0]; in rtw8821c_read_efuse()
63 efuse->lna_type_5g = map->lna_type_5g[0]; in rtw8821c_read_efuse()
65 efuse->country_code[0] = map->country_code[0]; in rtw8821c_read_efuse()
68 efuse->regd = map->rf_board_option & 0x7; in rtw8821c_read_efuse()
69 efuse->thermal_meter[0] = map->thermal_meter; in rtw8821c_read_efuse()
74 hal->pkg_type = map->rfe_option & BIT(5) ? 1 : 0; in rtw8821c_read_efuse()
77 case 0x2: in rtw8821c_read_efuse()
78 case 0x4: in rtw8821c_read_efuse()
79 case 0x7: in rtw8821c_read_efuse()
80 case 0xa: in rtw8821c_read_efuse()
81 case 0xc: in rtw8821c_read_efuse()
82 case 0xf: in rtw8821c_read_efuse()
87 for (i = 0; i < 4; i++) in rtw8821c_read_efuse()
91 efuse->txpwr_idx_table[0].pwr_idx_2g = map->txpwr_idx_table[1].pwr_idx_2g; in rtw8821c_read_efuse()
108 return 0; in rtw8821c_read_efuse()
112 0x081, 0x088, 0x090, 0x099, 0x0a2, 0x0ac, 0x0b6, 0x0c0, 0x0cc, 0x0d8,
113 0x0e5, 0x0f2, 0x101, 0x110, 0x120, 0x131, 0x143, 0x156, 0x16a, 0x180,
114 0x197, 0x1af, 0x1c8, 0x1e3, 0x200, 0x21e, 0x23e, 0x261, 0x285, 0x2ab,
115 0x2d3, 0x2fe, 0x32b, 0x35c, 0x38e, 0x3c4, 0x3fe
120 u8 i = 0; in rtw8821c_get_swing_index()
123 swing = rtw_read32_mask(rtwdev, REG_TXSCALE_A, 0xffe00000); in rtw8821c_get_swing_index()
124 for (i = 0; i < ARRAY_SIZE(rtw8821c_txscale_tbl); i++) { in rtw8821c_get_swing_index()
144 dm_info->delta_power_index[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
145 dm_info->delta_power_index_last[RF_PATH_A] = 0; in rtw8821c_pwrtrack_init()
155 rtw_write32(rtwdev, 0x1C94, 0xAFFFAFFF); in rtw8821c_phy_bf_init()
188 crystal_cap = rtwdev->efuse.crystal_cap & 0x3F; in rtw8821c_phy_set_param()
189 rtw_write32_mask(rtwdev, REG_AFE_XTAL_CTRL, 0x7e000000, crystal_cap); in rtw8821c_phy_set_param()
190 rtw_write32_mask(rtwdev, REG_AFE_PLL_CTRL, 0x7e, crystal_cap); in rtw8821c_phy_set_param()
191 rtw_write32_mask(rtwdev, REG_CCK0_FAREPORT, BIT(18) | BIT(22), 0); in rtw8821c_phy_set_param()
195 hal->ch_param[0] = rtw_read32_mask(rtwdev, REG_TXSF2, MASKDWORD); in rtw8821c_phy_set_param()
200 rtwdev->dm_info.cck_pd_default = rtw_read8(rtwdev, REG_CSRATIO) & 0x1f; in rtw8821c_phy_set_param()
216 rtw_write8(rtwdev, REG_PRECNT_CTRL, (u8)(pre_txcnt & 0xFF)); in rtw8821c_mac_init()
232 rtw_write16(rtwdev, REG_TXPAUSE, 0); in rtw8821c_mac_init()
257 rtw_write8(rtwdev, REG_ACKTO_CCK, 0x40); in rtw8821c_mac_init()
264 return 0; in rtw8821c_mac_init()
315 rf_reg18 = rtw_read_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK); in rtw8821c_set_channel_rf()
348 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x1); in rtw8821c_set_channel_rf()
349 rtw_write_rf(rtwdev, RF_PATH_A, 0x64, 0xf, 0xf); in rtw8821c_set_channel_rf()
352 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTDBG, BIT(6), 0x0); in rtw8821c_set_channel_rf()
355 rtw_write_rf(rtwdev, RF_PATH_A, 0x18, RFREG_MASK, rf_reg18); in rtw8821c_set_channel_rf()
357 rtw_write_rf(rtwdev, RF_PATH_A, RF_XTALX2, BIT(19), 0); in rtw8821c_set_channel_rf()
365 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
366 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
367 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
368 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
371 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
372 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x1); in rtw8821c_set_channel_rxdfir()
373 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
374 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
377 rtw_write32_mask(rtwdev, REG_ACBB0, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
378 rtw_write32_mask(rtwdev, REG_ACBBRXFIR, BIT(29) | BIT(28), 0x2); in rtw8821c_set_channel_rxdfir()
379 rtw_write32_mask(rtwdev, REG_TXDFIR, BIT(31), 0x1); in rtw8821c_set_channel_rxdfir()
380 rtw_write32_mask(rtwdev, REG_CHFIR, BIT(31), 0x0); in rtw8821c_set_channel_rxdfir()
389 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); in rtw8821c_cck_tx_filter_srrc()
390 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); in rtw8821c_cck_tx_filter_srrc()
391 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8821c_cck_tx_filter_srrc()
392 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); in rtw8821c_cck_tx_filter_srrc()
394 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); in rtw8821c_cck_tx_filter_srrc()
395 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); in rtw8821c_cck_tx_filter_srrc()
396 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
397 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); in rtw8821c_cck_tx_filter_srrc()
398 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
399 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); in rtw8821c_cck_tx_filter_srrc()
400 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
401 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); in rtw8821c_cck_tx_filter_srrc()
402 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
403 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
406 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xf8fe); in rtw8821c_cck_tx_filter_srrc()
407 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x64b80c1c); in rtw8821c_cck_tx_filter_srrc()
408 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x8810); in rtw8821c_cck_tx_filter_srrc()
409 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x01235667); in rtw8821c_cck_tx_filter_srrc()
411 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); in rtw8821c_cck_tx_filter_srrc()
412 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); in rtw8821c_cck_tx_filter_srrc()
413 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); in rtw8821c_cck_tx_filter_srrc()
414 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); in rtw8821c_cck_tx_filter_srrc()
415 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00027); in rtw8821c_cck_tx_filter_srrc()
416 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); in rtw8821c_cck_tx_filter_srrc()
417 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00029); in rtw8821c_cck_tx_filter_srrc()
418 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); in rtw8821c_cck_tx_filter_srrc()
419 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00026); in rtw8821c_cck_tx_filter_srrc()
420 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
422 rtw_write32_mask(rtwdev, REG_CCA_FLTR, MASKHWORD, 0xe82c); in rtw8821c_cck_tx_filter_srrc()
424 hal->ch_param[0]); in rtw8821c_cck_tx_filter_srrc()
430 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00002); in rtw8821c_cck_tx_filter_srrc()
431 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001e); in rtw8821c_cck_tx_filter_srrc()
432 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
433 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0001c); in rtw8821c_cck_tx_filter_srrc()
434 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
435 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000e); in rtw8821c_cck_tx_filter_srrc()
436 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
437 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWA, RFREG_MASK, 0x0000c); in rtw8821c_cck_tx_filter_srrc()
438 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWD0, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
439 rtw_write_rf(rtwdev, RF_PATH_A, RF_LUTWE2, RFREG_MASK, 0x00000); in rtw8821c_cck_tx_filter_srrc()
450 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x1); in rtw8821c_set_channel_bb()
451 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x0); in rtw8821c_set_channel_bb()
452 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x0); in rtw8821c_set_channel_bb()
453 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
455 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x0); in rtw8821c_set_channel_bb()
456 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x96a); in rtw8821c_set_channel_bb()
465 rtw_write32_mask(rtwdev, REG_TXSF2, MASKDWORD, 0x0000b81c); in rtw8821c_set_channel_bb()
466 rtw_write32_mask(rtwdev, REG_TXSF6, MASKLWORD, 0x0000); in rtw8821c_set_channel_bb()
467 rtw_write32_mask(rtwdev, REG_TXFILTER, MASKDWORD, 0x00003667); in rtw8821c_set_channel_bb()
470 hal->ch_param[0]); in rtw8821c_set_channel_bb()
477 rtw_write32_mask(rtwdev, REG_ENTXCCK, BIT(18), 0x1); in rtw8821c_set_channel_bb()
478 rtw_write32_mask(rtwdev, REG_CCK_CHECK, BIT(7), 0x1); in rtw8821c_set_channel_bb()
479 rtw_write32_mask(rtwdev, REG_RXPSEL, BIT(28), 0x0); in rtw8821c_set_channel_bb()
480 rtw_write32_mask(rtwdev, REG_RXCCAMSK, 0x0000FC00, 15); in rtw8821c_set_channel_bb()
483 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x1); in rtw8821c_set_channel_bb()
485 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x2); in rtw8821c_set_channel_bb()
487 rtw_write32_mask(rtwdev, REG_TXSCALE_A, 0xf00, 0x3); in rtw8821c_set_channel_bb()
490 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x494); in rtw8821c_set_channel_bb()
492 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x453); in rtw8821c_set_channel_bb()
494 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x452); in rtw8821c_set_channel_bb()
496 rtw_write32_mask(rtwdev, REG_CLKTRK, 0x1ffe0000, 0x412); in rtw8821c_set_channel_bb()
504 val32 &= 0xffcffc00; in rtw8821c_set_channel_bb()
505 val32 |= 0x10010000; in rtw8821c_set_channel_bb()
508 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
517 val32 &= 0xff3ff300; in rtw8821c_set_channel_bb()
518 val32 |= 0x20020000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
522 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
526 val32 &= 0xfcffcf00; in rtw8821c_set_channel_bb()
527 val32 |= 0x40040000 | ((primary_ch_idx & 0xf) << 2) | in rtw8821c_set_channel_bb()
531 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x1); in rtw8821c_set_channel_bb()
535 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
536 val32 |= 0x200240; in rtw8821c_set_channel_bb()
539 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
540 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
544 val32 &= 0xefcefc00; in rtw8821c_set_channel_bb()
545 val32 |= 0x300380; in rtw8821c_set_channel_bb()
548 rtw_write32_mask(rtwdev, REG_ADC160, BIT(30), 0x0); in rtw8821c_set_channel_bb()
549 rtw_write32_mask(rtwdev, REG_ADC40, BIT(31), 0x1); in rtw8821c_set_channel_bb()
558 u32 swing2setting[4] = {0x200, 0x16a, 0x101, 0x0b6}; in rtw8821c_get_bb_swing()
563 tx_bb_swing = 0; in rtw8821c_get_bb_swing()
591 s8 rx_pwr_all = 0; in get_cck_rx_pwr()
592 s8 lna_gain = 0; in get_cck_rx_pwr()
594 if (efuse->rfe_option == 0) { in get_cck_rx_pwr()
618 u8 lna_idx = 0; in query_phy_status_page0()
619 u8 vga_idx = 0; in query_phy_status_page0()
667 page = *phy_status & 0xf; in query_phy_status()
670 case 0: in query_phy_status()
687 static const u32 offset_txagc[2] = {0x1d00, 0x1d80}; in rtw8821c_set_tx_power_index_by_rate()
691 for (j = 0; j < rtw_rate_size[rs]; j++) { in rtw8821c_set_tx_power_index_by_rate()
694 shift = rate & 0x3; in rtw8821c_set_tx_power_index_by_rate()
696 if (shift == 0x3 || rate == DESC_RATEVHT1SS_MCS9) { in rtw8821c_set_tx_power_index_by_rate()
697 rate_idx = rate & 0xfc; in rtw8821c_set_tx_power_index_by_rate()
700 *phy_pwr_idx = 0; in rtw8821c_set_tx_power_index_by_rate()
708 u32 phy_pwr_idx = 0; in rtw8821c_set_tx_power_index()
711 for (path = 0; path < hal->rf_path_num; path++) { in rtw8821c_set_tx_power_index()
712 for (rs = 0; rs <= __RTW_RATE_SECTION_2SS_MAX; rs++) { in rtw8821c_set_tx_power_index()
742 dm_info->cck_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
746 dm_info->ofdm_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
750 dm_info->ht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
754 dm_info->vht_ok_cnt = FIELD_GET(GENMASK(15, 0), crc32_cnt); in rtw8821c_false_alarm_statistics()
762 dm_info->cck_cca_cnt = FIELD_GET(GENMASK(15, 0), cca32_cnt); in rtw8821c_false_alarm_statistics()
770 rtw_write32_set(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
771 rtw_write32_clr(rtwdev, REG_CNTRST, BIT(0)); in rtw8821c_false_alarm_statistics()
777 struct rtw_iqk_para para = {.clear = 0, .segment_iqk = 0}; in rtw8821c_do_iqk()
787 for (counter = 0; counter < 300; counter++) { in rtw8821c_do_iqk()
789 if (rf_reg == 0xabcde) in rtw8821c_do_iqk()
793 rtw_write_rf(rtwdev, RF_PATH_A, RF_DTXLOK, RFREG_MASK, 0x0); in rtw8821c_do_iqk()
796 iqk_fail_mask = rtw_read32_mask(rtwdev, REG_IQKFAILMSK, GENMASK(7, 0)); in rtw8821c_do_iqk()
798 "iqk counter=%d reload=%d do_iqk_cnt=%d n_iqk_fail(mask)=0x%02x\n", in rtw8821c_do_iqk()
814 rtw_write8_mask(rtwdev, REG_BT_TDMA_TIME, BIT_MASK_SAMPLE_RATE, 0x5); in rtw8821c_coex_cfg_init()
843 u8 regval = 0; in rtw8821c_coex_cfg_ant_switch()
875 if (coex_rfe->rfe_module_type != 0x4 && in rtw8821c_coex_cfg_ant_switch()
876 coex_rfe->rfe_module_type != 0x2) in rtw8821c_coex_cfg_ant_switch()
877 regval = 0x3; in rtw8821c_coex_cfg_ant_switch()
879 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
881 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
883 regval = (!polarity_inverse ? 0x1 : 0x2); in rtw8821c_coex_cfg_ant_switch()
896 regval = (!polarity_inverse ? 0x2 : 0x1); in rtw8821c_coex_cfg_ant_switch()
909 regval = (!polarity_inverse ? 0x0 : 0x1); in rtw8821c_coex_cfg_ant_switch()
952 coex_rfe->ant_switch_polarity = 0; in rtw8821c_coex_cfg_rfe_type()
957 case 0: in rtw8821c_coex_cfg_rfe_type()
1014 u8 swing_lower_bound = 0; in rtw8821c_txagc_swing_offset()
1015 u8 max_pwr_idx_offset = 0xf; in rtw8821c_txagc_swing_offset()
1016 s8 agc_index = 0; in rtw8821c_txagc_swing_offset()
1022 if (delta_pwr_idx >= 0) { in rtw8821c_txagc_swing_offset()
1032 } else if (delta_pwr_idx < 0) { in rtw8821c_txagc_swing_offset()
1087 pwr_idx_offset_lower = 0 - tx_pwr_idx; in rtw8821c_pwrtrack_set()
1100 if (rtwdev->efuse.thermal_meter[0] == 0xff) in rtw8821c_phy_pwrtrack()
1103 thermal_value = rtw_read_rf(rtwdev, RF_PATH_A, RF_T_METER, 0xfc00); in rtw8821c_phy_pwrtrack()
1138 if (efuse->power_track_type != 0) in rtw8821c_pwr_track()
1143 GENMASK(17, 16), 0x03); in rtw8821c_pwr_track()
1198 "is_linked=%d, lv=%d, n_rx=%d, cs_ratio=0x%x, pd_th=0x%x, cck_fa_avg=%d\n", in rtw8821c_phy_cck_pd_set()
1206 rtw_write32_mask(rtwdev, REG_PWRTH, 0x3f0000, pd[new_lvl]); in rtw8821c_phy_cck_pd_set()
1207 rtw_write32_mask(rtwdev, REG_PWRTH2, 0x1f0000, in rtw8821c_phy_cck_pd_set()
1237 {0x0086,
1241 RTW_PWR_CMD_WRITE, BIT(0), 0},
1242 {0x0086,
1247 {0x004A,
1251 RTW_PWR_CMD_WRITE, BIT(0), 0},
1252 {0x0005,
1256 RTW_PWR_CMD_WRITE, BIT(3) | BIT(4) | BIT(7), 0},
1257 {0x0300,
1261 RTW_PWR_CMD_WRITE, 0xFF, 0},
1262 {0x0301,
1266 RTW_PWR_CMD_WRITE, 0xFF, 0},
1267 {0xFFFF,
1270 0,
1271 RTW_PWR_CMD_END, 0, 0},
1275 {0x0020,
1279 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1280 {0x0001,
1285 {0x0000,
1289 RTW_PWR_CMD_WRITE, BIT(5), 0},
1290 {0x0005,
1294 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3) | BIT(2)), 0},
1295 {0x0075,
1299 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1300 {0x0006,
1305 {0x0075,
1309 RTW_PWR_CMD_WRITE, BIT(0), 0},
1310 {0x0006,
1314 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1315 {0x0005,
1319 RTW_PWR_CMD_WRITE, BIT(7), 0},
1320 {0x0005,
1324 RTW_PWR_CMD_WRITE, (BIT(4) | BIT(3)), 0},
1325 {0x10C3,
1329 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1330 {0x0005,
1334 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1335 {0x0005,
1339 RTW_PWR_CMD_POLLING, BIT(0), 0},
1340 {0x0020,
1345 {0x0074,
1350 {0x0022,
1354 RTW_PWR_CMD_WRITE, BIT(1), 0},
1355 {0x0062,
1361 {0x0061,
1365 RTW_PWR_CMD_WRITE, (BIT(7) | BIT(6) | BIT(5)), 0},
1366 {0x007C,
1370 RTW_PWR_CMD_WRITE, BIT(1), 0},
1371 {0xFFFF,
1374 0,
1375 RTW_PWR_CMD_END, 0, 0},
1379 {0x0093,
1383 RTW_PWR_CMD_WRITE, BIT(3), 0},
1384 {0x001F,
1388 RTW_PWR_CMD_WRITE, 0xFF, 0},
1389 {0x0049,
1393 RTW_PWR_CMD_WRITE, BIT(1), 0},
1394 {0x0006,
1398 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1399 {0x0002,
1403 RTW_PWR_CMD_WRITE, BIT(1), 0},
1404 {0x10C3,
1408 RTW_PWR_CMD_WRITE, BIT(0), 0},
1409 {0x0005,
1414 {0x0005,
1418 RTW_PWR_CMD_POLLING, BIT(1), 0},
1419 {0x0020,
1423 RTW_PWR_CMD_WRITE, BIT(3), 0},
1424 {0x0000,
1429 {0xFFFF,
1432 0,
1433 RTW_PWR_CMD_END, 0, 0},
1437 {0x0007,
1441 RTW_PWR_CMD_WRITE, 0xFF, 0x20},
1442 {0x0067,
1446 RTW_PWR_CMD_WRITE, BIT(5), 0},
1447 {0x0005,
1452 {0x004A,
1456 RTW_PWR_CMD_WRITE, BIT(0), 0},
1457 {0x0067,
1461 RTW_PWR_CMD_WRITE, BIT(5), 0},
1462 {0x0067,
1466 RTW_PWR_CMD_WRITE, BIT(4), 0},
1467 {0x004F,
1471 RTW_PWR_CMD_WRITE, BIT(0), 0},
1472 {0x0067,
1476 RTW_PWR_CMD_WRITE, BIT(1), 0},
1477 {0x0046,
1482 {0x0067,
1486 RTW_PWR_CMD_WRITE, BIT(2), 0},
1487 {0x0046,
1492 {0x0062,
1497 {0x0081,
1501 RTW_PWR_CMD_WRITE, BIT(7) | BIT(6), 0},
1502 {0x0005,
1507 {0x0086,
1511 RTW_PWR_CMD_WRITE, BIT(0), BIT(0)},
1512 {0x0086,
1516 RTW_PWR_CMD_POLLING, BIT(1), 0},
1517 {0x0090,
1521 RTW_PWR_CMD_WRITE, BIT(1), 0},
1522 {0x0044,
1526 RTW_PWR_CMD_WRITE, 0xFF, 0},
1527 {0x0040,
1531 RTW_PWR_CMD_WRITE, 0xFF, 0x90},
1532 {0x0041,
1536 RTW_PWR_CMD_WRITE, 0xFF, 0x00},
1537 {0x0042,
1541 RTW_PWR_CMD_WRITE, 0xFF, 0x04},
1542 {0xFFFF,
1545 0,
1546 RTW_PWR_CMD_END, 0, 0},
1562 {0xFFFF, 0x00,
1569 {0xFFFF, 0x0000,
1576 {0x0009, 0x6380,
1580 {0xFFFF, 0x0000,
1587 {0xFFFF, 0x0000,
1605 [0] = { .addr = 0xc50, .mask = 0x7f },
1615 /* not sure what [0] stands for */
1618 {16, 16, 0, 0, 1},
1619 {16, 16, 16, 0, 1},
1624 /* not sure what [0] stands for */
1696 {0x55555555, 0x55555555}, /* case-0 */
1697 {0x55555555, 0x55555555},
1698 {0x66555555, 0x66555555},
1699 {0xaaaaaaaa, 0xaaaaaaaa},
1700 {0x5a5a5a5a, 0x5a5a5a5a},
1701 {0xfafafafa, 0xfafafafa}, /* case-5 */
1702 {0x6a5a5555, 0xaaaaaaaa},
1703 {0x6a5a56aa, 0x6a5a56aa},
1704 {0x6a5a5a5a, 0x6a5a5a5a},
1705 {0x66555555, 0x5a5a5a5a},
1706 {0x66555555, 0x6a5a5a5a}, /* case-10 */
1707 {0x66555555, 0xaaaaaaaa},
1708 {0x66555555, 0x6a5a5aaa},
1709 {0x66555555, 0x6aaa6aaa},
1710 {0x66555555, 0x6a5a5aaa},
1711 {0x66555555, 0xaaaaaaaa}, /* case-15 */
1712 {0xffff55ff, 0xfafafafa},
1713 {0xffff55ff, 0x6afa5afa},
1714 {0xaaffffaa, 0xfafafafa},
1715 {0xaa5555aa, 0x5a5a5a5a},
1716 {0xaa5555aa, 0x6a5a5a5a}, /* case-20 */
1717 {0xaa5555aa, 0xaaaaaaaa},
1718 {0xffffffff, 0x55555555},
1719 {0xffffffff, 0x5a5a5a5a},
1720 {0xffffffff, 0x5a5a5a5a},
1721 {0xffffffff, 0x5a5a5aaa}, /* case-25 */
1722 {0x55555555, 0x5a5a5a5a},
1723 {0x55555555, 0xaaaaaaaa},
1724 {0x66555555, 0x6a5a6a5a},
1725 {0x66556655, 0x66556655},
1726 {0x66556aaa, 0x6a5a6aaa}, /* case-30 */
1727 {0xffffffff, 0x5aaa5aaa},
1728 {0x56555555, 0x5a5a5aaa}
1733 {0xffffffff, 0xffffffff}, /* case-100 */
1734 {0xffff55ff, 0xfafafafa},
1735 {0x66555555, 0x66555555},
1736 {0xaaaaaaaa, 0xaaaaaaaa},
1737 {0x5a5a5a5a, 0x5a5a5a5a},
1738 {0xffffffff, 0xffffffff}, /* case-105 */
1739 {0x5afa5afa, 0x5afa5afa},
1740 {0x55555555, 0xfafafafa},
1741 {0x66555555, 0xfafafafa},
1742 {0x66555555, 0x5a5a5a5a},
1743 {0x66555555, 0x6a5a5a5a}, /* case-110 */
1744 {0x66555555, 0xaaaaaaaa},
1745 {0xffff55ff, 0xfafafafa},
1746 {0xffff55ff, 0x5afa5afa},
1747 {0xffff55ff, 0xaaaaaaaa},
1748 {0xffff55ff, 0xffff55ff}, /* case-115 */
1749 {0xaaffffaa, 0x5afa5afa},
1750 {0xaaffffaa, 0xaaaaaaaa},
1751 {0xffffffff, 0xfafafafa},
1752 {0xffff55ff, 0xfafafafa},
1753 {0xffffffff, 0xaaaaaaaa}, /* case-120 */
1754 {0xffff55ff, 0x5afa5afa},
1755 {0xffff55ff, 0x5afa5afa},
1756 {0x55ff55ff, 0x55ff55ff}
1761 { {0x00, 0x00, 0x00, 0x00, 0x00} }, /* case-0 */
1762 { {0x61, 0x45, 0x03, 0x11, 0x11} }, /* case-1 */
1763 { {0x61, 0x3a, 0x03, 0x11, 0x11} },
1764 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1765 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1766 { {0x61, 0x3a, 0x03, 0x11, 0x11} }, /* case-5 */
1767 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1768 { {0x61, 0x35, 0x03, 0x11, 0x10} },
1769 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1770 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1771 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-10 */
1772 { {0x61, 0x08, 0x03, 0x11, 0x15} },
1773 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1774 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1775 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1776 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-15 */
1777 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1778 { {0x51, 0x3a, 0x03, 0x11, 0x50} },
1779 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1780 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1781 { {0x51, 0x10, 0x03, 0x10, 0x50} }, /* case-20 */
1782 { {0x51, 0x4a, 0x03, 0x10, 0x50} },
1783 { {0x51, 0x08, 0x03, 0x30, 0x54} },
1784 { {0x55, 0x08, 0x03, 0x10, 0x54} },
1785 { {0x65, 0x10, 0x03, 0x11, 0x10} },
1786 { {0x51, 0x10, 0x03, 0x10, 0x51} }, /* case-25 */
1787 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1788 { {0x61, 0x08, 0x03, 0x11, 0x11} }
1793 { {0x00, 0x00, 0x00, 0x40, 0x00} }, /* case-100 */
1794 { {0x61, 0x45, 0x03, 0x11, 0x11} },
1795 { {0x61, 0x25, 0x03, 0x11, 0x11} },
1796 { {0x61, 0x35, 0x03, 0x11, 0x11} },
1797 { {0x61, 0x20, 0x03, 0x11, 0x11} },
1798 { {0x61, 0x10, 0x03, 0x11, 0x11} }, /* case-105 */
1799 { {0x61, 0x45, 0x03, 0x11, 0x10} },
1800 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1801 { {0x61, 0x30, 0x03, 0x11, 0x10} },
1802 { {0x61, 0x20, 0x03, 0x11, 0x10} },
1803 { {0x61, 0x10, 0x03, 0x11, 0x10} }, /* case-110 */
1804 { {0x61, 0x10, 0x03, 0x11, 0x11} },
1805 { {0x61, 0x08, 0x03, 0x10, 0x14} },
1806 { {0x51, 0x08, 0x03, 0x10, 0x54} },
1807 { {0x51, 0x08, 0x03, 0x10, 0x55} },
1808 { {0x51, 0x08, 0x07, 0x10, 0x54} }, /* case-115 */
1809 { {0x51, 0x45, 0x03, 0x10, 0x50} },
1810 { {0x51, 0x3a, 0x03, 0x10, 0x50} },
1811 { {0x51, 0x30, 0x03, 0x10, 0x50} },
1812 { {0x51, 0x21, 0x03, 0x10, 0x50} },
1813 { {0x51, 0x21, 0x03, 0x10, 0x50} }, /* case-120 */
1814 { {0x51, 0x10, 0x03, 0x10, 0x50} }
1817 static const struct coex_5g_afh_map afh_5g_8821c[] = { {0, 0, 0} };
1821 {0, 0, false, 7}, /* for normal */
1822 {0, 20, false, 7}, /* for WL-CPT */
1830 {0, 0, false, 7}, /* for normal */
1831 {0, 20, false, 7}, /* for WL-CPT */
1835 {0, 28, true, 5}
1841 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1843 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1845 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1850 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1852 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1854 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1859 {0, 1, 1, 2, 3, 3, 3, 4, 4, 5, 5, 6, 6, 6, 7, 8, 8, 8, 9, 9, 9, 10, 10,
1861 {0, 1, 1, 1, 2, 3, 3, 4, 4, 5, 5, 5, 6, 6, 7, 8, 8, 9, 9, 10, 10, 11,
1863 {0, 1, 2, 2, 3, 4, 4, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 9, 10, 10, 11,
1868 {0, 1, 1, 2, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, 7, 7, 8, 8, 9, 9, 10, 11, 11,
1870 {0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 5, 6, 7, 7, 8, 8, 9, 10, 10, 11, 11,
1872 {0, 1, 1, 1, 2, 3, 3, 3, 4, 4, 4, 5, 6, 6, 7, 7, 8, 8, 9, 10, 10, 11,
1877 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1882 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1887 0, 0, 0, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 3, 4, 4,
1892 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5, 5,
1897 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1902 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1907 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4,
1912 0, 1, 1, 1, 1, 2, 2, 2, 3, 3, 3, 4, 4, 4, 5, 5,
1917 .pwrtrk_5gb_n[0] = rtw8821c_pwrtrk_5gb_n[0],
1920 .pwrtrk_5gb_p[0] = rtw8821c_pwrtrk_5gb_p[0],
1923 .pwrtrk_5ga_n[0] = rtw8821c_pwrtrk_5ga_n[0],
1926 .pwrtrk_5ga_p[0] = rtw8821c_pwrtrk_5ga_p[0],
1940 [0] = RTW_DEF_RFE(8821c, 0, 0, 0),
1941 [2] = RTW_DEF_RFE_EXT(8821c, 0, 0, 0, 2),
1942 [4] = RTW_DEF_RFE_EXT(8821c, 0, 0, 0, 2),
1943 [6] = RTW_DEF_RFE(8821c, 0, 0, 0),
1947 {0xCB0, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1948 {0xCB4, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1949 {0xCBA, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1950 {0, 0, RTW_REG_DOMAIN_NL},
1951 {0x430, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1952 {0x434, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1953 {0x42a, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1954 {0x426, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1955 {0x45e, BIT(3), RTW_REG_DOMAIN_MAC8},
1956 {0x454, MASKLWORD, RTW_REG_DOMAIN_MAC16},
1957 {0, 0, RTW_REG_DOMAIN_NL},
1958 {0x4c, BIT(24) | BIT(23), RTW_REG_DOMAIN_MAC32},
1959 {0x64, BIT(0), RTW_REG_DOMAIN_MAC8},
1960 {0x4c6, BIT(4), RTW_REG_DOMAIN_MAC8},
1961 {0x40, BIT(5), RTW_REG_DOMAIN_MAC8},
1962 {0x1, RFREG_MASK, RTW_REG_DOMAIN_RF_A},
1963 {0, 0, RTW_REG_DOMAIN_NL},
1964 {0x550, MASKDWORD, RTW_REG_DOMAIN_MAC32},
1965 {0x522, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1966 {0x953, BIT(1), RTW_REG_DOMAIN_MAC8},
1967 {0xc50, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1968 {0x60A, MASKBYTE0, RTW_REG_DOMAIN_MAC8},
1988 .max_power_index = 0x3f,
1989 .csi_buf_pg_num = 0,
1992 .dig_min = 0x1c,
2000 .sys_func_en = 0xD8,
2008 .rf_base_addr = {0x2800, 0x2c00},
2009 .rf_sipi_addr = {0xc90, 0xe90},
2024 .coex_para_ver = 0x19092746,
2025 .bt_desired_ver = 0x46,
2047 .bt_afh_span_bw20 = 0x24,
2048 .bt_afh_span_bw40 = 0x36,