Lines Matching +full:0 +full:x2000
44 #define AR9170_RX_PHY_RATE_CCK_1M 0x0a
45 #define AR9170_RX_PHY_RATE_CCK_2M 0x14
46 #define AR9170_RX_PHY_RATE_CCK_5M 0x37
47 #define AR9170_RX_PHY_RATE_CCK_11M 0x6e
49 #define AR9170_ENC_ALG_NONE 0x0
50 #define AR9170_ENC_ALG_WEP64 0x1
51 #define AR9170_ENC_ALG_TKIP 0x2
52 #define AR9170_ENC_ALG_AESCCMP 0x4
53 #define AR9170_ENC_ALG_WEP128 0x5
54 #define AR9170_ENC_ALG_WEP256 0x6
55 #define AR9170_ENC_ALG_CENC 0x7
57 #define AR9170_RX_ENC_SOFTWARE 0x8
59 #define AR9170_RX_STATUS_MODULATION 0x03
60 #define AR9170_RX_STATUS_MODULATION_S 0
61 #define AR9170_RX_STATUS_MODULATION_CCK 0x00
62 #define AR9170_RX_STATUS_MODULATION_OFDM 0x01
63 #define AR9170_RX_STATUS_MODULATION_HT 0x02
64 #define AR9170_RX_STATUS_MODULATION_DUPOFDM 0x03
67 #define AR9170_RX_STATUS_SHORT_PREAMBLE 0x08
68 #define AR9170_RX_STATUS_GREENFIELD 0x08
70 #define AR9170_RX_STATUS_MPDU 0x30
72 #define AR9170_RX_STATUS_MPDU_SINGLE 0x00
73 #define AR9170_RX_STATUS_MPDU_FIRST 0x20
74 #define AR9170_RX_STATUS_MPDU_MIDDLE 0x30
75 #define AR9170_RX_STATUS_MPDU_LAST 0x10
77 #define AR9170_RX_STATUS_CONT_AGGR 0x40
78 #define AR9170_RX_STATUS_TOTAL_ERROR 0x80
80 #define AR9170_RX_ERROR_RXTO 0x01
81 #define AR9170_RX_ERROR_OVERRUN 0x02
82 #define AR9170_RX_ERROR_DECRYPT 0x04
83 #define AR9170_RX_ERROR_FCS 0x08
84 #define AR9170_RX_ERROR_WRONG_RA 0x10
85 #define AR9170_RX_ERROR_PLCP 0x20
86 #define AR9170_RX_ERROR_MMIC 0x40
89 #define AR9170_TX_MAC_PROT_RTS 0x0001
90 #define AR9170_TX_MAC_PROT_CTS 0x0002
91 #define AR9170_TX_MAC_PROT 0x0003
93 #define AR9170_TX_MAC_NO_ACK 0x0004
95 #define AR9170_TX_MAC_BACKOFF 0x0008
96 #define AR9170_TX_MAC_BURST 0x0010
97 #define AR9170_TX_MAC_AGGR 0x0020
100 #define AR9170_TX_MAC_ENCR_NONE 0x0000
101 #define AR9170_TX_MAC_ENCR_RC4 0x0040
102 #define AR9170_TX_MAC_ENCR_CENC 0x0080
103 #define AR9170_TX_MAC_ENCR_AES 0x00c0
105 #define AR9170_TX_MAC_MMIC 0x0100
106 #define AR9170_TX_MAC_HW_DURATION 0x0200
108 #define AR9170_TX_MAC_QOS 0x0c00
109 #define AR9170_TX_MAC_DISABLE_TXOP 0x1000
110 #define AR9170_TX_MAC_TXOP_RIFS 0x2000
111 #define AR9170_TX_MAC_IMM_BA 0x4000
114 #define AR9170_TX_PHY_MOD_CCK 0x00000000
115 #define AR9170_TX_PHY_MOD_OFDM 0x00000001
116 #define AR9170_TX_PHY_MOD_HT 0x00000002
119 #define AR9170_TX_PHY_SHORT_PREAMBLE 0x00000004
120 #define AR9170_TX_PHY_GREENFIELD 0x00000004
124 #define AR9170_TX_PHY_BW_20MHZ 0
133 #define AR9170_TX_PHY_TX_PWR (0x3f << \
144 #define AR9170_TX_PHY_MCS (0x7f << \
147 #define AR9170_TX_PHY_RATE_CCK_1M 0x0
148 #define AR9170_TX_PHY_RATE_CCK_2M 0x1
149 #define AR9170_TX_PHY_RATE_CCK_5M 0x2
150 #define AR9170_TX_PHY_RATE_CCK_11M 0x3
153 #define AR9170_TXRX_PHY_RATE_OFDM_6M 0xb
154 #define AR9170_TXRX_PHY_RATE_OFDM_9M 0xf
155 #define AR9170_TXRX_PHY_RATE_OFDM_12M 0xa
156 #define AR9170_TXRX_PHY_RATE_OFDM_18M 0xe
157 #define AR9170_TXRX_PHY_RATE_OFDM_24M 0x9
158 #define AR9170_TXRX_PHY_RATE_OFDM_36M 0xd
159 #define AR9170_TXRX_PHY_RATE_OFDM_48M 0x8
160 #define AR9170_TXRX_PHY_RATE_OFDM_54M 0xc
162 #define AR9170_TXRX_PHY_RATE_HT_MCS0 0x0
163 #define AR9170_TXRX_PHY_RATE_HT_MCS1 0x1
164 #define AR9170_TXRX_PHY_RATE_HT_MCS2 0x2
165 #define AR9170_TXRX_PHY_RATE_HT_MCS3 0x3
166 #define AR9170_TXRX_PHY_RATE_HT_MCS4 0x4
167 #define AR9170_TXRX_PHY_RATE_HT_MCS5 0x5
168 #define AR9170_TXRX_PHY_RATE_HT_MCS6 0x6
169 #define AR9170_TXRX_PHY_RATE_HT_MCS7 0x7
170 #define AR9170_TXRX_PHY_RATE_HT_MCS8 0x8
171 #define AR9170_TXRX_PHY_RATE_HT_MCS9 0x9
172 #define AR9170_TXRX_PHY_RATE_HT_MCS10 0xa
173 #define AR9170_TXRX_PHY_RATE_HT_MCS11 0xb
174 #define AR9170_TXRX_PHY_RATE_HT_MCS12 0xc
175 #define AR9170_TXRX_PHY_RATE_HT_MCS13 0xd
176 #define AR9170_TXRX_PHY_RATE_HT_MCS14 0xe
177 #define AR9170_TXRX_PHY_RATE_HT_MCS15 0xf
179 #define AR9170_TX_PHY_SHORT_GI 0x80000000
291 #define CARL9170_TX_SUPER_AMPDU_DENSITY_S 0
292 #define CARL9170_TX_SUPER_AMPDU_DENSITY 0x7
293 #define CARL9170_TX_SUPER_AMPDU_FACTOR 0x18
295 #define CARL9170_TX_SUPER_AMPDU_COMMIT_DENSITY 0x20
297 #define CARL9170_TX_SUPER_AMPDU_COMMIT_FACTOR 0x40
300 #define CARL9170_TX_SUPER_MISC_QUEUE 0x3
301 #define CARL9170_TX_SUPER_MISC_QUEUE_S 0
302 #define CARL9170_TX_SUPER_MISC_ASSIGN_SEQ 0x4
303 #define CARL9170_TX_SUPER_MISC_VIF_ID 0x38
305 #define CARL9170_TX_SUPER_MISC_FILL_IN_TSF 0x40
306 #define CARL9170_TX_SUPER_MISC_CAB 0x80
308 #define CARL9170_TX_SUPER_RI_TRIES 0x7
309 #define CARL9170_TX_SUPER_RI_TRIES_S 0
310 #define CARL9170_TX_SUPER_RI_ERP_PROT 0x18
312 #define CARL9170_TX_SUPER_RI_AMPDU 0x20
403 return (t->SAidx & 0xc0) >> 4 | in ar9170_get_decrypt_type()
404 (t->DAidx & 0xc0) >> 6; in ar9170_get_decrypt_type()
425 AR9170_TXQ_BK = 0, /* TXQ0 */