Lines Matching +full:rx +full:- +full:sample +full:- +full:delay +full:- +full:ns
1 // SPDX-License-Identifier: GPL-2.0+
14 #include <linux/delay.h>
80 /* RTL822X_VND2_XXXXX registers are only accessible when phydev->is_c45
81 * is set, they cannot be accessed by C45-over-C22.
140 struct device *dev = &phydev->mdio.dev; in rtl821x_probe()
142 u32 phy_id = phydev->drv->phy_id; in rtl821x_probe()
147 return -ENOMEM; in rtl821x_probe()
149 priv->clk = devm_clk_get_optional_enabled(dev, NULL); in rtl821x_probe()
150 if (IS_ERR(priv->clk)) in rtl821x_probe()
151 return dev_err_probe(dev, PTR_ERR(priv->clk), in rtl821x_probe()
158 priv->phycr1 = ret & (RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF); in rtl821x_probe()
159 if (of_property_read_bool(dev->of_node, "realtek,aldps-enable")) in rtl821x_probe()
160 priv->phycr1 |= RTL8211F_ALDPS_PLL_OFF | RTL8211F_ALDPS_ENABLE | RTL8211F_ALDPS_XTAL_OFF; in rtl821x_probe()
162 priv->has_phycr2 = !(phy_id == RTL_8211FVD_PHYID); in rtl821x_probe()
163 if (priv->has_phycr2) { in rtl821x_probe()
168 priv->phycr2 = ret & RTL8211F_CLKOUT_EN; in rtl821x_probe()
169 if (of_property_read_bool(dev->of_node, "realtek,clkout-disable")) in rtl821x_probe()
170 priv->phycr2 &= ~RTL8211F_CLKOUT_EN; in rtl821x_probe()
173 phydev->priv = priv; in rtl821x_probe()
210 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8201_config_intr()
233 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211b_config_intr()
255 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211e_config_intr()
278 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl8211f_config_intr()
368 if (phydev->speed == SPEED_100 && phydev->autoneg == AUTONEG_DISABLE) { in rtl8211_config_aneg()
388 struct rtl821x_priv *priv = phydev->priv; in rtl8211f_config_init()
389 struct device *dev = &phydev->mdio.dev; in rtl8211f_config_init()
395 priv->phycr1); in rtl8211f_config_init()
402 switch (phydev->interface) { in rtl8211f_config_init()
423 default: /* the rest of the modes imply leaving delay as is. */ in rtl8211f_config_init()
430 dev_err(dev, "Failed to update the TX delay register\n"); in rtl8211f_config_init()
434 "%s 2ns TX delay (and changing the value from pin-strapping RXD1 or the bootloader)\n", in rtl8211f_config_init()
438 "2ns TX delay was already %s (by pin-strapping RXD1 or bootloader configuration)\n", in rtl8211f_config_init()
445 dev_err(dev, "Failed to update the RX delay register\n"); in rtl8211f_config_init()
449 "%s 2ns RX delay (and changing the value from pin-strapping RXD0 or the bootloader)\n", in rtl8211f_config_init()
453 "2ns RX delay was already %s (by pin-strapping RXD0 or bootloader configuration)\n", in rtl8211f_config_init()
457 /* Disable PHY-mode EEE so LPI is passed to the MAC */ in rtl8211f_config_init()
463 if (priv->has_phycr2) { in rtl8211f_config_init()
465 RTL8211F_CLKOUT_EN, priv->phycr2); in rtl8211f_config_init()
480 struct rtl821x_priv *priv = phydev->priv; in rtl821x_suspend()
483 if (!phydev->wol_enabled) { in rtl821x_suspend()
489 clk_disable_unprepare(priv->clk); in rtl821x_suspend()
497 struct rtl821x_priv *priv = phydev->priv; in rtl821x_resume()
500 if (!phydev->wol_enabled) in rtl821x_resume()
501 clk_prepare_enable(priv->clk); in rtl821x_resume()
522 * - Link: Configurable subset of 10/100/1000 link rates in rtl8211f_led_hw_is_supported()
523 * - Active: Blink on activity, RX or TX is not differentiated in rtl8211f_led_hw_is_supported()
525 * - A: Link and Active indication at configurable, but matching, in rtl8211f_led_hw_is_supported()
527 * - B: Link indication at configurable subset of 10/100/1000 link in rtl8211f_led_hw_is_supported()
534 return -EINVAL; in rtl8211f_led_hw_is_supported()
538 return -EOPNOTSUPP; in rtl8211f_led_hw_is_supported()
540 /* RX and TX are not differentiated, either both are set or not set. */ in rtl8211f_led_hw_is_supported()
542 return -EOPNOTSUPP; in rtl8211f_led_hw_is_supported()
553 return -EINVAL; in rtl8211f_led_hw_control_get()
586 return -EINVAL; in rtl8211f_led_hw_control_set()
613 /* enable TX/RX delay for rgmii-* modes, and disable them for rgmii. */ in rtl8211e_config_init()
614 switch (phydev->interface) { in rtl8211e_config_init()
631 /* According to a sample driver there is a 0x1c config register on the in rtl8211e_config_init()
633 * the RX/TX delays otherwise controlled by RXDLY/TXDLY pins. in rtl8211e_config_init()
636 * 13 = Force Tx RX Delay controlled by bit12 bit11, in rtl8211e_config_init()
637 * 12 = RX Delay, 11 = TX Delay in rtl8211e_config_init()
677 dev_err(&phydev->mdio.dev, in rtl8366rb_config_init()
692 phydev->duplex = DUPLEX_FULL; in rtlgen_decode_physr()
694 phydev->duplex = DUPLEX_HALF; in rtlgen_decode_physr()
698 phydev->speed = SPEED_10; in rtlgen_decode_physr()
701 phydev->speed = SPEED_100; in rtlgen_decode_physr()
704 phydev->speed = SPEED_1000; in rtlgen_decode_physr()
707 phydev->speed = SPEED_10000; in rtlgen_decode_physr()
710 phydev->speed = SPEED_2500; in rtlgen_decode_physr()
713 phydev->speed = SPEED_5000; in rtlgen_decode_physr()
723 if (phydev->speed >= 1000) { in rtlgen_decode_physr()
725 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in rtlgen_decode_physr()
727 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in rtlgen_decode_physr()
729 phydev->master_slave_state = MASTER_SLAVE_STATE_UNSUPPORTED; in rtlgen_decode_physr()
741 if (!phydev->link) in rtlgen_read_status()
755 return __mdiobus_c45_read(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum); in rtlgen_read_vend2()
760 return __mdiobus_c45_write(phydev->mdio.bus, 0, MDIO_MMD_VEND2, regnum, in rtlgen_write_vend2()
777 ret = -EOPNOTSUPP; in rtlgen_read_mmd()
792 ret = -EOPNOTSUPP; in rtlgen_write_mmd()
801 if (ret != -EOPNOTSUPP) in rtl822x_read_mmd()
819 if (ret != -EOPNOTSUPP) in rtl822x_write_mmd()
831 phydev->phy_id != RTL_GENERIC_PHYID) in rtl822x_probe()
844 phydev->host_interfaces) || in rtl822xb_config_init()
845 phydev->interface == PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_config_init()
848 phydev->host_interfaces) || in rtl822xb_config_init()
849 phydev->interface == PHY_INTERFACE_MODE_SGMII; in rtl822xb_config_init()
852 __assign_bit(PHY_INTERFACE_MODE_2500BASEX, phydev->possible_interfaces, in rtl822xb_config_init()
854 __assign_bit(PHY_INTERFACE_MODE_SGMII, phydev->possible_interfaces, in rtl822xb_config_init()
863 phydev->rate_matching = RATE_MATCH_PAUSE; in rtl822xb_config_init()
866 phydev->rate_matching = RATE_MATCH_NONE; in rtl822xb_config_init()
899 /* Only rate matching at 2500base-x */ in rtl822xb_get_rate_matching()
924 phydev->supported, val & MDIO_PMA_SPEED_2_5G); in rtl822x_get_features()
926 phydev->supported, val & MDIO_PMA_SPEED_5G); in rtl822x_get_features()
928 phydev->supported, val & MDIO_SPEED_10G); in rtl822x_get_features()
937 if (phydev->autoneg == AUTONEG_ENABLE) { in rtl822x_config_aneg()
938 u16 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in rtl822x_config_aneg()
955 if (!phydev->link) in rtl822xb_update_interface()
965 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in rtl822xb_update_interface()
968 phydev->interface = PHY_INTERFACE_MODE_SGMII; in rtl822xb_update_interface()
977 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in rtl822x_read_status()
983 if (phydev->autoneg == AUTONEG_DISABLE || in rtl822x_read_status()
984 !phydev->autoneg_complete) in rtl822x_read_status()
991 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, lpadv); in rtl822x_read_status()
1012 phydev->supported); in rtl822x_c45_get_features()
1022 if (phydev->autoneg == AUTONEG_DISABLE) in rtl822x_c45_config_aneg()
1031 val = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in rtl822x_c45_config_aneg()
1050 if (phydev->autoneg == AUTONEG_ENABLE && genphy_c45_aneg_done(phydev)) { in rtl822x_c45_read_status()
1058 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in rtl822x_c45_read_status()
1064 if (!phydev->link) { in rtl822x_c45_read_status()
1065 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in rtl822x_c45_read_status()
1104 * Check a MMD register which is known to be non-zero.
1122 return phydev->phy_id == RTL_GENERIC_PHYID && in rtlgen_match_phy_device()
1128 return phydev->phy_id == RTL_GENERIC_PHYID && in rtl8226_match_phy_device()
1136 if (phydev->is_c45) in rtlgen_is_c45_match()
1137 return is_c45 && (id == phydev->c45_ids.device_ids[1]); in rtlgen_is_c45_match()
1139 return !is_c45 && (id == phydev->phy_id); in rtlgen_is_c45_match()
1144 return phydev->phy_id == RTL_8221B && rtlgen_supports_mmd(phydev); in rtl8221b_match_phy_device()
1169 if (phydev->is_c45) in rtl_internal_nbaset_match_phy_device()
1172 switch (phydev->phy_id) { in rtl_internal_nbaset_match_phy_device()
1211 phydev->autoneg = AUTONEG_DISABLE; in rtl9000a_config_init()
1212 phydev->speed = SPEED_100; in rtl9000a_config_init()
1213 phydev->duplex = DUPLEX_FULL; in rtl9000a_config_init()
1223 switch (phydev->master_slave_set) { in rtl9000a_config_aneg()
1234 return -EOPNOTSUPP; in rtl9000a_config_aneg()
1248 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in rtl9000a_read_status()
1249 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in rtl9000a_read_status()
1259 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in rtl9000a_read_status()
1261 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in rtl9000a_read_status()
1267 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in rtl9000a_read_status()
1269 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in rtl9000a_read_status()
1288 if (phydev->interrupts == PHY_INTERRUPT_ENABLED) { in rtl9000a_config_intr()
1413 .name = "RTL8211F-VD Gigabit Ethernet",
1425 .name = "Generic FE-GE Realtek PHY",
1458 .name = "RTL8226-CG 2.5Gbps PHY",
1468 .name = "RTL8226B-CG_RTL8221B-CG 2.5Gbps PHY",
1480 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C22)",
1493 .name = "RTL8221B-VB-CG 2.5Gbps PHY (C45)",
1504 .name = "RTL8221B-VM-CG 2.5Gbps PHY (C22)",
1517 .name = "RTL8221B-VN-CG 2.5Gbps PHY (C45)",
1539 .name = "Realtek Internal NBASE-T PHY",
1587 .name = "RTL8365MB-VC Gigabit Ethernet",