Lines Matching +full:phy +full:- +full:10 +full:base +full:- +full:t1l +full:- +full:2
1 // SPDX-License-Identifier: GPL-2.0-only
3 * Clause 45 PHY support
9 #include <linux/phy.h>
11 #include "mdio-open-alliance.h"
12 #include "phylib-internal.h"
15 * genphy_c45_baset1_able - checks if the PMA has BASE-T1 extended abilities
22 if (phydev->pma_extable == -ENODATA) { in genphy_c45_baset1_able()
27 phydev->pma_extable = val; in genphy_c45_baset1_able()
30 return !!(phydev->pma_extable & MDIO_PMA_EXTABLE_BT1); in genphy_c45_baset1_able()
34 * genphy_c45_pma_can_sleep - checks if the PMA have sleep support
49 * genphy_c45_pma_resume - wakes up the PMA module
55 return -EOPNOTSUPP; in genphy_c45_pma_resume()
63 * genphy_c45_pma_suspend - suspends the PMA module
69 return -EOPNOTSUPP; in genphy_c45_pma_suspend()
77 * genphy_c45_pma_baset1_setup_master_slave - configures forced master/slave
85 switch (phydev->master_slave_set) { in genphy_c45_pma_baset1_setup_master_slave()
98 return -EOPNOTSUPP; in genphy_c45_pma_baset1_setup_master_slave()
107 * genphy_c45_pma_setup_forced - configures a forced speed
115 if (phydev->duplex != DUPLEX_FULL) in genphy_c45_pma_setup_forced()
116 return -EINVAL; in genphy_c45_pma_setup_forced()
129 * in 802.3-2012 and 802.3-2015. in genphy_c45_pma_setup_forced()
133 switch (phydev->speed) { in genphy_c45_pma_setup_forced()
146 /* Assume 1000base-T */ in genphy_c45_pma_setup_forced()
151 /* Assume 2.5Gbase-T */ in genphy_c45_pma_setup_forced()
156 /* Assume 5Gbase-T */ in genphy_c45_pma_setup_forced()
161 /* Assume 10Gbase-T */ in genphy_c45_pma_setup_forced()
165 return -EINVAL; in genphy_c45_pma_setup_forced()
182 if (phydev->speed == SPEED_1000) in genphy_c45_pma_setup_forced()
196 * The preference is set in the BIT(4) of BASE-T1 AN
198 * is forced or not, it is set in the BIT(12) of BASE-T1
200 * Sets 10BASE-T1L Ability BIT(14) in BASE-T1 autonegotiation
215 switch (phydev->master_slave_set) { in genphy_c45_baset1_an_config_aneg()
235 return -EOPNOTSUPP; in genphy_c45_baset1_an_config_aneg()
238 adv_l |= linkmode_adv_to_mii_t1_adv_l_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
247 adv_m |= linkmode_adv_to_mii_t1_adv_m_t(phydev->advertising); in genphy_c45_baset1_an_config_aneg()
260 * genphy_c45_an_config_aneg - configure advertisement registers
263 * Configure advertisement registers based on modes set in phydev->advertising
273 linkmode_and(phydev->advertising, phydev->advertising, in genphy_c45_an_config_aneg()
274 phydev->supported); in genphy_c45_an_config_aneg()
285 adv = linkmode_adv_to_mii_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
296 adv = linkmode_adv_to_mii_10gbt_adv_t(phydev->advertising); in genphy_c45_an_config_aneg()
312 * genphy_c45_an_disable_aneg - disable auto-negotiation
315 * Disable auto-negotiation in the Clause 45 PHY. The link parameters
333 * genphy_c45_restart_aneg - Enable and restart auto-negotiation
336 * This assumes that the auto-negotiation MMD is present.
338 * Enable and restart auto-negotiation.
353 * genphy_c45_check_and_restart_aneg - Enable and restart auto-negotiation
357 * This assumes that the auto-negotiation MMD is present.
359 * Check, and restart auto-negotiation if needed.
387 * genphy_c45_aneg_done - return auto-negotiation complete status
390 * This assumes that the auto-negotiation MMD is present.
392 * Reads the status register from the auto-negotiation MMD, returning:
393 * - positive if auto-negotiation is complete
394 * - negative errno code on error
395 * - zero otherwise
412 * genphy_c45_read_link - read the overall link status from the MMDs
416 * that the link is up, set phydev->link to 1. If an error is encountered,
425 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_read_link()
434 phydev->link = 0; in genphy_c45_read_link()
444 * drops can be detected. Do not double-read the status in genphy_c45_read_link()
448 if (!phy_polling_mode(phydev) || !phydev->link) { in genphy_c45_read_link()
464 phydev->link = link; in genphy_c45_read_link()
470 /* Read the Clause 45 defined BASE-T1 AN (7.513) status register to check
471 * if autoneg is complete. If so read the BASE-T1 Autonegotiation
484 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising); in genphy_c45_baset1_read_lpa()
485 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
486 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, 0); in genphy_c45_baset1_read_lpa()
488 phydev->pause = 0; in genphy_c45_baset1_read_lpa()
489 phydev->asym_pause = 0; in genphy_c45_baset1_read_lpa()
494 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, 1); in genphy_c45_baset1_read_lpa()
500 mii_t1_adv_l_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
501 phydev->pause = val & MDIO_AN_T1_ADV_L_PAUSE_CAP ? 1 : 0; in genphy_c45_baset1_read_lpa()
502 phydev->asym_pause = val & MDIO_AN_T1_ADV_L_PAUSE_ASYM ? 1 : 0; in genphy_c45_baset1_read_lpa()
508 mii_t1_adv_m_mod_linkmode_t(phydev->lp_advertising, val); in genphy_c45_baset1_read_lpa()
514 * genphy_c45_read_lpa - read the link partner advertisement and pause
517 * Read the Clause 45 defined base (7.19) and 10G (7.33) status registers,
519 * in @phydev. This assumes that the auto-negotiation MMD is present, and
520 * the backplane bit (7.48.0) is clear. Clause 45 PHY drivers are expected
536 phydev->lp_advertising); in genphy_c45_read_lpa()
537 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
538 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, 0); in genphy_c45_read_lpa()
539 phydev->pause = 0; in genphy_c45_read_lpa()
540 phydev->asym_pause = 0; in genphy_c45_read_lpa()
545 linkmode_mod_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->lp_advertising, in genphy_c45_read_lpa()
548 /* Read the link partner's base page advertisement */ in genphy_c45_read_lpa()
553 mii_adv_mod_linkmode_adv_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
554 phydev->pause = val & LPA_PAUSE_CAP ? 1 : 0; in genphy_c45_read_lpa()
555 phydev->asym_pause = val & LPA_PAUSE_ASYM ? 1 : 0; in genphy_c45_read_lpa()
557 /* Read the link partner's 10G advertisement */ in genphy_c45_read_lpa()
562 mii_10gbt_stat_mod_linkmode_lpa_t(phydev->lp_advertising, val); in genphy_c45_read_lpa()
569 * genphy_c45_pma_baset1_read_master_slave - read forced master/slave
577 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
578 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_pma_baset1_read_master_slave()
585 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_pma_baset1_read_master_slave()
586 phydev->master_slave_state = MASTER_SLAVE_STATE_MASTER; in genphy_c45_pma_baset1_read_master_slave()
588 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_pma_baset1_read_master_slave()
589 phydev->master_slave_state = MASTER_SLAVE_STATE_SLAVE; in genphy_c45_pma_baset1_read_master_slave()
597 * genphy_c45_read_pma - read link speed etc from PMA
604 linkmode_zero(phydev->lp_advertising); in genphy_c45_read_pma()
612 phydev->speed = SPEED_10; in genphy_c45_read_pma()
615 phydev->speed = SPEED_100; in genphy_c45_read_pma()
618 phydev->speed = SPEED_1000; in genphy_c45_read_pma()
621 phydev->speed = SPEED_2500; in genphy_c45_read_pma()
624 phydev->speed = SPEED_5000; in genphy_c45_read_pma()
627 phydev->speed = SPEED_10000; in genphy_c45_read_pma()
630 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_pma()
634 phydev->duplex = DUPLEX_FULL; in genphy_c45_read_pma()
647 * genphy_c45_read_mdix - read mdix status from PMA
654 if (phydev->speed == SPEED_10000) { in genphy_c45_read_mdix()
662 phydev->mdix = ETH_TP_MDI; in genphy_c45_read_mdix()
666 phydev->mdix = ETH_TP_MDI_X; in genphy_c45_read_mdix()
670 phydev->mdix = ETH_TP_MDI_INVALID; in genphy_c45_read_mdix()
680 * genphy_c45_write_eee_adv - write advertised EEE link modes
689 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_write_eee_adv()
692 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 in genphy_c45_write_eee_adv()
707 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_write_eee_adv()
710 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 in genphy_c45_write_eee_adv()
724 phydev->supported_eee)) { in genphy_c45_write_eee_adv()
726 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register in genphy_c45_write_eee_adv()
743 * genphy_c45_read_eee_adv - read advertised EEE link modes
751 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_adv()
752 /* IEEE 802.3-2018 45.2.7.13 EEE advertisement 1 in genphy_c45_read_eee_adv()
762 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_adv()
763 /* IEEE 802.3-2022 45.2.7.16 EEE advertisement 2 in genphy_c45_read_eee_adv()
774 phydev->supported_eee)) { in genphy_c45_read_eee_adv()
775 /* IEEE 802.3cg-2019 45.2.7.25 10BASE-T1 AN control register in genphy_c45_read_eee_adv()
789 * genphy_c45_read_eee_lpa - read advertised LP EEE link modes
798 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_lpa()
799 /* IEEE 802.3-2018 45.2.7.14 EEE link partner ability 1 in genphy_c45_read_eee_lpa()
809 if (linkmode_intersects(phydev->supported_eee, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_lpa()
810 /* IEEE 802.3-2022 45.2.7.17 EEE link partner ability 2 in genphy_c45_read_eee_lpa()
821 phydev->supported_eee)) { in genphy_c45_read_eee_lpa()
822 /* IEEE 802.3cg-2019 45.2.7.26 10BASE-T1 AN status register in genphy_c45_read_eee_lpa()
836 * genphy_c45_read_eee_cap1 - read supported EEE link modes from register 3.20
843 /* IEEE 802.3-2018 45.2.3.10 EEE control and capability 1 in genphy_c45_read_eee_cap1()
850 /* The 802.3 2018 standard says the top 2 bits are reserved and should in genphy_c45_read_eee_cap1()
851 * read as 0. Also, it seems unlikely anybody will build a PHY which in genphy_c45_read_eee_cap1()
852 * supports 100GBASE-R deep sleep all the way down to 100BASE-TX EEE. in genphy_c45_read_eee_cap1()
858 mii_eee_cap1_mod_linkmode_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap1()
863 linkmode_and(phydev->supported_eee, phydev->supported_eee, in genphy_c45_read_eee_cap1()
864 phydev->supported); in genphy_c45_read_eee_cap1()
870 * genphy_c45_read_eee_cap2 - read supported EEE link modes from register 3.21
877 /* IEEE 802.3-2022 45.2.3.11 EEE control and capability 2 in genphy_c45_read_eee_cap2()
884 /* IEEE 802.3-2022 45.2.3.11 says 9 bits are reserved. */ in genphy_c45_read_eee_cap2()
888 mii_eee_cap2_mod_linkmode_sup_t(phydev->supported_eee, val); in genphy_c45_read_eee_cap2()
894 * genphy_c45_read_eee_abilities - read supported EEE link modes
905 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP1_FEATURES)) { in genphy_c45_read_eee_abilities()
912 if (linkmode_intersects(phydev->supported, PHY_EEE_CAP2_FEATURES)) { in genphy_c45_read_eee_abilities()
919 phydev->supported)) { in genphy_c45_read_eee_abilities()
920 /* IEEE 802.3cg-2019 45.2.1.186b 10BASE-T1L PMA status register in genphy_c45_read_eee_abilities()
928 phydev->supported_eee, in genphy_c45_read_eee_abilities()
937 * genphy_c45_an_config_eee_aneg - configure EEE advertisement
942 if (!phydev->eee_cfg.eee_enabled) { in genphy_c45_an_config_eee_aneg()
948 return genphy_c45_write_eee_adv(phydev, phydev->advertising_eee); in genphy_c45_an_config_eee_aneg()
953 * genphy_c45_pma_baset1_read_abilities - read supported baset1 link modes from PMA
956 * Read the supported link modes from the extended BASE-T1 ability register
967 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
971 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
975 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
983 phydev->supported, in genphy_c45_pma_baset1_read_abilities()
991 * genphy_c45_pma_read_ext_abilities - read supported link modes from PMA
1006 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1009 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1012 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1015 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1018 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1021 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1025 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1028 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1032 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1035 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1045 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1049 phydev->supported, in genphy_c45_pma_read_ext_abilities()
1064 * genphy_c45_pma_read_abilities - read supported link modes from PMA
1067 * Read the supported link modes from the PMA Status 2 (1.8) register. If bit
1069 * PMA Extended Abilities (1.11) register, indicating 1000BASET an 10G related
1078 linkmode_clear_bit(ETHTOOL_LINK_MODE_Autoneg_BIT, phydev->supported); in genphy_c45_pma_read_abilities()
1079 if (phydev->c45_ids.mmds_present & MDIO_DEVS_AN) { in genphy_c45_pma_read_abilities()
1086 phydev->supported); in genphy_c45_pma_read_abilities()
1094 phydev->supported, in genphy_c45_pma_read_abilities()
1098 phydev->supported, in genphy_c45_pma_read_abilities()
1102 phydev->supported, in genphy_c45_pma_read_abilities()
1121 * The preference is read from the BIT(4) of BASE-T1 AN
1123 * is forced or not, it is read from BASE-T1 AN advertisement
1131 phydev->master_slave_get = MASTER_SLAVE_CFG_UNKNOWN; in genphy_c45_baset1_read_status()
1132 phydev->master_slave_state = MASTER_SLAVE_STATE_UNKNOWN; in genphy_c45_baset1_read_status()
1144 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_FORCE; in genphy_c45_baset1_read_status()
1146 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_FORCE; in genphy_c45_baset1_read_status()
1149 phydev->master_slave_get = MASTER_SLAVE_CFG_MASTER_PREFERRED; in genphy_c45_baset1_read_status()
1151 phydev->master_slave_get = MASTER_SLAVE_CFG_SLAVE_PREFERRED; in genphy_c45_baset1_read_status()
1159 * genphy_c45_read_status - read PHY status
1162 * Reads status from PHY and sets phy_device members accordingly.
1172 phydev->speed = SPEED_UNKNOWN; in genphy_c45_read_status()
1173 phydev->duplex = DUPLEX_UNKNOWN; in genphy_c45_read_status()
1174 phydev->pause = 0; in genphy_c45_read_status()
1175 phydev->asym_pause = 0; in genphy_c45_read_status()
1177 if (phydev->autoneg == AUTONEG_ENABLE) { in genphy_c45_read_status()
1198 * genphy_c45_config_aneg - restart auto-negotiation or forced setup
1201 * Description: If auto-negotiation is enabled, we configure the
1202 * advertising, and then restart auto-negotiation. If it is not
1210 if (phydev->autoneg == AUTONEG_DISABLE) in genphy_c45_config_aneg()
1234 return -EOPNOTSUPP; in genphy_c45_loopback()
1243 * genphy_c45_fast_retrain - configure fast retrain registers
1247 * Description: If fast-retrain is enabled, we configure PHY as
1260 if (linkmode_test_bit(ETHTOOL_LINK_MODE_2500baseT_Full_BIT, phydev->supported)) { in genphy_c45_fast_retrain()
1278 * genphy_c45_plca_get_cfg - get PLCA configuration from standard registers
1282 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1296 return -ENODEV; in genphy_c45_plca_get_cfg()
1298 plca_cfg->version = ret & ~MDIO_OATC14_PLCA_IDM; in genphy_c45_plca_get_cfg()
1304 plca_cfg->enabled = !!(ret & MDIO_OATC14_PLCA_EN); in genphy_c45_plca_get_cfg()
1310 plca_cfg->node_cnt = (ret & MDIO_OATC14_PLCA_NCNT) >> 8; in genphy_c45_plca_get_cfg()
1311 plca_cfg->node_id = (ret & MDIO_OATC14_PLCA_ID); in genphy_c45_plca_get_cfg()
1317 plca_cfg->to_tmr = ret & MDIO_OATC14_PLCA_TOT; in genphy_c45_plca_get_cfg()
1323 plca_cfg->burst_cnt = (ret & MDIO_OATC14_PLCA_MAXBC) >> 8; in genphy_c45_plca_get_cfg()
1324 plca_cfg->burst_tmr = (ret & MDIO_OATC14_PLCA_BTMR); in genphy_c45_plca_get_cfg()
1331 * genphy_c45_plca_set_cfg - set PLCA configuration using standard registers
1333 * @plca_cfg: structure containing the PLCA configuration. Fields set to -1 are
1336 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1346 // PLCA IDVER is read-only in genphy_c45_plca_set_cfg()
1347 if (plca_cfg->version >= 0) in genphy_c45_plca_set_cfg()
1348 return -EINVAL; in genphy_c45_plca_set_cfg()
1351 if (plca_cfg->enabled == 0) { in genphy_c45_plca_set_cfg()
1361 if (plca_cfg->node_cnt >= 0 || plca_cfg->node_id >= 0) { in genphy_c45_plca_set_cfg()
1362 /* if one between node count and node ID is -not- to be in genphy_c45_plca_set_cfg()
1366 if (plca_cfg->node_cnt < 0 || plca_cfg->node_id < 0) { in genphy_c45_plca_set_cfg()
1376 if (plca_cfg->node_cnt >= 0) in genphy_c45_plca_set_cfg()
1378 (plca_cfg->node_cnt << 8); in genphy_c45_plca_set_cfg()
1380 if (plca_cfg->node_id >= 0) in genphy_c45_plca_set_cfg()
1382 (plca_cfg->node_id); in genphy_c45_plca_set_cfg()
1391 if (plca_cfg->to_tmr >= 0) { in genphy_c45_plca_set_cfg()
1394 plca_cfg->to_tmr); in genphy_c45_plca_set_cfg()
1401 if (plca_cfg->burst_cnt >= 0 || plca_cfg->burst_tmr >= 0) { in genphy_c45_plca_set_cfg()
1402 /* if one between burst count and burst timer is -not- to be in genphy_c45_plca_set_cfg()
1406 if (plca_cfg->burst_cnt < 0 || plca_cfg->burst_tmr < 0) { in genphy_c45_plca_set_cfg()
1416 if (plca_cfg->burst_cnt >= 0) in genphy_c45_plca_set_cfg()
1418 (plca_cfg->burst_cnt << 8); in genphy_c45_plca_set_cfg()
1420 if (plca_cfg->burst_tmr >= 0) in genphy_c45_plca_set_cfg()
1422 (plca_cfg->burst_tmr); in genphy_c45_plca_set_cfg()
1432 if (plca_cfg->enabled > 0) { in genphy_c45_plca_set_cfg()
1446 * genphy_c45_plca_get_status - get PLCA status from standard registers
1450 * Description: if the PHY complies to the Open Alliance TC14 10BASE-T1S PLCA
1463 plca_st->pst = !!(ret & MDIO_OATC14_PLCA_PST); in genphy_c45_plca_get_status()
1469 * genphy_c45_eee_is_active - get EEE status
1473 * Description: this function will read link partner PHY advertisement
1482 if (!phydev->eee_cfg.eee_enabled) in genphy_c45_eee_is_active()
1492 linkmode_and(common, phydev->advertising_eee, tmp_lp); in genphy_c45_eee_is_active()
1496 return phy_check_valid(phydev->speed, phydev->duplex, common); in genphy_c45_eee_is_active()
1501 * genphy_c45_ethtool_get_eee - get EEE supported and status
1513 ret = genphy_c45_eee_is_active(phydev, data->lp_advertised); in genphy_c45_ethtool_get_eee()
1517 data->eee_active = phydev->eee_active; in genphy_c45_ethtool_get_eee()
1518 linkmode_andnot(data->supported, phydev->supported_eee, in genphy_c45_ethtool_get_eee()
1519 phydev->eee_disabled_modes); in genphy_c45_ethtool_get_eee()
1520 linkmode_copy(data->advertised, phydev->advertising_eee); in genphy_c45_ethtool_get_eee()
1526 * genphy_c45_ethtool_set_eee - set EEE supported and status
1534 * non-destructive way.
1536 * value if there was a change which triggered auto-neg.
1543 if (data->eee_enabled) { in genphy_c45_ethtool_set_eee()
1544 unsigned long *adv = data->advertised; in genphy_c45_ethtool_set_eee()
1549 if (linkmode_andnot(tmp, adv, phydev->supported_eee)) { in genphy_c45_ethtool_set_eee()
1551 return -EINVAL; in genphy_c45_ethtool_set_eee()
1554 linkmode_andnot(phydev->advertising_eee, adv, in genphy_c45_ethtool_set_eee()
1555 phydev->eee_disabled_modes); in genphy_c45_ethtool_set_eee()
1556 } else if (linkmode_empty(phydev->advertising_eee)) { in genphy_c45_ethtool_set_eee()
1580 .name = "Generic Clause 45 PHY",