1 // SPDX-License-Identifier: GPL-2.0+
13 #include <dt-bindings/net/microchip-lan78xx.h>
42 	struct lan88xx_priv *priv = phydev->priv;  in lan88xx_suspend()
45 	if (!priv->wolopts)  in lan88xx_suspend()
105 	 * Write 24-bit value 0x12B00A to register. Setting MrvlTrFix1000Kf,  in lan88xx_config_TR_regs()
113 	 * Write 24-bit value 0xD2C46F to register. Setting SSTrKf1000Slv,  in lan88xx_config_TR_regs()
121 	 * Write 24-bit value 0x620 to register. Setting rem_upd_done_thresh  in lan88xx_config_TR_regs()
129 	 * Write 24-bit value 0xEEFFDD to register. Setting  in lan88xx_config_TR_regs()
138 	 * Write 24-bit value 0x071448 to register. Setting  in lan88xx_config_TR_regs()
146 	 * Write 24-bit value 0x13132F to register. Setting  in lan88xx_config_TR_regs()
154 	 * Write 24-bit value 0x0 to register. Setting eee_3level_delay,  in lan88xx_config_TR_regs()
162 	 * Write 24-bit value 0x91B06C to register. Setting  in lan88xx_config_TR_regs()
171 	 * Write 24-bit value 0xC0A028 to register. Setting  in lan88xx_config_TR_regs()
180 	 * Write 24-bit value 0x041600 to register. Setting  in lan88xx_config_TR_regs()
189 	 * Write 24-bit value 0x000004 to register. Setting TrFreeze bits.  in lan88xx_config_TR_regs()
198 	struct device *dev = &phydev->mdio.dev;  in lan88xx_probe()
205 		return -ENOMEM;  in lan88xx_probe()
207 	priv->wolopts = 0;  in lan88xx_probe()
209 	len = of_property_read_variable_u32_array(dev->of_node,  in lan88xx_probe()
210 						  "microchip,led-modes",  in lan88xx_probe()
220 				return -EINVAL;  in lan88xx_probe()
226 	} else if (len == -EOVERFLOW) {  in lan88xx_probe()
227 		return -EINVAL;  in lan88xx_probe()
231 	priv->chip_id = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_ID);  in lan88xx_probe()
232 	priv->chip_rev = phy_read_mmd(phydev, 3, LAN88XX_MMD3_CHIP_REV);  in lan88xx_probe()
234 	phydev->priv = priv;  in lan88xx_probe()
241 	struct device *dev = &phydev->mdio.dev;  in lan88xx_remove()
242 	struct lan88xx_priv *priv = phydev->priv;  in lan88xx_remove()
251 	struct lan88xx_priv *priv = phydev->priv;  in lan88xx_set_wol()
253 	priv->wolopts = wol->wolopts;  in lan88xx_set_wol()
263 	switch (phydev->mdix_ctrl) {  in lan88xx_set_mdix()
315 	/* Reset PHY to ensure MII_LPA provides up-to-date information. This  in lan88xx_link_change_notify()
316 	 * issue is reproducible only after parallel detection, as described  in lan88xx_link_change_notify()
317 	 * in IEEE 802.3-2022, Section 28.2.3.1 ("Parallel detection function"),  in lan88xx_link_change_notify()
318 	 * where the link partner does not support auto-negotiation.  in lan88xx_link_change_notify()
320 	if (phydev->state == PHY_NOLINK) {  in lan88xx_link_change_notify()
335 	if (!phydev->autoneg && phydev->speed == 100) {  in lan88xx_link_change_notify()
363  * lan937x_tx_read_mdix_status - Read the MDIX status for the LAN937x TX PHY.
368  * Note that MDIX status is not supported in AUTO mode, and will be set
382 		phydev->mdix_ctrl = ETH_TP_MDI_AUTO;  in lan937x_tx_read_mdix_status()
384 		phydev->mdix = ETH_TP_MDI_INVALID;  in lan937x_tx_read_mdix_status()
386 		phydev->mdix_ctrl = ETH_TP_MDI_X;  in lan937x_tx_read_mdix_status()
387 		phydev->mdix = ETH_TP_MDI_X;  in lan937x_tx_read_mdix_status()
389 		phydev->mdix_ctrl = ETH_TP_MDI;  in lan937x_tx_read_mdix_status()
390 		phydev->mdix = ETH_TP_MDI;  in lan937x_tx_read_mdix_status()
397  * lan937x_tx_read_status - Read the status for the LAN937x TX PHY.
417  * lan937x_tx_set_mdix - Set the MDIX mode for the LAN937x TX PHY.
422  * MDI (straight-through), MDIX (crossover), or AUTO (auto-MDIX). If the mode
431 	switch (phydev->mdix_ctrl) {  in lan937x_tx_set_mdix()
450  * lan937x_tx_config_aneg - Configure auto-negotiation and fixed modes for the
455  * proceeds to configure the auto-negotiation or fixed mode settings