Lines Matching +full:5 +full:gbase +full:- +full:x
1 // SPDX-License-Identifier: GPL-2.0+
10 * via observation and experimentation for a setup using single-lane Serdes:
12 * SGMII PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for <= 1G)
13 * 10GBASE-KR PHYXS -- BASE-T PCS -- 10G PMA -- AN -- Copper (for 10G)
14 * 10GBASE-KR PHYXS -- BASE-R PCS -- Fiber
18 * XAUI PHYXS -- <appropriate PCS as above>
104 /* These registers appear at 0x800X and 0xa00X - the 0xa00X control
108 MV_AN_CTRL1000 = 0x8000, /* 1000base-T control register */
109 MV_AN_STAT1000 = 0x8001, /* 1000base-T status register */
178 return phydev->drv->driver_data; in to_mv3310_chip()
216 temp = chip->hwmon_read_temp_reg(phydev); in mv3310_hwmon_read()
220 *value = ((temp & 0xff) - 75) * 1000; in mv3310_hwmon_read()
225 return -EOPNOTSUPP; in mv3310_hwmon_read()
249 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310) in mv3310_hwmon_config()
265 struct device *dev = &phydev->mdio.dev; in mv3310_hwmon_probe()
266 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_hwmon_probe()
269 priv->hwmon_name = devm_kstrdup(dev, dev_name(dev), GFP_KERNEL); in mv3310_hwmon_probe()
270 if (!priv->hwmon_name) in mv3310_hwmon_probe()
271 return -ENODEV; in mv3310_hwmon_probe()
273 for (i = j = 0; priv->hwmon_name[i]; i++) { in mv3310_hwmon_probe()
274 if (isalnum(priv->hwmon_name[i])) { in mv3310_hwmon_probe()
276 priv->hwmon_name[j] = priv->hwmon_name[i]; in mv3310_hwmon_probe()
280 priv->hwmon_name[j] = '\0'; in mv3310_hwmon_probe()
286 priv->hwmon_dev = devm_hwmon_device_register_with_info(dev, in mv3310_hwmon_probe()
287 priv->hwmon_name, phydev, in mv3310_hwmon_probe()
290 return PTR_ERR_OR_ZERO(priv->hwmon_dev); in mv3310_hwmon_probe()
312 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_power_up()
325 if (phydev->drv->phy_id != MARVELL_PHY_ID_88X3310 || in mv3310_power_up()
326 priv->firmware_ver < 0x00030000) in mv3310_power_up()
350 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_get_downshift()
353 if (!priv->has_downshift) in mv3310_get_downshift()
354 return -EOPNOTSUPP; in mv3310_get_downshift()
371 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_set_downshift()
375 if (!priv->has_downshift) in mv3310_set_downshift()
376 return -EOPNOTSUPP; in mv3310_set_downshift()
384 * "ethtool --set-phy-tunable ethN downshift on". The intention is in mv3310_set_downshift()
393 return -E2BIG; in mv3310_set_downshift()
395 ds -= 1; in mv3310_set_downshift()
455 return -EINVAL; in mv3310_set_edpd()
473 sfp_parse_support(phydev->sfp_bus, id, support, interfaces); in mv3310_sfp_insert()
474 iface = sfp_select_interface(phydev->sfp_bus, support); in mv3310_sfp_insert()
477 dev_err(&phydev->mdio.dev, "incompatible SFP module inserted\n"); in mv3310_sfp_insert()
478 return -EINVAL; in mv3310_sfp_insert()
498 if (!phydev->is_c45 || in mv3310_probe()
499 (phydev->c45_ids.devices_in_package & mmd_mask) != mmd_mask) in mv3310_probe()
500 return -ENODEV; in mv3310_probe()
507 dev_warn(&phydev->mdio.dev, in mv3310_probe()
508 "PHY failed to boot firmware, status=%04x\n", ret); in mv3310_probe()
509 return -ENODEV; in mv3310_probe()
512 priv = devm_kzalloc(&phydev->mdio.dev, sizeof(*priv), GFP_KERNEL); in mv3310_probe()
514 return -ENOMEM; in mv3310_probe()
516 dev_set_drvdata(&phydev->mdio.dev, priv); in mv3310_probe()
522 priv->firmware_ver = ret << 16; in mv3310_probe()
528 priv->firmware_ver |= ret; in mv3310_probe()
531 priv->firmware_ver >> 24, (priv->firmware_ver >> 16) & 255, in mv3310_probe()
532 (priv->firmware_ver >> 8) & 255, priv->firmware_ver & 255); in mv3310_probe()
534 if (chip->has_downshift) in mv3310_probe()
535 priv->has_downshift = chip->has_downshift(phydev); in mv3310_probe()
546 chip->init_supported_interfaces(priv->supported_interfaces); in mv3310_probe()
574 * support 2.5GBASET and 5GBASET. For these models, we can still read their
575 * 2.5G/5G extended abilities register (1.21). We detect these models based on
581 if (!(phydev->c45_ids.devices_in_package & MDIO_DEVS_PMAPMD)) in mv3310_has_pma_ngbaset_quirk()
585 return (phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_has_pma_ngbaset_quirk()
640 return -1; in mv2110_select_mactype()
691 return -1; in mv3310_select_mactype()
790 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_fill_possible_interfaces()
791 unsigned long *possible = phydev->possible_interfaces; in mv3310_fill_possible_interfaces()
792 const struct mv3310_mactype *mactype = priv->mactype; in mv3310_fill_possible_interfaces()
794 if (mactype->interface_10g != PHY_INTERFACE_MODE_NA) in mv3310_fill_possible_interfaces()
795 __set_bit(priv->mactype->interface_10g, possible); in mv3310_fill_possible_interfaces()
797 if (!mactype->fixed_interface) { in mv3310_fill_possible_interfaces()
806 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_config_init()
811 if (!test_bit(phydev->interface, priv->supported_interfaces)) in mv3310_config_init()
812 return -ENODEV; in mv3310_config_init()
814 phydev->mdix_ctrl = ETH_TP_MDI_AUTO; in mv3310_config_init()
824 if (!phy_interface_empty(phydev->host_interfaces)) { in mv3310_config_init()
825 mactype = chip->select_mactype(phydev->host_interfaces); in mv3310_config_init()
829 err = chip->set_mactype(phydev, mactype); in mv3310_config_init()
835 mactype = chip->get_mactype(phydev); in mv3310_config_init()
839 if (mactype >= chip->n_mactypes || !chip->mactypes[mactype].valid) { in mv3310_config_init()
841 return -EINVAL; in mv3310_config_init()
844 priv->mactype = &chip->mactypes[mactype]; in mv3310_config_init()
848 /* Enable EDPD mode - saving 600mW */ in mv3310_config_init()
855 if (err && err != -EOPNOTSUPP) in mv3310_config_init()
876 phydev->supported, in mv3310_get_features()
880 phydev->supported, in mv3310_get_features()
892 switch (phydev->mdix_ctrl) { in mv3310_config_mdix()
903 return -EINVAL; in mv3310_config_mdix()
924 if (phydev->autoneg == AUTONEG_DISABLE) in mv3310_config_aneg()
936 reg = linkmode_adv_to_mii_ctrl1000_t(phydev->advertising); in mv3310_config_aneg()
963 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_update_interface()
965 if (!phydev->link) in mv3310_update_interface()
974 if (priv->mactype->fixed_interface) { in mv3310_update_interface()
975 phydev->interface = priv->mactype->interface_10g; in mv3310_update_interface()
980 * instance) between Cisco SGMII, 2500BaseX, 5GBase-R and 10GBase-R / in mv3310_update_interface()
982 * Florian suggests setting phydev->interface to communicate this to the in mv3310_update_interface()
985 switch (phydev->speed) { in mv3310_update_interface()
987 phydev->interface = priv->mactype->interface_10g; in mv3310_update_interface()
990 phydev->interface = PHY_INTERFACE_MODE_5GBASER; in mv3310_update_interface()
993 phydev->interface = PHY_INTERFACE_MODE_2500BASEX; in mv3310_update_interface()
998 phydev->interface = PHY_INTERFACE_MODE_SGMII; in mv3310_update_interface()
1005 /* 10GBASE-ER,LR,LRM,SR do not support autonegotiation. */
1008 phydev->link = 1; in mv3310_read_status_10gbaser()
1009 phydev->speed = SPEED_10000; in mv3310_read_status_10gbaser()
1010 phydev->duplex = DUPLEX_FULL; in mv3310_read_status_10gbaser()
1011 phydev->port = PORT_FIBRE; in mv3310_read_status_10gbaser()
1034 phydev->link = 0; in mv3310_read_status_copper()
1045 phydev->speed = SPEED_10000; in mv3310_read_status_copper()
1049 phydev->speed = SPEED_5000; in mv3310_read_status_copper()
1053 phydev->speed = SPEED_2500; in mv3310_read_status_copper()
1057 phydev->speed = SPEED_1000; in mv3310_read_status_copper()
1061 phydev->speed = SPEED_100; in mv3310_read_status_copper()
1065 phydev->speed = SPEED_10; in mv3310_read_status_copper()
1069 phydev->duplex = cssr1 & MV_PCS_CSSR1_DUPLEX_FULL ? in mv3310_read_status_copper()
1071 phydev->port = PORT_TP; in mv3310_read_status_copper()
1072 phydev->mdix = cssr1 & MV_PCS_CSSR1_MDIX ? in mv3310_read_status_copper()
1085 mii_stat1000_mod_linkmode_lpa_t(phydev->lp_advertising, val); in mv3310_read_status_copper()
1098 phydev->speed = SPEED_UNKNOWN; in mv3310_read_status()
1099 phydev->duplex = DUPLEX_UNKNOWN; in mv3310_read_status()
1100 linkmode_zero(phydev->lp_advertising); in mv3310_read_status()
1101 phydev->link = 0; in mv3310_read_status()
1102 phydev->pause = 0; in mv3310_read_status()
1103 phydev->asym_pause = 0; in mv3310_read_status()
1104 phydev->mdix = ETH_TP_MDI_INVALID; in mv3310_read_status()
1117 if (phydev->link) in mv3310_read_status()
1126 switch (tuna->id) { in mv3310_get_tunable()
1132 return -EOPNOTSUPP; in mv3310_get_tunable()
1139 switch (tuna->id) { in mv3310_set_tunable()
1145 return -EOPNOTSUPP; in mv3310_set_tunable()
1151 struct mv3310_priv *priv = dev_get_drvdata(&phydev->mdio.dev); in mv3310_has_downshift()
1154 return priv->firmware_ver >= MV_VERSION(0,3,5,0); in mv3310_has_downshift()
1269 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3310_match_phy_device()
1278 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv3340_match_phy_device()
1289 if ((phydev->c45_ids.device_ids[MDIO_MMD_PMAPMD] & in mv211x_match_phy_device()
1315 wol->supported = WAKE_MAGIC; in mv3110_get_wol()
1316 wol->wolopts = 0; in mv3110_get_wol()
1323 wol->wolopts |= WAKE_MAGIC; in mv3110_get_wol()
1331 if (wol->wolopts & WAKE_MAGIC) { in mv3110_set_wol()
1342 ((phydev->attached_dev->dev_addr[5] << 8) | in mv3110_set_wol()
1343 phydev->attached_dev->dev_addr[4])); in mv3110_set_wol()
1349 ((phydev->attached_dev->dev_addr[3] << 8) | in mv3110_set_wol()
1350 phydev->attached_dev->dev_addr[2])); in mv3110_set_wol()
1356 ((phydev->attached_dev->dev_addr[1] << 8) | in mv3110_set_wol()
1357 phydev->attached_dev->dev_addr[0])); in mv3110_set_wol()
1378 /* Reset the clear WOL status bit as it does not self-clear */ in mv3110_set_wol()
1473 MODULE_DESCRIPTION("Marvell Alaska X/M multi-gigabit Ethernet PHY driver");