19 #define PHY_ID_AQ1202	0x03a1b445
20 #define PHY_ID_AQ2104	0x03a1b460
21 #define PHY_ID_AQR105	0x03a1b4a2
22 #define PHY_ID_AQR106	0x03a1b4d0
23 #define PHY_ID_AQR107	0x03a1b4e0
24 #define PHY_ID_AQCS109	0x03a1b5c2
25 #define PHY_ID_AQR405	0x03a1b4b0
26 #define PHY_ID_AQR111	0x03a1b610
27 #define PHY_ID_AQR111B0	0x03a1b612
28 #define PHY_ID_AQR112	0x03a1b662
29 #define PHY_ID_AQR412	0x03a1b712
30 #define PHY_ID_AQR113	0x31c31c40
31 #define PHY_ID_AQR113C	0x31c31c12
32 #define PHY_ID_AQR114C	0x31c31c22
33 #define PHY_ID_AQR115C	0x31c31c33
34 #define PHY_ID_AQR813	0x31c31cb2
36 #define MDIO_PHYXS_VEND_IF_STATUS		0xe812
38 #define MDIO_PHYXS_VEND_IF_STATUS_TYPE_KR	0
48 #define MDIO_AN_VEND_PROV			0xc400
55 #define MDIO_AN_VEND_PROV_DOWNSHIFT_MASK	GENMASK(3, 0)
58 #define MDIO_AN_RESVD_VEND_PROV			0xc410
59 #define MDIO_AN_RESVD_VEND_PROV_MDIX_AUTO	0
62 #define MDIO_AN_RESVD_VEND_PROV_MDIX_MASK	GENMASK(1, 0)
64 #define MDIO_AN_TX_VEND_STATUS1			0xc800
66 #define MDIO_AN_TX_VEND_STATUS1_10BASET		0
72 #define MDIO_AN_TX_VEND_STATUS1_FULL_DUPLEX	BIT(0)
74 #define MDIO_AN_RESVD_VEND_STATUS1		0xc810
77 #define MDIO_AN_TX_VEND_INT_STATUS1		0xcc00
80 #define MDIO_AN_TX_VEND_INT_STATUS2		0xcc01
81 #define MDIO_AN_TX_VEND_INT_STATUS2_MASK	BIT(0)
83 #define MDIO_AN_TX_VEND_INT_MASK2		0xd401
84 #define MDIO_AN_TX_VEND_INT_MASK2_LINK		BIT(0)
86 #define PMAPMD_RSVD_VEND_PROV			0xe400
87 #define PMAPMD_RSVD_VEND_PROV_MDI_CONF		GENMASK(1, 0)
88 #define PMAPMD_RSVD_VEND_PROV_MDI_REVERSE	BIT(0)
91 #define MDIO_AN_RX_LP_STAT1			0xe820
98 #define MDIO_AN_RX_LP_STAT4			0xe823
100 #define MDIO_AN_RX_LP_STAT4_FW_MINOR		GENMASK(7, 0)
102 #define MDIO_AN_RX_VEND_STAT3			0xe832
103 #define MDIO_AN_RX_VEND_STAT3_AFR		BIT(0)
120 	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++)  in aqr107_get_strings()
134 	if (val < 0)  in aqr107_get_stat()
137 	ret = val & GENMASK(len_l - 1, 0);  in aqr107_get_stat()
140 		if (val < 0)  in aqr107_get_stat()
143 		ret += (val & GENMASK(len_h - 1, 0)) << 16;  in aqr107_get_stat()
156 	for (i = 0; i < AQR107_SGMII_STAT_SZ; i++) {  in aqr107_get_stats()
170 	u16 val = 0;  in aqr_set_mdix()
197 	if (ret < 0)  in aqr_config_aneg()
199 	if (ret > 0)  in aqr_config_aneg()
206 	if (ret < 0)  in aqr_config_aneg()
208 	if (ret > 0)  in aqr_config_aneg()
214 	reg = 0;  in aqr_config_aneg()
237 	if (ret < 0)  in aqr_config_aneg()
239 	if (ret > 0)  in aqr_config_aneg()
253 		if (err < 0)  in aqr_config_intr()
258 			    en ? MDIO_AN_TX_VEND_INT_MASK2_LINK : 0);  in aqr_config_intr()
259 	if (err < 0)  in aqr_config_intr()
263 			    en ? VEND1_GLOBAL_INT_STD_MASK_ALL : 0);  in aqr_config_intr()
264 	if (err < 0)  in aqr_config_intr()
269 			    VEND1_GLOBAL_INT_VEND_MASK_AN : 0);  in aqr_config_intr()
270 	if (err < 0)  in aqr_config_intr()
276 		if (err < 0)  in aqr_config_intr()
280 	return 0;  in aqr_config_intr()
289 	if (irq_status < 0) {  in aqr_handle_interrupt()
308 		if (val < 0)  in aqr_read_status()
320 	if (val < 0)  in aqr_read_status()
324 		if (val < 0)  in aqr_read_status()
358 	return 0;  in aqr105_get_features()
364 	int ctrl10 = 0;  in aqr105_setup_forced()
395 	if (ret < 0)  in aqr105_setup_forced()
398 	if (ret < 0)  in aqr105_setup_forced()
401 	if (ret < 0)  in aqr105_setup_forced()
407 	if (ret < 0)  in aqr105_setup_forced()
420 	if (ret < 0)  in aqr105_config_aneg()
422 	if (ret > 0)  in aqr105_config_aneg()
429 	if (ret < 0)  in aqr105_config_aneg()
431 	if (ret > 0)  in aqr105_config_aneg()
437 	reg = 0;  in aqr105_config_aneg()
460 	if (ret < 0)  in aqr105_config_aneg()
462 	if (ret > 0)  in aqr105_config_aneg()
473 	if (val < 0)  in aqr105_read_rate()
504 	return 0;  in aqr105_read_rate()
517 		return 0;  in aqr105_read_status()
575 	if (val < 0)  in aqr107_read_rate()
610 		return 0;  in aqr107_read_rate()
614 	if (val < 0)  in aqr107_read_rate()
623 	return 0;  in aqr107_read_rate()
635 		return 0;  in aqr107_read_status()
692 	if (val < 0)  in aqr107_get_downshift()
700 	return 0;  in aqr107_get_downshift()
705 	int val = 0;  in aqr107_set_downshift()
756 	ret = read_poll_timeout(phy_read_mmd, val, val != 0,  in aqr_wait_reset_complete()
760 	if (val < 0) {  in aqr_wait_reset_complete()
775 	if (val < 0)  in aqr107_chip_info()
782 	if (val < 0)  in aqr107_chip_info()
802 		return 0;  in aqr107_config_mdi()
861 	return 0;  in aqr107_config_init()
891 	if (val < 0 || !(val & MDIO_AN_RX_LP_STAT1_AQ_PHY))  in aqr107_link_change_notify()
898 	if (val < 0)  in aqr107_link_change_notify()
905 	if (val < 0)  in aqr107_link_change_notify()
917 	if (val < 0)  in aqr107_link_change_notify()
946 	return 0;  in aqr107_wait_processor_intensive_op()
1003 	for (i = 0; i < ARRAY_SIZE(aqr_global_cfg_regs); i++) {  in aqr107_fill_interface_modes()
1006 		if (val < 0)  in aqr107_fill_interface_modes()
1043 	return 0;  in aqr107_fill_interface_modes()
1057 					VEND1_GLOBAL_CFG_100M, val, val != 0,  in aqr113c_fill_interface_modes()
1075 	return 0;  in aqr115c_get_features()
1087 	return 0;  in aqr111_get_features()
1095 	if (ret < 0)  in aqr113c_config_init()