31 	(offs[slice].ft1_slot_base + FT1_SLOT_SIZE * (n) + (reg))
66 	(offs[slice].ft3_slot_base + FT3_SLOT_SIZE * (n) + (reg))
74 #define RX_CLASS_N_REG(slice, n, reg)	\  argument
75 	(offs[slice].rx_class_base + RX_CLASS_EN_SIZE * (n) + (reg))
80 #define RX_CLASS_GATES_N_REG(slice, n)	\  argument
81 	(offs[slice].rx_class_gates_base + RX_CLASS_GATES_SIZE * (n))
205 static void rx_class_ft1_set_start_len(struct regmap *miig_rt, int slice,  in rx_class_ft1_set_start_len()  argument
210 	offset = offs[slice].ft1_start_len;  in rx_class_ft1_set_start_len()
215 static void rx_class_ft1_set_da(struct regmap *miig_rt, int slice,  in rx_class_ft1_set_da()  argument
220 	offset = FT1_N_REG(slice, n, FT1_DA0);  in rx_class_ft1_set_da()
223 	offset = FT1_N_REG(slice, n, FT1_DA1);  in rx_class_ft1_set_da()
227 static void rx_class_ft1_set_da_mask(struct regmap *miig_rt, int slice,  in rx_class_ft1_set_da_mask()  argument
232 	offset = FT1_N_REG(slice, n, FT1_DA0_MASK);  in rx_class_ft1_set_da_mask()
235 	offset = FT1_N_REG(slice, n, FT1_DA1_MASK);  in rx_class_ft1_set_da_mask()
239 static void rx_class_ft1_cfg_set_type(struct regmap *miig_rt, int slice, int n,  in rx_class_ft1_cfg_set_type()  argument
244 	offset = offs[slice].ft1_cfg;  in rx_class_ft1_cfg_set_type()
249 static void rx_class_sel_set_type(struct regmap *miig_rt, int slice, int n,  in rx_class_sel_set_type()  argument
254 	offset = offs[slice].rx_class_cfg1;  in rx_class_sel_set_type()
259 static void rx_class_set_and(struct regmap *miig_rt, int slice, int n,  in rx_class_set_and()  argument
264 	offset = RX_CLASS_N_REG(slice, n, RX_CLASS_AND_EN);  in rx_class_set_and()
268 static void rx_class_set_or(struct regmap *miig_rt, int slice, int n,  in rx_class_set_or()  argument
273 	offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN);  in rx_class_set_or()
277 static u32 rx_class_get_or(struct regmap *miig_rt, int slice, int n)  in rx_class_get_or()  argument
281 	offset = RX_CLASS_N_REG(slice, n, RX_CLASS_OR_EN);  in rx_class_get_or()
295 void icssg_class_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac)  in icssg_class_set_mac_addr()  argument
297 	regmap_write(miig_rt, offs[slice].mac0, (u32)(mac[0] | mac[1] << 8 |  in icssg_class_set_mac_addr()
299 	regmap_write(miig_rt, offs[slice].mac1, (u32)(mac[4] | mac[5] << 8));  in icssg_class_set_mac_addr()
303 static void icssg_class_ft1_add_mcast(struct regmap *miig_rt, int slice,  in icssg_class_ft1_add_mcast()  argument
311 	rx_class_ft1_set_da(miig_rt, slice, slot, addr);  in icssg_class_ft1_add_mcast()
312 	rx_class_ft1_set_da_mask(miig_rt, slice, slot, mask);  in icssg_class_ft1_add_mcast()
313 	rx_class_ft1_cfg_set_type(miig_rt, slice, slot, FT1_CFG_TYPE_EQ);  in icssg_class_ft1_add_mcast()
317 		val = rx_class_get_or(miig_rt, slice, i);  in icssg_class_ft1_add_mcast()
319 		rx_class_set_or(miig_rt, slice, i, val);  in icssg_class_ft1_add_mcast()
324 void icssg_class_disable(struct regmap *miig_rt, int slice)  in icssg_class_disable()  argument
335 		rx_class_set_and(miig_rt, slice, n, 0);  in icssg_class_disable()
337 		rx_class_set_or(miig_rt, slice, n, 0);  in icssg_class_disable()
340 		rx_class_sel_set_type(miig_rt, slice, n, RX_CLASS_SEL_TYPE_OR);  in icssg_class_disable()
343 		offset = RX_CLASS_GATES_N_REG(slice, n);  in icssg_class_disable()
356 		rx_class_ft1_cfg_set_type(miig_rt, slice, n,  in icssg_class_disable()
358 		rx_class_ft1_set_da(miig_rt, slice, n, addr);  in icssg_class_disable()
359 		rx_class_ft1_set_da_mask(miig_rt, slice, n, addr);  in icssg_class_disable()
363 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);  in icssg_class_disable()
367 void icssg_class_default(struct regmap *miig_rt, int slice, bool allmulti,  in icssg_class_default()  argument
375 	icssg_class_disable(miig_rt, slice);  in icssg_class_default()
386 		rx_class_set_or(miig_rt, slice, n, data);  in icssg_class_default()
389 		rx_class_sel_set_type(miig_rt, slice, n,  in icssg_class_default()
394 	regmap_write(miig_rt, offs[slice].rx_class_cfg2, 0);  in icssg_class_default()
398 void icssg_class_promiscuous_sr1(struct regmap *miig_rt, int slice)  in icssg_class_promiscuous_sr1()  argument
404 	icssg_class_disable(miig_rt, slice);  in icssg_class_promiscuous_sr1()
409 		offset = RX_CLASS_GATES_N_REG(slice, n);  in icssg_class_promiscuous_sr1()
417 void icssg_class_add_mcast_sr1(struct regmap *miig_rt, int slice,  in icssg_class_add_mcast_sr1()  argument
424 	rx_class_ft1_set_start_len(miig_rt, slice, 0, 6);  in icssg_class_add_mcast_sr1()
430 	icssg_class_ft1_add_mcast(miig_rt, slice, 0,  in icssg_class_add_mcast_sr1()
432 	icssg_class_ft1_add_mcast(miig_rt, slice, 1,  in icssg_class_add_mcast_sr1()
447 			icssg_class_default(miig_rt, slice, 1, true);  in icssg_class_add_mcast_sr1()
452 		icssg_class_ft1_add_mcast(miig_rt, slice, slot,  in icssg_class_add_mcast_sr1()
460 void icssg_ft1_set_mac_addr(struct regmap *miig_rt, int slice, u8 *mac_addr)  in icssg_ft1_set_mac_addr()  argument
464 	rx_class_ft1_set_start_len(miig_rt, slice, ETH_ALEN, ETH_ALEN);  in icssg_ft1_set_mac_addr()
465 	rx_class_ft1_set_da(miig_rt, slice, 0, mac_addr);  in icssg_ft1_set_mac_addr()
466 	rx_class_ft1_set_da_mask(miig_rt, slice, 0, mask_addr);  in icssg_ft1_set_mac_addr()
467 	rx_class_ft1_cfg_set_type(miig_rt, slice, 0, FT1_CFG_TYPE_EQ);  in icssg_ft1_set_mac_addr()