stmicro/stmmac/dwmac4.h

1 /* SPDX-License-Identifier: GPL-2.0-only */
133 /* TX Queues Priorities */
137 /* MAC Flow Control TX */
199 /* MAC config */
220 /* MAC extended config */
277 /* MAC extended config 1 */
312 /*  MTL registers */
341 		addr = addrs->mtl_chan + (x * addrs->mtl_chan_offset);  in mtl_chanx_base_addr()
394 /* MTL ETS Control register */
404 		addr = addrs->mtl_ets_ctrl + (x * addrs->mtl_ets_ctrl_offset);  in mtl_etsx_ctrl_base_addr()
414 /* MTL Queue Quantum Weight */
424 		addr = addrs->mtl_txq_weight + (x * addrs->mtl_txq_weight_offset);  in mtl_txqx_weight_base_addr()
433 /* MTL sendSlopeCredit register */
443 		addr = addrs->mtl_send_slp_cred + (x * addrs->mtl_send_slp_cred_offset);  in mtl_send_slp_credx_base_addr()
452 /* MTL hiCredit register */
462 		addr = addrs->mtl_high_cred + (x * addrs->mtl_high_cred_offset);  in mtl_high_credx_base_addr()
471 /* MTL loCredit register */
481 		addr = addrs->mtl_low_cred + (x * addrs->mtl_low_cred_offset);  in mtl_low_credx_base_addr()
490 /*  MTL debug */
495 /* MTL debug: Tx FIFO Read Controller Status */
519 /*  MTL interrupt */
531 /*  MTL debug */
536 /* MTL debug: Tx FIFO Read Controller Status */