Lines Matching +full:mixed +full:- +full:burst
1 /* SPDX-License-Identifier: GPL-2.0-only */
3 Copyright (C) 2007-2009 STMicroelectronics Ltd
23 #define GMAC_WAKEUP_FILTER 0x00000028 /* Wake-up Frame Filter */
68 #define GMAC_ADDR_HIGH(reg) ((reg > 15) ? 0x00000800 + (reg - 16) * 8 : \
70 #define GMAC_ADDR_LOW(reg) ((reg > 15) ? 0x00000804 + (reg - 16) * 8 : \
97 #define GMAC_CONTROL_BE 0x00200000 /* Frame Burst Enable */
108 #define GMAC_CONTROL_LM 0x00001000 /* Loop-back mode */
166 #define GMAC_DEBUG_RXFSTS_MASK GENMASK(9, 8) /* MTL Rx FIFO Fill-level */
185 /*--- DMA BLOCK defines ---*/
190 /* Programmable burst length (passed thorugh platform)*/
191 #define DMA_BUS_MODE_PBL_MASK 0x00003f00 /* Programmable Burst Len */
201 #define DMA_BUS_MODE_FB 0x00010000 /* Fixed burst */
202 #define DMA_BUS_MODE_MB 0x04000000 /* Mixed burst */
203 #define DMA_BUS_MODE_RPBL_MASK 0x007e0000 /* Rx-Programmable Burst Len */
215 #define DMA_BUS_FB 0x00010000 /* Fixed Burst */
267 * 0,00 - Full minus 1KB (only valid when rxfifo >= 4KB and EFC enabled)
268 * 0,01 - Full minus 2KB (only valid when rxfifo >= 4KB and EFC enabled)
269 * 0,10 - Full minus 3KB (only valid when rxfifo >= 4KB and EFC enabled)
270 * 0,11 - Full minus 4KB (only valid when rxfifo > 4KB and EFC enabled)
271 * 1,00 - Full minus 5KB (only valid when rxfifo > 8KB and EFC enabled)
272 * 1,01 - Full minus 6KB (only valid when rxfifo > 8KB and EFC enabled)
273 * 1,10 - Full minus 7KB (only valid when rxfifo > 8KB and EFC enabled)
274 * 1,11 - Reserved