Lines Matching +full:speed +full:- +full:bins
1 // SPDX-License-Identifier: GPL-2.0
5 #include <linux/clk-provider.h>
9 #include "dwmac-intel.h"
98 int func = PCI_FUNC(pdev->devfn); in stmmac_pci_find_phy_addr()
103 return -ENODEV; in stmmac_pci_find_phy_addr()
105 dmi_data = dmi_id->driver_data; in stmmac_pci_find_phy_addr()
106 func_data = dmi_data->func; in stmmac_pci_find_phy_addr()
108 for (n = 0; n < dmi_data->nfuncs; n++, func_data++) in stmmac_pci_find_phy_addr()
109 if (func_data->func == func) in stmmac_pci_find_phy_addr()
110 return func_data->phy_addr; in stmmac_pci_find_phy_addr()
112 return -ENODEV; in stmmac_pci_find_phy_addr()
122 val_rd = mdiobus_read(priv->mii, phyaddr, phyreg); in serdes_status_poll()
126 } while (--retries); in serdes_status_poll()
128 return -ETIMEDOUT; in serdes_status_poll()
138 if (!intel_priv->mdio_adhoc_addr) in intel_serdes_powerup()
141 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_serdes_powerup()
144 data = mdiobus_read(priv->mii, serdes_phy_addr, in intel_serdes_powerup()
150 if (priv->plat->phy_interface == PHY_INTERFACE_MODE_2500BASEX) in intel_serdes_powerup()
157 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
160 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
162 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
171 dev_err(priv->device, "Serdes PLL clk request timeout\n"); in intel_serdes_powerup()
176 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
178 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
187 dev_err(priv->device, "Serdes assert lane reset timeout\n"); in intel_serdes_powerup()
192 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerup()
197 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerup()
206 dev_err(priv->device, "Serdes power state P0 timeout.\n"); in intel_serdes_powerup()
210 /* PSE only - ungate SGMII PHY Rx Clock */ in intel_serdes_powerup()
211 if (intel_priv->is_pse) in intel_serdes_powerup()
212 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, in intel_serdes_powerup()
225 if (!intel_priv->mdio_adhoc_addr) in intel_serdes_powerdown()
228 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_serdes_powerdown()
230 /* PSE only - gate SGMII PHY Rx Clock */ in intel_serdes_powerdown()
231 if (intel_priv->is_pse) in intel_serdes_powerdown()
232 mdiobus_modify(priv->mii, serdes_phy_addr, SERDES_GCR0, in intel_serdes_powerdown()
236 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
241 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
250 dev_err(priv->device, "Serdes power state P3 timeout\n"); in intel_serdes_powerdown()
254 /* de-assert clk_req */ in intel_serdes_powerdown()
255 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
257 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
259 /* check for clk_ack de-assert */ in intel_serdes_powerdown()
266 dev_err(priv->device, "Serdes PLL clk de-assert timeout\n"); in intel_serdes_powerdown()
270 /* de-assert lane reset */ in intel_serdes_powerdown()
271 data = mdiobus_read(priv->mii, serdes_phy_addr, SERDES_GCR0); in intel_serdes_powerdown()
273 mdiobus_write(priv->mii, serdes_phy_addr, SERDES_GCR0, data); in intel_serdes_powerdown()
275 /* check for de-assert lane reset reflection */ in intel_serdes_powerdown()
282 dev_err(priv->device, "Serdes de-assert lane reset timeout\n"); in intel_serdes_powerdown()
294 serdes_phy_addr = intel_priv->mdio_adhoc_addr; in intel_speed_mode_2500()
296 /* Determine the link speed mode: 2.5Gbps/1Gbps */ in intel_speed_mode_2500()
297 data = mdiobus_read(priv->mii, serdes_phy_addr, in intel_speed_mode_2500()
302 dev_info(priv->device, "Link Speed Mode: 2.5Gbps\n"); in intel_speed_mode_2500()
303 priv->plat->max_speed = 2500; in intel_speed_mode_2500()
304 priv->plat->phy_interface = PHY_INTERFACE_MODE_2500BASEX; in intel_speed_mode_2500()
305 priv->plat->mdio_bus_data->default_an_inband = false; in intel_speed_mode_2500()
307 priv->plat->max_speed = 1000; in intel_speed_mode_2500()
319 intel_priv = (struct intel_priv_data *)priv->plat->bsp_priv; in intel_mgbe_ptp_clk_freq_config()
321 gpio_value = readl(priv->ioaddr + GMAC_GPIO_STATUS); in intel_mgbe_ptp_clk_freq_config()
323 if (intel_priv->is_pse) { in intel_mgbe_ptp_clk_freq_config()
333 writel(gpio_value, priv->ioaddr + GMAC_GPIO_STATUS); in intel_mgbe_ptp_clk_freq_config()
354 return (readl(priv->ioaddr + GMAC_INT_STATUS) & GMAC_INT_TSIE); in stmmac_cross_ts_isr()
364 void __iomem *ptpaddr = priv->ptpaddr; in intel_crosststamp()
365 void __iomem *ioaddr = priv->hw->pcsr; in intel_crosststamp()
375 return -EOPNOTSUPP; in intel_crosststamp()
377 intel_priv = priv->plat->bsp_priv; in intel_crosststamp()
382 if (priv->plat->flags & STMMAC_FLAG_EXT_SNAPSHOT_EN) in intel_crosststamp()
383 return -EBUSY; in intel_crosststamp()
385 priv->plat->flags |= STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
387 mutex_lock(&priv->aux_ts_lock); in intel_crosststamp()
391 switch (priv->plat->int_snapshot_num) { in intel_crosststamp()
405 mutex_unlock(&priv->aux_ts_lock); in intel_crosststamp()
406 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
407 return -EINVAL; in intel_crosststamp()
416 mutex_unlock(&priv->aux_ts_lock); in intel_crosststamp()
428 /* Time sync done Indication - Interrupt method */ in intel_crosststamp()
429 if (!wait_event_interruptible_timeout(priv->tstamp_busy_wait, in intel_crosststamp()
432 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
433 return -ETIMEDOUT; in intel_crosststamp()
442 read_lock_irqsave(&priv->ptp_lock, flags); in intel_crosststamp()
445 read_unlock_irqrestore(&priv->ptp_lock, flags); in intel_crosststamp()
446 get_arttime(priv->mii, intel_priv->mdio_adhoc_addr, &art_time); in intel_crosststamp()
447 system->cycles = art_time; in intel_crosststamp()
450 system->cycles *= intel_priv->crossts_adj; in intel_crosststamp()
451 system->cs_id = CSID_X86_ART; in intel_crosststamp()
452 priv->plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_crosststamp()
468 intel_priv->crossts_adj = art_freq; in intel_mgbe_pse_crossts_adj()
489 netdev_info(priv->dev, "Failed to read from PMC.\n"); in intel_tsn_lane_is_available()
493 for (j = 0; j <= intel_priv->max_tsn_lane_regs; j++) in intel_tsn_lane_is_available()
495 (4 * (intel_priv->tsn_lane_regs[j] % 8)) & in intel_tsn_lane_is_available()
500 return -EINVAL; in intel_tsn_lane_is_available()
537 netdev_info(priv->dev, "No TSN lane available to set the registers.\n"); in intel_mac_finish()
542 regs = intel_priv->pid_2p5g.regs; in intel_mac_finish()
543 max_regs = intel_priv->pid_2p5g.num_regs; in intel_mac_finish()
545 regs = intel_priv->pid_1g.regs; in intel_mac_finish()
546 max_regs = intel_priv->pid_1g.num_regs; in intel_mac_finish()
553 priv->plat->phy_interface = interface; in intel_mac_finish()
563 plat->clk_csr = 2; /* clk_csr_i = 20-35MHz & MDC = clk_csr_i/16 */ in common_default_data()
564 plat->has_gmac = 1; in common_default_data()
565 plat->force_sf_dma_mode = 1; in common_default_data()
567 plat->mdio_bus_data->needs_reset = true; in common_default_data()
569 /* Set default value for multicast hash bins */ in common_default_data()
570 plat->multicast_filter_bins = HASH_TABLE_SIZE; in common_default_data()
573 plat->unicast_filter_entries = 1; in common_default_data()
576 plat->maxmtu = JUMBO_LEN; in common_default_data()
579 plat->tx_queues_to_use = 1; in common_default_data()
580 plat->rx_queues_to_use = 1; in common_default_data()
583 plat->tx_queues_cfg[0].use_prio = false; in common_default_data()
584 plat->rx_queues_cfg[0].use_prio = false; in common_default_data()
587 plat->rx_queues_cfg[0].pkt_route = 0x0; in common_default_data()
593 /* plat->mdio_bus_data->has_xpcs has been set true, so there in intel_mgbe_select_pcs()
597 return xpcs_to_phylink_pcs(priv->hw->xpcs); in intel_mgbe_select_pcs()
608 plat->pdev = pdev; in intel_mgbe_common_data()
609 plat->phy_addr = -1; in intel_mgbe_common_data()
610 plat->clk_csr = 5; in intel_mgbe_common_data()
611 plat->has_gmac = 0; in intel_mgbe_common_data()
612 plat->has_gmac4 = 1; in intel_mgbe_common_data()
613 plat->force_sf_dma_mode = 0; in intel_mgbe_common_data()
614 plat->flags |= (STMMAC_FLAG_TSO_EN | STMMAC_FLAG_SPH_DISABLE); in intel_mgbe_common_data()
625 plat->mult_fact_100ns = 1; in intel_mgbe_common_data()
627 plat->rx_sched_algorithm = MTL_RX_ALGORITHM_SP; in intel_mgbe_common_data()
629 for (i = 0; i < plat->rx_queues_to_use; i++) { in intel_mgbe_common_data()
630 plat->rx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
631 plat->rx_queues_cfg[i].chan = i; in intel_mgbe_common_data()
634 plat->rx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
637 plat->rx_queues_cfg[i].pkt_route = 0x0; in intel_mgbe_common_data()
640 for (i = 0; i < plat->tx_queues_to_use; i++) { in intel_mgbe_common_data()
641 plat->tx_queues_cfg[i].mode_to_use = MTL_QUEUE_DCB; in intel_mgbe_common_data()
644 plat->tx_queues_cfg[i].use_prio = false; in intel_mgbe_common_data()
647 plat->tx_queues_cfg[i].tbs_en = 1; in intel_mgbe_common_data()
651 plat->tx_fifo_size = plat->tx_queues_to_use * 4096; in intel_mgbe_common_data()
652 plat->rx_fifo_size = plat->rx_queues_to_use * 4096; in intel_mgbe_common_data()
654 plat->tx_sched_algorithm = MTL_TX_ALGORITHM_WRR; in intel_mgbe_common_data()
655 plat->tx_queues_cfg[0].weight = 0x09; in intel_mgbe_common_data()
656 plat->tx_queues_cfg[1].weight = 0x0A; in intel_mgbe_common_data()
657 plat->tx_queues_cfg[2].weight = 0x0B; in intel_mgbe_common_data()
658 plat->tx_queues_cfg[3].weight = 0x0C; in intel_mgbe_common_data()
659 plat->tx_queues_cfg[4].weight = 0x0D; in intel_mgbe_common_data()
660 plat->tx_queues_cfg[5].weight = 0x0E; in intel_mgbe_common_data()
661 plat->tx_queues_cfg[6].weight = 0x0F; in intel_mgbe_common_data()
662 plat->tx_queues_cfg[7].weight = 0x10; in intel_mgbe_common_data()
664 plat->dma_cfg->pbl = 32; in intel_mgbe_common_data()
665 plat->dma_cfg->pblx8 = true; in intel_mgbe_common_data()
666 plat->dma_cfg->fixed_burst = 0; in intel_mgbe_common_data()
667 plat->dma_cfg->mixed_burst = 0; in intel_mgbe_common_data()
668 plat->dma_cfg->aal = 0; in intel_mgbe_common_data()
669 plat->dma_cfg->dche = true; in intel_mgbe_common_data()
671 plat->axi = devm_kzalloc(&pdev->dev, sizeof(*plat->axi), in intel_mgbe_common_data()
673 if (!plat->axi) in intel_mgbe_common_data()
674 return -ENOMEM; in intel_mgbe_common_data()
676 plat->axi->axi_lpi_en = 0; in intel_mgbe_common_data()
677 plat->axi->axi_xit_frm = 0; in intel_mgbe_common_data()
678 plat->axi->axi_wr_osr_lmt = 1; in intel_mgbe_common_data()
679 plat->axi->axi_rd_osr_lmt = 1; in intel_mgbe_common_data()
680 plat->axi->axi_blen[0] = 4; in intel_mgbe_common_data()
681 plat->axi->axi_blen[1] = 8; in intel_mgbe_common_data()
682 plat->axi->axi_blen[2] = 16; in intel_mgbe_common_data()
684 plat->ptp_max_adj = plat->clk_ptp_rate; in intel_mgbe_common_data()
685 plat->eee_usecs_rate = plat->clk_ptp_rate; in intel_mgbe_common_data()
688 sprintf(clk_name, "%s-%s", "stmmac", pci_name(pdev)); in intel_mgbe_common_data()
690 plat->stmmac_clk = clk_register_fixed_rate(&pdev->dev, in intel_mgbe_common_data()
692 plat->clk_ptp_rate); in intel_mgbe_common_data()
694 if (IS_ERR(plat->stmmac_clk)) { in intel_mgbe_common_data()
695 dev_warn(&pdev->dev, "Fail to register stmmac-clk\n"); in intel_mgbe_common_data()
696 plat->stmmac_clk = NULL; in intel_mgbe_common_data()
699 ret = clk_prepare_enable(plat->stmmac_clk); in intel_mgbe_common_data()
701 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_mgbe_common_data()
705 plat->ptp_clk_freq_config = intel_mgbe_ptp_clk_freq_config; in intel_mgbe_common_data()
707 /* Set default value for multicast hash bins */ in intel_mgbe_common_data()
708 plat->multicast_filter_bins = HASH_TABLE_SIZE; in intel_mgbe_common_data()
711 plat->unicast_filter_entries = 1; in intel_mgbe_common_data()
714 plat->maxmtu = JUMBO_LEN; in intel_mgbe_common_data()
716 plat->flags |= STMMAC_FLAG_VLAN_FAIL_Q_EN; in intel_mgbe_common_data()
719 plat->vlan_fail_q = plat->rx_queues_to_use - 1; in intel_mgbe_common_data()
721 /* For fixed-link setup, we allow phy-mode setting */ in intel_mgbe_common_data()
722 fwnode = dev_fwnode(&pdev->dev); in intel_mgbe_common_data()
726 /* "phy-mode" setting is optional. If it is set, in intel_mgbe_common_data()
727 * we allow either sgmii or 1000base-x for now. in intel_mgbe_common_data()
733 plat->phy_interface = phy_mode; in intel_mgbe_common_data()
735 dev_warn(&pdev->dev, "Invalid phy-mode\n"); in intel_mgbe_common_data()
739 /* Intel mgbe SGMII interface uses pcs-xcps */ in intel_mgbe_common_data()
740 if (plat->phy_interface == PHY_INTERFACE_MODE_SGMII || in intel_mgbe_common_data()
741 plat->phy_interface == PHY_INTERFACE_MODE_1000BASEX) { in intel_mgbe_common_data()
742 plat->mdio_bus_data->pcs_mask = BIT(INTEL_MGBE_XPCS_ADDR); in intel_mgbe_common_data()
743 plat->mdio_bus_data->default_an_inband = true; in intel_mgbe_common_data()
744 plat->select_pcs = intel_mgbe_select_pcs; in intel_mgbe_common_data()
747 /* Ensure mdio bus scan skips intel serdes and pcs-xpcs */ in intel_mgbe_common_data()
748 plat->mdio_bus_data->phy_mask = 1 << INTEL_MGBE_ADHOC_ADDR; in intel_mgbe_common_data()
749 plat->mdio_bus_data->phy_mask |= 1 << INTEL_MGBE_XPCS_ADDR; in intel_mgbe_common_data()
751 plat->int_snapshot_num = AUX_SNAPSHOT1; in intel_mgbe_common_data()
753 plat->crosststamp = intel_crosststamp; in intel_mgbe_common_data()
754 plat->flags &= ~STMMAC_FLAG_INT_SNAPSHOT_EN; in intel_mgbe_common_data()
757 plat->msi_mac_vec = 29; in intel_mgbe_common_data()
758 plat->msi_lpi_vec = 28; in intel_mgbe_common_data()
759 plat->msi_sfty_ce_vec = 27; in intel_mgbe_common_data()
760 plat->msi_sfty_ue_vec = 26; in intel_mgbe_common_data()
761 plat->msi_rx_base_vec = 0; in intel_mgbe_common_data()
762 plat->msi_tx_base_vec = 1; in intel_mgbe_common_data()
770 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_common_data()
772 plat->rx_queues_to_use = 8; in ehl_common_data()
773 plat->tx_queues_to_use = 8; in ehl_common_data()
774 plat->flags |= STMMAC_FLAG_USE_PHY_WOL; in ehl_common_data()
775 plat->flags |= STMMAC_FLAG_HWTSTAMP_CORRECT_LATENCY; in ehl_common_data()
777 plat->safety_feat_cfg->tsoee = 1; in ehl_common_data()
778 plat->safety_feat_cfg->mrxpee = 1; in ehl_common_data()
779 plat->safety_feat_cfg->mestee = 1; in ehl_common_data()
780 plat->safety_feat_cfg->mrxee = 1; in ehl_common_data()
781 plat->safety_feat_cfg->mtxee = 1; in ehl_common_data()
782 plat->safety_feat_cfg->epsi = 0; in ehl_common_data()
783 plat->safety_feat_cfg->edpp = 0; in ehl_common_data()
784 plat->safety_feat_cfg->prtyen = 0; in ehl_common_data()
785 plat->safety_feat_cfg->tmouten = 0; in ehl_common_data()
787 intel_priv->tsn_lane_regs = ehl_tsn_lane_regs; in ehl_common_data()
788 intel_priv->max_tsn_lane_regs = ARRAY_SIZE(ehl_tsn_lane_regs); in ehl_common_data()
796 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_sgmii_data()
798 plat->bus_id = 1; in ehl_sgmii_data()
799 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_sgmii_data()
800 plat->serdes_powerup = intel_serdes_powerup; in ehl_sgmii_data()
801 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_sgmii_data()
802 plat->mac_finish = intel_mac_finish; in ehl_sgmii_data()
803 plat->clk_ptp_rate = 204800000; in ehl_sgmii_data()
805 intel_priv->pid_1g.regs = pid_modphy3_1g_regs; in ehl_sgmii_data()
806 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy3_1g_regs); in ehl_sgmii_data()
807 intel_priv->pid_2p5g.regs = pid_modphy3_2p5g_regs; in ehl_sgmii_data()
808 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy3_2p5g_regs); in ehl_sgmii_data()
820 plat->bus_id = 1; in ehl_rgmii_data()
821 plat->phy_interface = PHY_INTERFACE_MODE_RGMII; in ehl_rgmii_data()
823 plat->clk_ptp_rate = 204800000; in ehl_rgmii_data()
835 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse0_common_data()
837 intel_priv->is_pse = true; in ehl_pse0_common_data()
838 plat->bus_id = 2; in ehl_pse0_common_data()
839 plat->host_dma_width = 32; in ehl_pse0_common_data()
841 plat->clk_ptp_rate = 200000000; in ehl_pse0_common_data()
851 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse0_rgmii1g_data()
862 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse0_sgmii1g_data()
864 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse0_sgmii1g_data()
865 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse0_sgmii1g_data()
866 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse0_sgmii1g_data()
867 plat->mac_finish = intel_mac_finish; in ehl_pse0_sgmii1g_data()
869 intel_priv->pid_1g.regs = pid_modphy1_1g_regs; in ehl_pse0_sgmii1g_data()
870 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); in ehl_pse0_sgmii1g_data()
871 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; in ehl_pse0_sgmii1g_data()
872 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); in ehl_pse0_sgmii1g_data()
884 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse1_common_data()
886 intel_priv->is_pse = true; in ehl_pse1_common_data()
887 plat->bus_id = 3; in ehl_pse1_common_data()
888 plat->host_dma_width = 32; in ehl_pse1_common_data()
890 plat->clk_ptp_rate = 200000000; in ehl_pse1_common_data()
900 plat->phy_interface = PHY_INTERFACE_MODE_RGMII_ID; in ehl_pse1_rgmii1g_data()
911 struct intel_priv_data *intel_priv = plat->bsp_priv; in ehl_pse1_sgmii1g_data()
913 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in ehl_pse1_sgmii1g_data()
914 plat->serdes_powerup = intel_serdes_powerup; in ehl_pse1_sgmii1g_data()
915 plat->serdes_powerdown = intel_serdes_powerdown; in ehl_pse1_sgmii1g_data()
916 plat->mac_finish = intel_mac_finish; in ehl_pse1_sgmii1g_data()
918 intel_priv->pid_1g.regs = pid_modphy1_1g_regs; in ehl_pse1_sgmii1g_data()
919 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); in ehl_pse1_sgmii1g_data()
920 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; in ehl_pse1_sgmii1g_data()
921 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); in ehl_pse1_sgmii1g_data()
933 plat->rx_queues_to_use = 6; in tgl_common_data()
934 plat->tx_queues_to_use = 4; in tgl_common_data()
935 plat->clk_ptp_rate = 204800000; in tgl_common_data()
936 plat->speed_mode_2500 = intel_speed_mode_2500; in tgl_common_data()
938 plat->safety_feat_cfg->tsoee = 1; in tgl_common_data()
939 plat->safety_feat_cfg->mrxpee = 0; in tgl_common_data()
940 plat->safety_feat_cfg->mestee = 1; in tgl_common_data()
941 plat->safety_feat_cfg->mrxee = 1; in tgl_common_data()
942 plat->safety_feat_cfg->mtxee = 1; in tgl_common_data()
943 plat->safety_feat_cfg->epsi = 0; in tgl_common_data()
944 plat->safety_feat_cfg->edpp = 0; in tgl_common_data()
945 plat->safety_feat_cfg->prtyen = 0; in tgl_common_data()
946 plat->safety_feat_cfg->tmouten = 0; in tgl_common_data()
954 plat->bus_id = 1; in tgl_sgmii_phy0_data()
955 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_phy0_data()
956 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_phy0_data()
957 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_phy0_data()
968 plat->bus_id = 2; in tgl_sgmii_phy1_data()
969 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in tgl_sgmii_phy1_data()
970 plat->serdes_powerup = intel_serdes_powerup; in tgl_sgmii_phy1_data()
971 plat->serdes_powerdown = intel_serdes_powerdown; in tgl_sgmii_phy1_data()
982 plat->bus_id = 1; in adls_sgmii_phy0_data()
983 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adls_sgmii_phy0_data()
997 plat->bus_id = 2; in adls_sgmii_phy1_data()
998 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adls_sgmii_phy1_data()
1012 struct intel_priv_data *intel_priv = plat->bsp_priv; in adln_common_data()
1014 plat->rx_queues_to_use = 6; in adln_common_data()
1015 plat->tx_queues_to_use = 4; in adln_common_data()
1016 plat->clk_ptp_rate = 204800000; in adln_common_data()
1018 plat->safety_feat_cfg->tsoee = 1; in adln_common_data()
1019 plat->safety_feat_cfg->mrxpee = 0; in adln_common_data()
1020 plat->safety_feat_cfg->mestee = 1; in adln_common_data()
1021 plat->safety_feat_cfg->mrxee = 1; in adln_common_data()
1022 plat->safety_feat_cfg->mtxee = 1; in adln_common_data()
1023 plat->safety_feat_cfg->epsi = 0; in adln_common_data()
1024 plat->safety_feat_cfg->edpp = 0; in adln_common_data()
1025 plat->safety_feat_cfg->prtyen = 0; in adln_common_data()
1026 plat->safety_feat_cfg->tmouten = 0; in adln_common_data()
1028 intel_priv->tsn_lane_regs = adln_tsn_lane_regs; in adln_common_data()
1029 intel_priv->max_tsn_lane_regs = ARRAY_SIZE(adln_tsn_lane_regs); in adln_common_data()
1037 struct intel_priv_data *intel_priv = plat->bsp_priv; in adln_sgmii_phy0_data()
1039 plat->bus_id = 1; in adln_sgmii_phy0_data()
1040 plat->phy_interface = PHY_INTERFACE_MODE_SGMII; in adln_sgmii_phy0_data()
1041 plat->serdes_powerup = intel_serdes_powerup; in adln_sgmii_phy0_data()
1042 plat->serdes_powerdown = intel_serdes_powerdown; in adln_sgmii_phy0_data()
1043 plat->mac_finish = intel_mac_finish; in adln_sgmii_phy0_data()
1045 intel_priv->pid_1g.regs = pid_modphy1_1g_regs; in adln_sgmii_phy0_data()
1046 intel_priv->pid_1g.num_regs = ARRAY_SIZE(pid_modphy1_1g_regs); in adln_sgmii_phy0_data()
1047 intel_priv->pid_2p5g.regs = pid_modphy1_2p5g_regs; in adln_sgmii_phy0_data()
1048 intel_priv->pid_2p5g.num_regs = ARRAY_SIZE(pid_modphy1_2p5g_regs); in adln_sgmii_phy0_data()
1099 * The asset tag "6ES7647-0AA00-0YA2" is only for IOT2020 which
1107 "6ES7647-0AA00-0YA2"),
1144 plat->bus_id = pci_dev_id(pdev); in quark_default_data()
1145 plat->phy_addr = ret; in quark_default_data()
1146 plat->phy_interface = PHY_INTERFACE_MODE_RMII; in quark_default_data()
1148 plat->dma_cfg->pbl = 16; in quark_default_data()
1149 plat->dma_cfg->pblx8 = true; in quark_default_data()
1150 plat->dma_cfg->fixed_burst = 1; in quark_default_data()
1168 dev_info(&pdev->dev, "%s: Single IRQ enablement failed\n", in stmmac_config_single_msi()
1173 res->irq = pci_irq_vector(pdev, 0); in stmmac_config_single_msi()
1174 res->wol_irq = res->irq; in stmmac_config_single_msi()
1175 plat->flags &= ~STMMAC_FLAG_MULTI_MSI_EN; in stmmac_config_single_msi()
1176 dev_info(&pdev->dev, "%s: Single IRQ enablement successful\n", in stmmac_config_single_msi()
1189 if (plat->msi_rx_base_vec >= STMMAC_MSI_VEC_MAX || in stmmac_config_multi_msi()
1190 plat->msi_tx_base_vec >= STMMAC_MSI_VEC_MAX) { in stmmac_config_multi_msi()
1191 dev_info(&pdev->dev, "%s: Invalid RX & TX vector defined\n", in stmmac_config_multi_msi()
1193 return -1; in stmmac_config_multi_msi()
1199 dev_info(&pdev->dev, "%s: multi MSI enablement failed\n", in stmmac_config_multi_msi()
1205 for (i = 0; i < plat->rx_queues_to_use; i++) { in stmmac_config_multi_msi()
1206 res->rx_irq[i] = pci_irq_vector(pdev, in stmmac_config_multi_msi()
1207 plat->msi_rx_base_vec + i * 2); in stmmac_config_multi_msi()
1211 for (i = 0; i < plat->tx_queues_to_use; i++) { in stmmac_config_multi_msi()
1212 res->tx_irq[i] = pci_irq_vector(pdev, in stmmac_config_multi_msi()
1213 plat->msi_tx_base_vec + i * 2); in stmmac_config_multi_msi()
1216 if (plat->msi_mac_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1217 res->irq = pci_irq_vector(pdev, plat->msi_mac_vec); in stmmac_config_multi_msi()
1218 if (plat->msi_wol_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1219 res->wol_irq = pci_irq_vector(pdev, plat->msi_wol_vec); in stmmac_config_multi_msi()
1220 if (plat->msi_lpi_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1221 res->lpi_irq = pci_irq_vector(pdev, plat->msi_lpi_vec); in stmmac_config_multi_msi()
1222 if (plat->msi_sfty_ce_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1223 res->sfty_ce_irq = pci_irq_vector(pdev, plat->msi_sfty_ce_vec); in stmmac_config_multi_msi()
1224 if (plat->msi_sfty_ue_vec < STMMAC_MSI_VEC_MAX) in stmmac_config_multi_msi()
1225 res->sfty_ue_irq = pci_irq_vector(pdev, plat->msi_sfty_ue_vec); in stmmac_config_multi_msi()
1227 plat->flags |= STMMAC_FLAG_MULTI_MSI_EN; in stmmac_config_multi_msi()
1228 dev_info(&pdev->dev, "%s: multi MSI enablement successful\n", __func__); in stmmac_config_multi_msi()
1243 * to take "ownership" of the device or an error code(-ve no) otherwise.
1248 struct stmmac_pci_info *info = (struct stmmac_pci_info *)id->driver_data; in intel_eth_pci_probe()
1254 intel_priv = devm_kzalloc(&pdev->dev, sizeof(*intel_priv), GFP_KERNEL); in intel_eth_pci_probe()
1256 return -ENOMEM; in intel_eth_pci_probe()
1258 plat = devm_kzalloc(&pdev->dev, sizeof(*plat), GFP_KERNEL); in intel_eth_pci_probe()
1260 return -ENOMEM; in intel_eth_pci_probe()
1262 plat->mdio_bus_data = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
1263 sizeof(*plat->mdio_bus_data), in intel_eth_pci_probe()
1265 if (!plat->mdio_bus_data) in intel_eth_pci_probe()
1266 return -ENOMEM; in intel_eth_pci_probe()
1268 plat->dma_cfg = devm_kzalloc(&pdev->dev, sizeof(*plat->dma_cfg), in intel_eth_pci_probe()
1270 if (!plat->dma_cfg) in intel_eth_pci_probe()
1271 return -ENOMEM; in intel_eth_pci_probe()
1273 plat->safety_feat_cfg = devm_kzalloc(&pdev->dev, in intel_eth_pci_probe()
1274 sizeof(*plat->safety_feat_cfg), in intel_eth_pci_probe()
1276 if (!plat->safety_feat_cfg) in intel_eth_pci_probe()
1277 return -ENOMEM; in intel_eth_pci_probe()
1282 dev_err(&pdev->dev, "%s: ERROR: failed to enable device\n", in intel_eth_pci_probe()
1293 plat->bsp_priv = intel_priv; in intel_eth_pci_probe()
1294 intel_priv->mdio_adhoc_addr = INTEL_MGBE_ADHOC_ADDR; in intel_eth_pci_probe()
1295 intel_priv->crossts_adj = 1; in intel_eth_pci_probe()
1301 plat->msi_mac_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1302 plat->msi_wol_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1303 plat->msi_lpi_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1304 plat->msi_sfty_ce_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1305 plat->msi_sfty_ue_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1306 plat->msi_rx_base_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1307 plat->msi_tx_base_vec = STMMAC_MSI_VEC_MAX; in intel_eth_pci_probe()
1309 ret = info->setup(pdev, plat); in intel_eth_pci_probe()
1316 if (plat->eee_usecs_rate > 0) { in intel_eth_pci_probe()
1319 tx_lpi_usec = (plat->eee_usecs_rate / 1000000) - 1; in intel_eth_pci_probe()
1327 dev_err(&pdev->dev, "%s: ERROR: failed to enable IRQ\n", in intel_eth_pci_probe()
1333 ret = stmmac_dvr_probe(&pdev->dev, plat, &res); in intel_eth_pci_probe()
1341 clk_disable_unprepare(plat->stmmac_clk); in intel_eth_pci_probe()
1342 clk_unregister_fixed_rate(plat->stmmac_clk); in intel_eth_pci_probe()
1355 struct net_device *ndev = dev_get_drvdata(&pdev->dev); in intel_eth_pci_remove()
1358 stmmac_dvr_remove(&pdev->dev); in intel_eth_pci_remove()
1360 clk_disable_unprepare(priv->plat->stmmac_clk); in intel_eth_pci_remove()
1361 clk_unregister_fixed_rate(priv->plat->stmmac_clk); in intel_eth_pci_remove()
1446 .name = "intel-eth-pci",