Lines Matching +full:tx +full:- +full:output +full:- +full:config
1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*------------------------------------------------------------------------
3 . smc91x.h - macros for SMSC's 91C9x/91C1xx single-chip Ethernet device.
21 ---------------------------------------------------------------------------*/
29 * Any 16-bit access is performed with two 8-bit accesses if the hardware
30 * can't do it directly. Most registers are 16-bit so those are mandatory.
55 #include <asm/mach-types.h>
65 #define SMC_IO_SHIFT (lp->io_shift)
96 #define SMC_IRQ_FLAGS (-1) /* from resource */
114 (lp)->cfg.pxa_u16_align4)
148 while (l-- > 0) in mcf_insw()
155 while (l-- > 0) in mcf_outsw()
177 #define SMC_IO_SHIFT (lp->io_shift)
245 /* on some platforms a u16 write must be 4-bytes aligned */
251 #define SMC_8BIT(p) ((p)->cfg.flags & SMC91X_USE_8BIT)
252 #define SMC_16BIT(p) ((p)->cfg.flags & SMC91X_USE_16BIT)
253 #define SMC_32BIT(p) ((p)->cfg.flags & SMC91X_USE_32BIT)
258 * always happening in irq context so no need to worry about races. TX is
262 #include <linux/dma-mapping.h>
267 smc_pxa_dma_insl(a, lp, r, dev->dma, p, l)
272 struct dma_async_tx_descriptor *tx; in smc_pxa_dma_inpump() local
277 dmabuf = dma_map_single(lp->device, buf, len, DMA_FROM_DEVICE); in smc_pxa_dma_inpump()
278 tx = dmaengine_prep_slave_single(lp->dma_chan, dmabuf, len, in smc_pxa_dma_inpump()
280 if (tx) { in smc_pxa_dma_inpump()
281 cookie = dmaengine_submit(tx); in smc_pxa_dma_inpump()
282 dma_async_issue_pending(lp->dma_chan); in smc_pxa_dma_inpump()
284 status = dmaengine_tx_status(lp->dma_chan, cookie, in smc_pxa_dma_inpump()
289 dmaengine_terminate_all(lp->dma_chan); in smc_pxa_dma_inpump()
291 dma_unmap_single(lp->device, dmabuf, len, DMA_FROM_DEVICE); in smc_pxa_dma_inpump()
298 struct dma_slave_config config; in smc_pxa_dma_insl() local
302 if (!lp->dma_chan) { in smc_pxa_dma_insl()
311 len--; in smc_pxa_dma_insl()
314 memset(&config, 0, sizeof(config)); in smc_pxa_dma_insl()
315 config.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in smc_pxa_dma_insl()
316 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; in smc_pxa_dma_insl()
317 config.src_addr = lp->physaddr + reg; in smc_pxa_dma_insl()
318 config.dst_addr = lp->physaddr + reg; in smc_pxa_dma_insl()
319 config.src_maxburst = 32; in smc_pxa_dma_insl()
320 config.dst_maxburst = 32; in smc_pxa_dma_insl()
321 ret = dmaengine_slave_config(lp->dma_chan, &config); in smc_pxa_dma_insl()
323 dev_err(lp->device, "dma channel configuration failed: %d\n", in smc_pxa_dma_insl()
336 smc_pxa_dma_insw(a, lp, r, dev->dma, p, l)
341 struct dma_slave_config config; in smc_pxa_dma_insw() local
345 if (!lp->dma_chan) { in smc_pxa_dma_insw()
354 len--; in smc_pxa_dma_insw()
357 memset(&config, 0, sizeof(config)); in smc_pxa_dma_insw()
358 config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; in smc_pxa_dma_insw()
359 config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES; in smc_pxa_dma_insw()
360 config.src_addr = lp->physaddr + reg; in smc_pxa_dma_insw()
361 config.dst_addr = lp->physaddr + reg; in smc_pxa_dma_insw()
362 config.src_maxburst = 32; in smc_pxa_dma_insw()
363 config.dst_maxburst = 32; in smc_pxa_dma_insw()
364 ret = dmaengine_slave_config(lp->dma_chan, &config); in smc_pxa_dma_insw()
366 dev_err(lp->device, "dma channel configuration failed: %d\n", in smc_pxa_dma_insw()
461 #define TCR_LOOP 0x0002 // Controls output pin LBK
463 #define TCR_PAD_EN 0x0080 // When 1 will pad tx frames < 64 bytes w/0
464 #define TCR_NOCRC 0x0100 // When 1 will not append CRC to tx frames
465 #define TCR_MON_CSN 0x0400 // When 1 tx monitors carrier
467 #define TCR_STP_SQET 0x1000 // When 1 stops tx if Signal Quality Error
479 #define ES_TX_SUC 0x0001 // Last TX was successful
480 #define ES_SNGL_COL 0x0002 // Single collision detected for last tx
481 #define ES_MUL_COL 0x0004 // Multiple collisions detected for last tx
482 #define ES_LTX_MULT 0x0008 // Last tx was a multicast
485 #define ES_LTXBRD 0x0040 // Last tx was a broadcast
487 #define ES_LATCOL 0x0200 // Late collision detected on last tx
492 #define ES_TXUNRN 0x8000 // Tx Underrun
526 #define RPC_DPLX 0x1000 // When 1 PHY is in Full-Duplex Mode
527 #define RPC_ANEG 0x0800 // When 1 PHY is in Auto-Negotiate Mode
556 // Default is powered-up, Internal Phy, Wait States, and pin nCNTRL=low
581 #define CTL_AUTO_RELEASE 0x0800 // When 1 tx pages are released automatically
601 #define MC_RSTTXFIFO (7<<5) // Reset the TX FIFOs
615 // TX FIFO Ports Register
618 #define TXFIFO_TEMPTY 0x80 // TX FIFO Empty
653 #define IM_TX_EMPTY_INT 0x04 // Set if the TX FIFO goes empty
669 #define MII_MSK_CRS100 0x4000 // Disables CRS100 detection during tx half dup
670 #define MII_MDOE 0x0008 // MII Output Enable
673 #define MII_MDO 0x0001 // MII Output, pin MDO
741 * These phy registers are specific to our on-board phy.
754 #define PHY_CFG1_TLVL_SHIFT 2 // Transmit Output Level Adjust
766 // PHY Status Output (and Interrupt status) Register
767 #define PHY_INT_REG 0x12 // Status Output (Interrupt Status)
776 #define PHY_INT_SPDDET 0x0080 // 1=100Base-TX mode, 0=10Base-T mode
785 * SMC91C96 ethernet config and status registers.
805 * Note: the following macros do *not* select the bank -- this must
835 * effects and use a 32-bit access.
837 * Enforce it on any 32-bit capable setup for now.
1036 __len -= 2; \
1040 if (SMC_CAN_USE_DATACS && lp->datacs) \
1041 __ioaddr = lp->datacs; \
1065 * Back both source (on-chip) and \
1073 __ptr -= 2; \
1078 if (SMC_CAN_USE_DATACS && lp->datacs) \
1079 __ioaddr = lp->datacs; \