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1 /* SPDX-License-Identifier: GPL-2.0-only */
4 * Copyright 2009-2018 Solarflare Communications Inc.
5 * Copyright 2019-2020 Xilinx Inc.
13 /* Power-on reset state */
19 #define MC_FW_STATE_BOOTING (4)
35 /* The 'doorbell' addresses are hard-wired to alert the MC when written */
36 #define MC_SMEM_P0_DOORBELL_OFST 0x000
37 #define MC_SMEM_P1_DOORBELL_OFST 0x004
38 /* The rest of these are firmware-defined */
39 #define MC_SMEM_P0_PDU_OFST 0x008
40 #define MC_SMEM_P1_PDU_OFST 0x108
41 #define MC_SMEM_PDU_LEN 0x100
42 #define MC_SMEM_P0_PTP_TIME_OFST 0x7f0
43 #define MC_SMEM_P0_STATUS_OFST 0x7f8
44 #define MC_SMEM_P1_STATUS_OFST 0x7fc
46 /* Values to be written to the per-port status dword in shared
48 #define MC_STATUS_DWORD_REBOOT (0xb007b007)
49 #define MC_STATUS_DWORD_ASSERT (0xdeaddead)
52 #define MC_FW_VERSION_IS_BOOTLOADER(_v) (((_v) >> 16) == 0xb007)
57 * least every driver must support version 0 and MCDI_PCOL_VERSION
61 /* Unused commands: 0x23, 0x27, 0x30, 0x31 */
68 * 0 7 8 16 20 22 23 24 31
71 * | | \--- Response
72 * | \------- Error
73 * \------------------------------ Resync (always set)
94 #define MCDI_HEADER_OFST 0
95 #define MCDI_HEADER_CODE_LBN 0
102 #define MCDI_HEADER_SEQ_WIDTH 4
114 #define MCDI_HEADER_XFLAGS_EVREQ 0x01
116 #define MCDI_HEADER_XFLAGS_DBRET 0x02
119 #define MCDI_CTL_SDU_LEN_MAX_V1 0xfc
120 #define MCDI_CTL_SDU_LEN_MAX_V2 0x400
126 * - To advance a shared memory request if XFLAGS_EVREQ was set
127 * - As a notification (link state, i2c event), controlled
132 * 0 32 33 36 44 52 60
139 * - LEVEL==INFO Command succeeded
140 * - LEVEL==ERR Command failed
142 * 0 8 16 24 32
146 * LEVEL==ERR, Datalen == 0 => Reboot
150 * examining the first byte which is 0xc0. This corresponds to the
151 * non-existent MCDI command MC_CMD_DEBUG_LOG.
153 * 0 7 8
154 * | command | Resync | = 0xc0
156 * Since the event is written in big-endian byte order, this works
157 * providing bits 56-63 of the event are 0xc0.
160 * | Rsvd | Code | = 0xc0
162 * Which means for convenience the event code is 0xc for all MC
165 #define FSE_AZ_EV_CODE_MCDI_EVRESPONSE 0xc
169 #define MC_CMD_ERR_CODE_OFST 0
170 #define MC_CMD_ERR_PROXY_PENDING_HANDLE_OFST 4
175 #define MC_CMD_CMD_SPACE_ESCAPE_0 0x78
176 #define MC_CMD_CMD_SPACE_ESCAPE_1 0x79
177 #define MC_CMD_CMD_SPACE_ESCAPE_2 0x7A
178 #define MC_CMD_CMD_SPACE_ESCAPE_3 0x7B
179 #define MC_CMD_CMD_SPACE_ESCAPE_4 0x7C
180 #define MC_CMD_CMD_SPACE_ESCAPE_5 0x7D
181 #define MC_CMD_CMD_SPACE_ESCAPE_6 0x7E
182 #define MC_CMD_CMD_SPACE_ESCAPE_7 0x7F
186 #define SIENA_MC_BOOTROM_COPYCODE_VEC (0x800 - 3 * 0x4)
187 #define HUNT_MC_BOOTROM_COPYCODE_VEC (0x8000 - 3 * 0x4)
188 #define MEDFORD_MC_BOOTROM_COPYCODE_VEC (0x10000 - 3 * 0x4)
190 #define SIENA_MC_BOOTROM_NOFLASH_VEC (0x800 - 2 * 0x4)
191 #define HUNT_MC_BOOTROM_NOFLASH_VEC (0x8000 - 2 * 0x4)
192 #define MEDFORD_MC_BOOTROM_NOFLASH_VEC (0x10000 - 2 * 0x4)
194 #define SIENA_MC_BOOTROM_RECOVERY_VEC (0x800 - 2 * 0x4)
195 #define HUNT_MC_BOOTROM_RECOVERY_VEC (0x8000 - 2 * 0x4)
196 #define MEDFORD_MC_BOOTROM_RECOVERY_VEC (0x10000 - 2 * 0x4)
199 #define MEDFORD_MC_BOOTROM_REAL_NOFLASH_VEC (0x10000 - 4 * 0x4)
207 0, 0, 0 }
227 /* This may be ORed with an EVB_PORT_ID_xxx constant to pass a non-default
228 * stack ID (which must be in the range 1-255) along with an EVB port ID.
230 #define EVB_STACK_ID(n) (((n) & 0xff) << 16)
234 * may be followed by the (0-based) number of the first argument that
237 #define MC_CMD_ERR_ARG_OFST 4
241 * specific to Solarflare firmware should use values in the range 0x1000 -
242 * 0x10ff. The range 0x2000 - 0x20ff is reserved for private error codes (see
246 #define MC_CMD_ERR_EPERM 0x1
247 /* enum: Non-existent command target */
248 #define MC_CMD_ERR_ENOENT 0x2
250 #define MC_CMD_ERR_EINTR 0x4
252 #define MC_CMD_ERR_EIO 0x5
254 #define MC_CMD_ERR_EEXIST 0x6
256 #define MC_CMD_ERR_EAGAIN 0xb
258 #define MC_CMD_ERR_ENOMEM 0xc
260 #define MC_CMD_ERR_EACCES 0xd
262 #define MC_CMD_ERR_EBUSY 0x10
264 #define MC_CMD_ERR_ENODEV 0x13
266 #define MC_CMD_ERR_EINVAL 0x16
268 #define MC_CMD_ERR_ENOSPC 0x1c
269 /* enum: Read-only */
270 #define MC_CMD_ERR_EROFS 0x1e
272 #define MC_CMD_ERR_EPIPE 0x20
274 #define MC_CMD_ERR_ERANGE 0x22
275 /* enum: Non-recursive resource is already acquired */
276 #define MC_CMD_ERR_EDEADLK 0x23
278 #define MC_CMD_ERR_ENOSYS 0x26
280 #define MC_CMD_ERR_ETIME 0x3e
282 #define MC_CMD_ERR_ENOLINK 0x43
284 #define MC_CMD_ERR_EPROTO 0x47
286 #define MC_CMD_ERR_EBADMSG 0x4a
288 #define MC_CMD_ERR_ENOTSUP 0x5f
290 #define MC_CMD_ERR_EADDRNOTAVAIL 0x63
292 #define MC_CMD_ERR_ENOTCONN 0x6b
294 #define MC_CMD_ERR_EALREADY 0x72
297 #define MC_CMD_ERR_ESTALE 0x74
299 #define MC_CMD_ERR_ALLOC_FAIL 0x1000
300 /* enum: V-adaptor not found. */
301 #define MC_CMD_ERR_NO_VADAPTOR 0x1001
303 #define MC_CMD_ERR_NO_EVB_PORT 0x1002
304 /* enum: V-switch not found. */
305 #define MC_CMD_ERR_NO_VSWITCH 0x1003
307 #define MC_CMD_ERR_VLAN_LIMIT 0x1004
309 #define MC_CMD_ERR_BAD_PCI_FUNC 0x1005
311 #define MC_CMD_ERR_BAD_VLAN_MODE 0x1006
312 /* enum: Invalid v-switch type. */
313 #define MC_CMD_ERR_BAD_VSWITCH_TYPE 0x1007
314 /* enum: Invalid v-port type. */
315 #define MC_CMD_ERR_BAD_VPORT_TYPE 0x1008
317 #define MC_CMD_ERR_MAC_EXIST 0x1009
319 #define MC_CMD_ERR_SLAVE_NOT_PRESENT 0x100a
321 #define MC_CMD_ERR_DATAPATH_DISABLED 0x100b
323 #define MC_CMD_ERR_CLIENT_NOT_FN 0x100c
328 #define MC_CMD_ERR_TRANSPORT_NOPROXY 0x100d
330 #define MC_CMD_ERR_VLAN_EXIST 0x100e
332 #define MC_CMD_ERR_NO_MAC_ADDR 0x100f
335 * event and then resend its request. This error code is followed by a 32-bit
338 #define MC_CMD_ERR_PROXY_PENDING 0x1010
343 #define MC_CMD_ERR_PROXY_INPROGRESS 0x1011
348 #define MC_CMD_ERR_PROXY_UNEXPECTED 0x1012
350 * an operation failed due to lack of SR-IOV privilege. Normally it is
355 #define MC_CMD_ERR_NO_PRIVILEGE 0x1013
359 * sub-variant switching.
361 #define MC_CMD_ERR_FILTERS_PRESENT 0x1014
365 #define MC_CMD_ERR_NO_CLOCK 0x1015
369 #define MC_CMD_ERR_UNREACHABLE 0x1016
373 #define MC_CMD_ERR_QUEUE_FULL 0x1017
378 #define MC_CMD_ERR_NO_PCIE 0x1018
383 #define MC_CMD_ERR_NO_DATAPATH 0x1019
385 #define MC_CMD_ERR_VIS_PRESENT 0x101a
389 #define MC_CMD_ERR_PIOBUFS_PRESENT 0x101b
404 #define PCIE_INTERFACE_HOST_PRIMARY 0x0
406 * an on-NIC ARM module is expected to be connected.
408 #define PCIE_INTERFACE_NIC_EMBEDDED 0x1
409 /* enum: The PCIe logical interface 0. It is an alias for HOST_PRIMARY. */
410 #define PCIE_INTERFACE_PCIE_HOST_INTF_0 0x0
412 #define PCIE_INTERFACE_PCIE_HOST_INTF_1 0x2
414 #define PCIE_INTERFACE_PCIE_HOST_INTF_2 0x3
416 #define PCIE_INTERFACE_PCIE_HOST_INTF_3 0x4
421 #define PCIE_INTERFACE_CALLER 0xffffffff
425 #define MC_CMD_CLIENT_ID_SELF 0xffffffff
437 * and must never set a non-zero mask value for this field.
439 #define MAE_FIELD_UNSUPPORTED 0x0
444 #define MAE_FIELD_SUPPORTED_MATCH_NEVER 0x1
449 #define MAE_FIELD_SUPPORTED_MATCH_ALWAYS 0x2
455 #define MAE_FIELD_SUPPORTED_MATCH_OPTIONAL 0x3
461 #define MAE_FIELD_SUPPORTED_MATCH_PREFIX 0x4
465 #define MAE_FIELD_SUPPORTED_MATCH_MASK 0x5
468 * lookup. (Values are not arbitrary - constrained by table access ABI.)
471 #define MAE_CT_VNI_MODE_ZERO 0x0
475 #define MAE_CT_VNI_MODE_VNI 0x1
479 #define MAE_CT_VNI_MODE_1VLAN 0x2
483 #define MAE_CT_VNI_MODE_2VLAN 0x3
488 #define MAE_FIELD_INGRESS_PORT 0x0
489 #define MAE_FIELD_MARK 0x1 /* enum */
493 #define MAE_FIELD_RECIRC_ID 0x2
494 #define MAE_FIELD_IS_IP_FRAG 0x3 /* enum */
495 #define MAE_FIELD_DO_CT 0x4 /* enum */
496 #define MAE_FIELD_CT_HIT 0x5 /* enum */
498 #define MAE_FIELD_CT_MARK 0x6
500 #define MAE_FIELD_CT_DOMAIN 0x7
502 #define MAE_FIELD_CT_PRIVATE_FLAGS 0x8
503 /* enum: 1 if the packet ingressed the NIC from one of the MACs, else 0. */
504 #define MAE_FIELD_IS_FROM_NETWORK 0x9
505 /* enum: 1 if the packet has 1 or more VLAN tags, else 0. */
506 #define MAE_FIELD_HAS_OVLAN 0xa
507 /* enum: 1 if the packet has 2 or more VLAN tags, else 0. */
508 #define MAE_FIELD_HAS_IVLAN 0xb
509 /* enum: 1 if the outer packet has 1 or more VLAN tags, else 0; only present
512 #define MAE_FIELD_ENC_HAS_OVLAN 0xc
513 /* enum: 1 if the outer packet has 2 or more VLAN tags, else 0; only present
516 #define MAE_FIELD_ENC_HAS_IVLAN 0xd
518 #define MAE_FIELD_ENC_IP_FRAG 0xe
519 #define MAE_FIELD_ETHER_TYPE 0x21 /* enum */
520 #define MAE_FIELD_VLAN0_TCI 0x22 /* enum */
521 #define MAE_FIELD_VLAN0_PROTO 0x23 /* enum */
522 #define MAE_FIELD_VLAN1_TCI 0x24 /* enum */
523 #define MAE_FIELD_VLAN1_PROTO 0x25 /* enum */
525 #define MAE_FIELD_ETH_SADDR 0x28
527 #define MAE_FIELD_ETH_DADDR 0x29
529 #define MAE_FIELD_SRC_IP4 0x2a
531 #define MAE_FIELD_SRC_IP6 0x2b
533 #define MAE_FIELD_DST_IP4 0x2c
535 #define MAE_FIELD_DST_IP6 0x2d
537 #define MAE_FIELD_IP_PROTO 0x2e
539 #define MAE_FIELD_IP_TOS 0x2f
541 #define MAE_FIELD_IP_TTL 0x30
544 * matching? TODO: there was a proposal for driver-allocation fields. The
550 #define MAE_FIELD_IP_FLAGS 0x31
552 #define MAE_FIELD_L4_SPORT 0x32
554 #define MAE_FIELD_L4_DPORT 0x33
556 #define MAE_FIELD_TCP_FLAGS 0x34
558 #define MAE_FIELD_TCP_SYN_FIN_RST 0x35
559 /* enum: Packet is IP fragment with fragment offset 0 */
560 #define MAE_FIELD_IP_FIRST_FRAG 0x36
564 #define MAE_FIELD_ENCAP_TYPE 0x3f
568 #define MAE_FIELD_OUTER_RULE_ID 0x40
570 #define MAE_FIELD_ENC_ETHER_TYPE 0x41
572 #define MAE_FIELD_ENC_VLAN0_TCI 0x42
574 #define MAE_FIELD_ENC_VLAN0_PROTO 0x43
576 #define MAE_FIELD_ENC_VLAN1_TCI 0x44
578 #define MAE_FIELD_ENC_VLAN1_PROTO 0x45
580 #define MAE_FIELD_ENC_ETH_SADDR 0x48
582 #define MAE_FIELD_ENC_ETH_DADDR 0x49
584 #define MAE_FIELD_ENC_SRC_IP4 0x4a
586 #define MAE_FIELD_ENC_SRC_IP6 0x4b
588 #define MAE_FIELD_ENC_DST_IP4 0x4c
590 #define MAE_FIELD_ENC_DST_IP6 0x4d
592 #define MAE_FIELD_ENC_IP_PROTO 0x4e
594 #define MAE_FIELD_ENC_IP_TOS 0x4f
596 #define MAE_FIELD_ENC_IP_TTL 0x50
598 #define MAE_FIELD_ENC_IP_FLAGS 0x51
600 #define MAE_FIELD_ENC_L4_SPORT 0x52
602 #define MAE_FIELD_ENC_L4_DPORT 0x53
606 #define MAE_FIELD_ENC_VNET_ID 0x54
610 * should be treated same as NONE. (Values are not arbitrary - constrained by
613 #define MAE_MCDI_ENCAP_TYPE_NONE 0x0 /* enum */
615 #define MAE_MCDI_ENCAP_TYPE_VXLAN 0x1
616 #define MAE_MCDI_ENCAP_TYPE_NVGRE 0x2 /* enum */
617 #define MAE_MCDI_ENCAP_TYPE_GENEVE 0x3 /* enum */
618 #define MAE_MCDI_ENCAP_TYPE_L2GRE 0x4 /* enum */
624 #define MAE_MPORT_END_MAE 0x1
626 #define MAE_MPORT_END_VNIC 0x2
631 * from CT counter 42. Generation counts are also type-specific. This value is
639 /* enum: Action Rule counters - can be referenced in AR response. */
640 #define MAE_COUNTER_TYPE_AR 0x0
641 /* enum: Conntrack counters - can be referenced in CT response. */
642 #define MAE_COUNTER_TYPE_CT 0x1
643 /* enum: Outer Rule counters - can be referenced in OR response. */
644 #define MAE_COUNTER_TYPE_OR 0x2
645 /* enum: LACP counters - linked to LACP balance table entries. */
646 #define MAE_COUNTER_TYPE_LACP 0x3
652 #define MAE_COUNTER_ID_NULL 0xffffffff
654 /* TABLE_ID enum: Unique IDs for tables. The 32-bit ID values have been
655 * structured with bits [31:24] reserved (0), [23:16] indicating which major
656 * block the tables belongs to (0=VNIC TX, none currently; 1=MAE; 2=VNIC RX),
657 * [15:8] a unique ID within the block, and [7:0] reserved for future
660 * all supported - MC_CMD_TABLE_LIST returns the list of actually supported
662 * 0x01010000 + is_dpu_net * 0x10000 + is_wr_or_tx * 0x8000 + is_lite_pipe *
663 * 0x1000 + oe_engine_type * 0x100 + oe_instance_within_pipe * 0x10
665 /* enum: Outer_Rule_Table in the MAE - refer to SF-123102-TC. */
666 #define TABLE_ID_OUTER_RULE_TABLE 0x10000
667 /* enum: Outer_Rule_No_CT_Table in the MAE - refer to SF-123102-TC. */
668 #define TABLE_ID_OUTER_RULE_NO_CT_TABLE 0x10100
669 /* enum: Mgmt_Filter_Table in the MAE - refer to SF-123102-TC. */
670 #define TABLE_ID_MGMT_FILTER_TABLE 0x10200
671 /* enum: Conntrack_Table in the MAE - refer to SF-123102-TC. */
672 #define TABLE_ID_CONNTRACK_TABLE 0x10300
673 /* enum: Action_Rule_Table in the MAE - refer to SF-123102-TC. */
674 #define TABLE_ID_ACTION_RULE_TABLE 0x10400
675 /* enum: Mgroup_Default_Action_Set_Table in the MAE - refer to SF-123102-TC. */
676 #define TABLE_ID_MGROUP_DEFAULT_ACTION_SET_TABLE 0x10500
677 /* enum: Encap_Hdr_Part1_Table in the MAE - refer to SF-123102-TC. */
678 #define TABLE_ID_ENCAP_HDR_PART1_TABLE 0x10600
679 /* enum: Encap_Hdr_Part2_Table in the MAE - refer to SF-123102-TC. */
680 #define TABLE_ID_ENCAP_HDR_PART2_TABLE 0x10700
681 /* enum: Replace_Src_MAC_Table in the MAE - refer to SF-123102-TC. */
682 #define TABLE_ID_REPLACE_SRC_MAC_TABLE 0x10800
683 /* enum: Replace_Dst_MAC_Table in the MAE - refer to SF-123102-TC. */
684 #define TABLE_ID_REPLACE_DST_MAC_TABLE 0x10900
685 /* enum: Dst_Mport_VC_Table in the MAE - refer to SF-123102-TC. */
686 #define TABLE_ID_DST_MPORT_VC_TABLE 0x10a00
687 /* enum: LACP_LAG_Config_Table in the MAE - refer to SF-123102-TC. */
688 #define TABLE_ID_LACP_LAG_CONFIG_TABLE 0x10b00
689 /* enum: LACP_Balance_Table in the MAE - refer to SF-123102-TC. */
690 #define TABLE_ID_LACP_BALANCE_TABLE 0x10c00
691 /* enum: Dst_Mport_Host_Chan_Table in the MAE - refer to SF-123102-TC. */
692 #define TABLE_ID_DST_MPORT_HOST_CHAN_TABLE 0x10d00
693 /* enum: VNIC_Rx_Encap_Table in VNIC Rx - refer to SF-123102-TC. */
694 #define TABLE_ID_VNIC_RX_ENCAP_TABLE 0x20000
695 /* enum: Steering_Table in VNIC Rx - refer to SF-123102-TC. */
696 #define TABLE_ID_STEERING_TABLE 0x20100
697 /* enum: RSS_Context_Table in VNIC Rx - refer to SF-123102-TC. */
698 #define TABLE_ID_RSS_CONTEXT_TABLE 0x20200
699 /* enum: Indirection_Table in VNIC Rx - refer to SF-123102-TC. */
700 #define TABLE_ID_INDIRECTION_TABLE 0x20300
701 /* enum: DPU.host read pipe first CRC offload engine profiles - refer to
702 * XN-200147-AN.
704 #define TABLE_ID_DPU_HOST_RD_CRC0_OE_PROFILE 0x1010000
705 /* enum: DPU.host read pipe second CRC offload engine profiles - refer to
706 * XN-200147-AN.
708 #define TABLE_ID_DPU_HOST_RD_CRC1_OE_PROFILE 0x1010010
709 /* enum: DPU.host write pipe first CRC offload engine profiles - refer to
710 * XN-200147-AN.
712 #define TABLE_ID_DPU_HOST_WR_CRC0_OE_PROFILE 0x1018000
713 /* enum: DPU.host write pipe second CRC offload engine profiles - refer to
714 * XN-200147-AN.
716 #define TABLE_ID_DPU_HOST_WR_CRC1_OE_PROFILE 0x1018010
717 /* enum: DPU.net 'full' receive pipe CRC offload engine profiles - refer to
718 * XN-200147-AN.
720 #define TABLE_ID_DPU_NET_RX_CRC0_OE_PROFILE 0x1020000
721 /* enum: DPU.net 'full' receive pipe first checksum offload engine profiles -
722 * refer to XN-200147-AN.
724 #define TABLE_ID_DPU_NET_RX_CSUM0_OE_PROFILE 0x1020100
725 /* enum: DPU.net 'full' receive pipe second checksum offload engine profiles -
726 * refer to XN-200147-AN.
728 #define TABLE_ID_DPU_NET_RX_CSUM1_OE_PROFILE 0x1020110
729 /* enum: DPU.net 'full' receive pipe AES-GCM offload engine profiles - refer to
730 * XN-200147-AN.
732 #define TABLE_ID_DPU_NET_RX_AES_GCM0_OE_PROFILE 0x1020200
733 /* enum: DPU.net 'lite' receive pipe CRC offload engine profiles - refer to
734 * XN-200147-AN.
736 #define TABLE_ID_DPU_NET_RXLITE_CRC0_OE_PROFILE 0x1021000
737 /* enum: DPU.net 'lite' receive pipe checksum offload engine profiles - refer
738 * to XN-200147-AN.
740 #define TABLE_ID_DPU_NET_RXLITE_CSUM0_OE_PROFILE 0x1021100
741 /* enum: DPU.net 'full' transmit pipe CRC offload engine profiles - refer to
742 * XN-200147-AN.
744 #define TABLE_ID_DPU_NET_TX_CRC0_OE_PROFILE 0x1028000
745 /* enum: DPU.net 'full' transmit pipe first checksum offload engine profiles -
746 * refer to XN-200147-AN.
748 #define TABLE_ID_DPU_NET_TX_CSUM0_OE_PROFILE 0x1028100
749 /* enum: DPU.net 'full' transmit pipe second checksum offload engine profiles -
750 * refer to XN-200147-AN.
752 #define TABLE_ID_DPU_NET_TX_CSUM1_OE_PROFILE 0x1028110
753 /* enum: DPU.net 'full' transmit pipe AES-GCM offload engine profiles - refer
754 * to XN-200147-AN.
756 #define TABLE_ID_DPU_NET_TX_AES_GCM0_OE_PROFILE 0x1028200
757 /* enum: DPU.net 'lite' transmit pipe CRC offload engine profiles - refer to
758 * XN-200147-AN.
760 #define TABLE_ID_DPU_NET_TXLITE_CRC0_OE_PROFILE 0x1029000
761 /* enum: DPU.net 'lite' transmit pipe checksum offload engine profiles - refer
762 * to XN-200147-AN.
764 #define TABLE_ID_DPU_NET_TXLITE_CSUM0_OE_PROFILE 0x1029100
770 * corresponding table definitions in SF-123102-TC; however, the mapping should
778 * the field is unused and should be set to 0 (or masked out if permitted by
781 #define TABLE_FIELD_ID_UNUSED 0x0
782 /* enum: Source m-port (a full m-port label). */
783 #define TABLE_FIELD_ID_SRC_MPORT 0x1
784 /* enum: Destination m-port (a full m-port label). */
785 #define TABLE_FIELD_ID_DST_MPORT 0x2
786 /* enum: Source m-group ID. */
787 #define TABLE_FIELD_ID_SRC_MGROUP_ID 0x3
788 /* enum: Physical network port ID (or m-port ID; same thing, for physical
791 #define TABLE_FIELD_ID_NETWORK_PORT_ID 0x4
794 #define TABLE_FIELD_ID_IS_FROM_NETWORK 0x5
796 #define TABLE_FIELD_ID_CH_VC 0x6
798 #define TABLE_FIELD_ID_CH_VC_LOW 0x7
800 #define TABLE_FIELD_ID_USER_MARK 0x8
802 #define TABLE_FIELD_ID_USER_FLAG 0x9
803 /* enum: Counter ID associated with a response. All-bits-1 is a null value to
806 #define TABLE_FIELD_ID_COUNTER_ID 0xa
811 #define TABLE_FIELD_ID_DISCRIM 0xb
813 * 48-bit value for this field is in network order, i.e. a MAC address of
814 * AA:BB:CC:DD:EE:FF becomes a 48-bit value of 0xAABBCCDDEEFF.
816 #define TABLE_FIELD_ID_DST_MAC 0x14
818 #define TABLE_FIELD_ID_SRC_MAC 0x15
820 #define TABLE_FIELD_ID_OVLAN_TPID_COMPRESSED 0x16
822 #define TABLE_FIELD_ID_OVLAN 0x17
823 /* enum: Outer VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
824 #define TABLE_FIELD_ID_OVLAN_VID 0x18
826 #define TABLE_FIELD_ID_IVLAN_TPID_COMPRESSED 0x19
828 #define TABLE_FIELD_ID_IVLAN 0x1a
829 /* enum: Inner VLAN ID (least significant 12 bits of full 16-bit TCI) only. */
830 #define TABLE_FIELD_ID_IVLAN_VID 0x1b
832 #define TABLE_FIELD_ID_ETHER_TYPE 0x1c
834 * frame to the 128-bit value for this field is in network order, with IPv4
836 * [2345::6789:ABCD] is 0x2345000000000000000000006789ABCD; the IPv4 address
837 * 192.168.1.2 is 0xC0A80102000000000000000000000000.
839 #define TABLE_FIELD_ID_SRC_IP 0x1d
841 #define TABLE_FIELD_ID_DST_IP 0x1e
842 /* enum: IPv4 Type-of-Service or IPv6 Traffic Class field. */
843 #define TABLE_FIELD_ID_IP_TOS 0x1f
845 #define TABLE_FIELD_ID_IP_PROTO 0x20
846 /* enum: Layer 4 source port. */
847 #define TABLE_FIELD_ID_SRC_PORT 0x21
848 /* enum: Layer 4 destination port. */
849 #define TABLE_FIELD_ID_DST_PORT 0x22
851 #define TABLE_FIELD_ID_TCP_FLAGS 0x23
853 #define TABLE_FIELD_ID_VNI 0x24
855 #define TABLE_FIELD_ID_HAS_ENCAP 0x32
857 #define TABLE_FIELD_ID_HAS_ENC_OVLAN 0x33
859 #define TABLE_FIELD_ID_HAS_ENC_IVLAN 0x34
861 #define TABLE_FIELD_ID_HAS_ENC_IP 0x35
863 #define TABLE_FIELD_ID_HAS_ENC_IP4 0x36
865 #define TABLE_FIELD_ID_HAS_ENC_UDP 0x37
867 #define TABLE_FIELD_ID_HAS_OVLAN 0x38
869 #define TABLE_FIELD_ID_HAS_IVLAN 0x39
871 #define TABLE_FIELD_ID_HAS_IP 0x3a
874 #define TABLE_FIELD_ID_HAS_L4 0x3b
876 #define TABLE_FIELD_ID_IP_FRAG 0x3c
877 /* enum: True if only/inner frame is the first IP fragment (fragment offset 0).
879 #define TABLE_FIELD_ID_IP_FIRST_FRAG 0x3d
880 /* enum: True if only/inner frame has an IP Time-To-Live of <= 1. (Note: the
882 * with TTL=0 - which we shouldn't be seeing! - as well.)
884 #define TABLE_FIELD_ID_IP_TTL_LE_ONE 0x3e
886 #define TABLE_FIELD_ID_TCP_INTERESTING_FLAGS 0x3f
888 #define TABLE_FIELD_ID_RDP_PL_CHAN 0x50
890 #define TABLE_FIELD_ID_RDP_C_PL_EN 0x51
892 #define TABLE_FIELD_ID_RDP_C_PL 0x52
894 #define TABLE_FIELD_ID_RDP_D_PL_EN 0x53
896 #define TABLE_FIELD_ID_RDP_D_PL 0x54
898 #define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN_EN 0x55
900 #define TABLE_FIELD_ID_RDP_OUT_HOST_CHAN 0x56
902 #define TABLE_FIELD_ID_RECIRC_ID 0x64
904 #define TABLE_FIELD_ID_DOMAIN 0x65
905 /* enum: Construction mode for encap_tunnel_id - see MAE_CT_VNI_MODE enum. */
906 #define TABLE_FIELD_ID_CT_VNI_MODE 0x66
909 #define TABLE_FIELD_ID_CT_TCP_FLAGS_INHIBIT 0x67
911 #define TABLE_FIELD_ID_DO_CT_IP4_TCP 0x68
913 #define TABLE_FIELD_ID_DO_CT_IP4_UDP 0x69
915 #define TABLE_FIELD_ID_DO_CT_IP6_TCP 0x6a
917 #define TABLE_FIELD_ID_DO_CT_IP6_UDP 0x6b
919 #define TABLE_FIELD_ID_OUTER_RULE_ID 0x6c
920 /* enum: Encapsulation type - see MAE_MCDI_ENCAP_TYPE enum. */
921 #define TABLE_FIELD_ID_ENCAP_TYPE 0x6d
922 /* enum: Encap tunnel ID for conntrack lookups from VNI, VLAN tag(s), or 0,
925 #define TABLE_FIELD_ID_ENCAP_TUNNEL_ID 0x78
927 #define TABLE_FIELD_ID_CT_ENTRY_ID 0x79
929 #define TABLE_FIELD_ID_NAT_PORT 0x7a
932 * byte mapped to a 32-bit value in network order, i.e. the IPv4 address
933 * 192.168.1.2 is the value 0xC0A80102.
935 #define TABLE_FIELD_ID_NAT_IP 0x7b
936 /* enum: NAT direction: 0=>source, 1=>destination. */
937 #define TABLE_FIELD_ID_NAT_DIR 0x7c
941 #define TABLE_FIELD_ID_CT_MARK 0x7d
943 #define TABLE_FIELD_ID_CT_PRIV_FLAGS 0x7e
945 #define TABLE_FIELD_ID_CT_HIT 0x7f
946 /* enum: True to suppress delivery when source and destination m-ports match.
948 #define TABLE_FIELD_ID_SUPPRESS_SELF_DELIVERY 0x8c
950 #define TABLE_FIELD_ID_DO_DECAP 0x8d
952 #define TABLE_FIELD_ID_DECAP_DSCP_COPY 0x8e
954 #define TABLE_FIELD_ID_DECAP_ECN_RFC6040 0x8f
956 #define TABLE_FIELD_ID_DO_REPLACE_DSCP 0x90
958 #define TABLE_FIELD_ID_DO_REPLACE_ECN 0x91
959 /* enum: True to decrement IP Time-To-Live. */
960 #define TABLE_FIELD_ID_DO_DECR_IP_TTL 0x92
962 #define TABLE_FIELD_ID_DO_SRC_MAC 0x93
964 #define TABLE_FIELD_ID_DO_DST_MAC 0x94
965 /* enum: Number of VLAN tags to pop. Valid values are 0, 1, or 2. */
966 #define TABLE_FIELD_ID_DO_VLAN_POP 0x95
967 /* enum: Number of VLANs tags to push. Valid values are 0, 1, or 2. */
968 #define TABLE_FIELD_ID_DO_VLAN_PUSH 0x96
970 #define TABLE_FIELD_ID_DO_COUNT 0x97
972 #define TABLE_FIELD_ID_DO_ENCAP 0x98
974 #define TABLE_FIELD_ID_ENCAP_DSCP_COPY 0x99
976 #define TABLE_FIELD_ID_ENCAP_ECN_COPY 0x9a
978 #define TABLE_FIELD_ID_DO_DELIVER 0x9b
980 #define TABLE_FIELD_ID_DO_FLAG 0x9c
982 #define TABLE_FIELD_ID_DO_MARK 0x9d
985 #define TABLE_FIELD_ID_DO_SET_NET_CHAN 0x9e
986 /* enum: True to override the reported source m-port for host deliveries. */
987 #define TABLE_FIELD_ID_DO_SET_SRC_MPORT 0x9f
989 #define TABLE_FIELD_ID_ENCAP_HDR_ID 0xaa
991 #define TABLE_FIELD_ID_DSCP_VALUE 0xab
993 * DO_REPLACE_ECN is not set, ECN_CONTROL[0] and ECN_CONTROL[1] are set to
996 #define TABLE_FIELD_ID_ECN_CONTROL 0xac
998 #define TABLE_FIELD_ID_SRC_MAC_ID 0xad
1000 #define TABLE_FIELD_ID_DST_MAC_ID 0xae
1004 #define TABLE_FIELD_ID_REPORTED_SRC_MPORT_OR_NET_CHAN 0xaf
1005 /* enum: 64-byte chunk of added encapsulation header. */
1006 #define TABLE_FIELD_ID_CHUNK64 0xb4
1007 /* enum: 32-byte chunk of added encapsulation header. */
1008 #define TABLE_FIELD_ID_CHUNK32 0xb5
1009 /* enum: 16-byte chunk of added encapsulation header. */
1010 #define TABLE_FIELD_ID_CHUNK16 0xb6
1011 /* enum: 8-byte chunk of added encapsulation header. */
1012 #define TABLE_FIELD_ID_CHUNK8 0xb7
1013 /* enum: 4-byte chunk of added encapsulation header. */
1014 #define TABLE_FIELD_ID_CHUNK4 0xb8
1015 /* enum: 2-byte chunk of added encapsulation header. */
1016 #define TABLE_FIELD_ID_CHUNK2 0xb9
1018 #define TABLE_FIELD_ID_HDR_LEN_W 0xba
1020 #define TABLE_FIELD_ID_ENC_LACP_HASH_L23 0xbb
1021 /* enum: Static value for layer 4 LACP hash of the encapsulation header. */
1022 #define TABLE_FIELD_ID_ENC_LACP_HASH_L4 0xbc
1025 * encapsulated packet to a LAG m-port.
1027 #define TABLE_FIELD_ID_USE_ENC_LACP_HASHES 0xbd
1031 #define TABLE_FIELD_ID_DO_CT 0xc8
1034 #define TABLE_FIELD_ID_DO_NAT 0xc9
1036 #define TABLE_FIELD_ID_DO_RECIRC 0xca
1037 /* enum: Next action set payload ID for replay. The null value is all-1-bits.
1039 #define TABLE_FIELD_ID_NEXT_ACTION_SET_PAYLOAD 0xcb
1040 /* enum: Next action set row ID for replay. The null value is all-1-bits. */
1041 #define TABLE_FIELD_ID_NEXT_ACTION_SET_ROW 0xcc
1043 * null value is all-1-bits.
1045 #define TABLE_FIELD_ID_MC_ACTION_SET_PAYLOAD 0xcd
1047 * value is all-1-bits.
1049 #define TABLE_FIELD_ID_MC_ACTION_SET_ROW 0xce
1050 /* enum: True to include layer 4 in LACP hash on delivery to a LAG m-port. */
1051 #define TABLE_FIELD_ID_LACP_INC_L4 0xdc
1053 #define TABLE_FIELD_ID_LACP_PLUGIN 0xdd
1055 #define TABLE_FIELD_ID_BAL_TBL_BASE_DIV64 0xde
1056 /* enum: Length of balance table region: 0=>64, 1=>128, 2=>256. */
1057 #define TABLE_FIELD_ID_BAL_TBL_LEN_ID 0xdf
1059 * LACP_LAG_Config_Table. Refer to SF-123102-TC.
1061 #define TABLE_FIELD_ID_LACP_LAG_ID 0xe0
1065 * to SF-123102-TC.
1067 #define TABLE_FIELD_ID_BAL_TBL_ADDR 0xe1
1068 /* enum: UDP port to match for UDP-based encapsulations; required to be 0 for
1071 #define TABLE_FIELD_ID_UDP_PORT 0xe6
1073 #define TABLE_FIELD_ID_RSS_ON_OUTER 0xe7
1077 #define TABLE_FIELD_ID_STEER_ON_OUTER 0xe8
1079 #define TABLE_FIELD_ID_DST_QID 0xf0
1081 #define TABLE_FIELD_ID_DROP 0xf1
1083 #define TABLE_FIELD_ID_VLAN_STRIP 0xf2
1085 * false to bitwise-OR the USER_MARK into it.
1087 #define TABLE_FIELD_ID_MARK_OVERRIDE 0xf3
1089 * false to bitwise-OR the USER_FLAG into it.
1091 #define TABLE_FIELD_ID_FLAG_OVERRIDE 0xf4
1093 #define TABLE_FIELD_ID_RSS_CTX_ID 0xfa
1095 #define TABLE_FIELD_ID_RSS_EN 0xfb
1097 #define TABLE_FIELD_ID_KEY 0xfc
1098 /* enum: Key mode for IPv4 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1099 #define TABLE_FIELD_ID_TCP_V4_KEY_MODE 0xfd
1100 /* enum: Key mode for IPv6 TCP packets - see TABLE_RSS_KEY_MODE enum. */
1101 #define TABLE_FIELD_ID_TCP_V6_KEY_MODE 0xfe
1102 /* enum: Key mode for IPv4 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1103 #define TABLE_FIELD_ID_UDP_V4_KEY_MODE 0xff
1104 /* enum: Key mode for IPv6 UDP packets - see TABLE_RSS_KEY_MODE enum. */
1105 #define TABLE_FIELD_ID_UDP_V6_KEY_MODE 0x100
1106 /* enum: Key mode for other IPv4 packets - see TABLE_RSS_KEY_MODE enum. */
1107 #define TABLE_FIELD_ID_OTHER_V4_KEY_MODE 0x101
1108 /* enum: Key mode for other IPv6 packets - see TABLE_RSS_KEY_MODE enum. */
1109 #define TABLE_FIELD_ID_OTHER_V6_KEY_MODE 0x102
1110 /* enum: Spreading mode - 0=>indirection; 1=>even. */
1111 #define TABLE_FIELD_ID_SPREAD_MODE 0x103
1114 * spread across (only values 1-255 are valid for this mode).
1116 #define TABLE_FIELD_ID_INDIR_TBL_BASE 0x104
1118 * within the Indirection_Table, where length = 32 << len_id. Must be set to 0
1121 #define TABLE_FIELD_ID_INDIR_TBL_LEN_ID 0x105
1123 #define TABLE_FIELD_ID_INDIR_OFFSET 0x106
1125 #define TABLE_FIELD_ID_OE_PROFILE 0x3e8
1126 /* enum: Width of the CRC to calculate - see CRC_VARIANT enum. */
1127 #define TABLE_FIELD_ID_CRC_VARIANT 0x3f2
1128 /* enum: If set, reflect the bits of each input byte, bit 7 is LSB, bit 0 is
1129 * MSB. If clear, bit 7 is MSB, bit 0 is LSB.
1131 #define TABLE_FIELD_ID_CRC_REFIN 0x3f3
1132 /* enum: If set, reflect the bits of each output byte, bit 7 is LSB, bit 0 is
1133 * MSB. If clear, bit 7 is MSB, bit 0 is LSB.
1135 #define TABLE_FIELD_ID_CRC_REFOUT 0x3f4
1137 #define TABLE_FIELD_ID_CRC_INVOUT 0x3f5
1139 #define TABLE_FIELD_ID_CRC_POLY 0x3f6
1140 /* enum: Operation for the checksum engine to perform - see DPU_CSUM_OP enum.
1142 #define TABLE_FIELD_ID_CSUM_OP 0x410
1146 #define TABLE_FIELD_ID_CSUM_OFFSET 0x411
1150 #define TABLE_FIELD_ID_CSUM_OPR_ADDITIONAL_DATA 0x412
1152 #define TABLE_FIELD_ID_CSUM_OPR_DATA_SIZE_LOG2 0x413
1153 /* enum: 4 byte offset of where to find the additional data on the OPR bus. */
1154 #define TABLE_FIELD_ID_CSUM_OPR_4B_OFF 0x414
1155 /* enum: Operation type for the AES-GCM core - see GCM_OP_CODE enum. */
1156 #define TABLE_FIELD_ID_GCM_OP_CODE 0x41a
1157 /* enum: Key length - AES_KEY_LEN enum. */
1158 #define TABLE_FIELD_ID_GCM_KEY_LEN 0x41b
1159 /* enum: OPR 4 byte offset for ICV or GHASH output (only in BULK_* mode) or
1162 #define TABLE_FIELD_ID_GCM_OPR_4B_OFFSET 0x41c
1164 * indicates IPSEC-ESN mode.
1166 #define TABLE_FIELD_ID_GCM_EMIT_GHASH_ISESN 0x41d
1168 #define TABLE_FIELD_ID_GCM_REPLAY_PROTECT_EN 0x41e
1170 #define TABLE_FIELD_ID_GCM_NEXT_HDR 0x41f
1172 #define TABLE_FIELD_ID_GCM_REPLAY_WIN_SIZE 0x420
1183 #define MCDI_EVENT_LEVEL_INFO 0x0
1185 #define MCDI_EVENT_LEVEL_WARN 0x1
1187 #define MCDI_EVENT_LEVEL_ERR 0x2
1189 #define MCDI_EVENT_LEVEL_FATAL 0x3
1190 #define MCDI_EVENT_DATA_OFST 0
1191 #define MCDI_EVENT_DATA_LEN 4
1192 #define MCDI_EVENT_CMDDONE_SEQ_OFST 0
1193 #define MCDI_EVENT_CMDDONE_SEQ_LBN 0
1195 #define MCDI_EVENT_CMDDONE_DATALEN_OFST 0
1198 #define MCDI_EVENT_CMDDONE_ERRNO_OFST 0
1201 #define MCDI_EVENT_LINKCHANGE_LP_CAP_OFST 0
1202 #define MCDI_EVENT_LINKCHANGE_LP_CAP_LBN 0
1204 #define MCDI_EVENT_LINKCHANGE_SPEED_OFST 0
1206 #define MCDI_EVENT_LINKCHANGE_SPEED_WIDTH 4
1208 #define MCDI_EVENT_LINKCHANGE_SPEED_UNKNOWN 0x0
1210 #define MCDI_EVENT_LINKCHANGE_SPEED_100M 0x1
1212 #define MCDI_EVENT_LINKCHANGE_SPEED_1G 0x2
1214 #define MCDI_EVENT_LINKCHANGE_SPEED_10G 0x3
1216 #define MCDI_EVENT_LINKCHANGE_SPEED_40G 0x4
1218 #define MCDI_EVENT_LINKCHANGE_SPEED_25G 0x5
1220 #define MCDI_EVENT_LINKCHANGE_SPEED_50G 0x6
1222 #define MCDI_EVENT_LINKCHANGE_SPEED_100G 0x7
1223 #define MCDI_EVENT_LINKCHANGE_FCNTL_OFST 0
1225 #define MCDI_EVENT_LINKCHANGE_FCNTL_WIDTH 4
1226 #define MCDI_EVENT_LINKCHANGE_LINK_FLAGS_OFST 0
1229 #define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_OFST 0
1230 #define MCDI_EVENT_PORT_LINKCHANGE_PORT_HANDLE_LBN 0
1232 #define MCDI_EVENT_PORT_LINKCHANGE_SEQ_NUM_OFST 0
1235 #define MCDI_EVENT_PORT_LINKCHANGE_LINK_UP_OFST 0
1238 #define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_OFST 0
1239 #define MCDI_EVENT_PORT_MODULECHANGE_PORT_HANDLE_LBN 0
1241 #define MCDI_EVENT_PORT_MODULECHANGE_SEQ_NUM_OFST 0
1244 #define MCDI_EVENT_PORT_MODULECHANGE_MDI_CONNECTED_OFST 0
1247 #define MCDI_EVENT_SENSOREVT_MONITOR_OFST 0
1248 #define MCDI_EVENT_SENSOREVT_MONITOR_LBN 0
1250 #define MCDI_EVENT_SENSOREVT_STATE_OFST 0
1253 #define MCDI_EVENT_SENSOREVT_VALUE_OFST 0
1256 #define MCDI_EVENT_FWALERT_DATA_OFST 0
1259 #define MCDI_EVENT_FWALERT_REASON_OFST 0
1260 #define MCDI_EVENT_FWALERT_REASON_LBN 0
1263 #define MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS 0x1
1264 #define MCDI_EVENT_FLR_VF_OFST 0
1265 #define MCDI_EVENT_FLR_VF_LBN 0
1267 #define MCDI_EVENT_TX_ERR_TXQ_OFST 0
1268 #define MCDI_EVENT_TX_ERR_TXQ_LBN 0
1270 #define MCDI_EVENT_TX_ERR_TYPE_OFST 0
1272 #define MCDI_EVENT_TX_ERR_TYPE_WIDTH 4
1273 /* enum: Descriptor loader reported failure. Specific to EF10-family NICs. */
1274 #define MCDI_EVENT_TX_ERR_DL_FAIL 0x1
1276 * EF10-family NICs
1278 #define MCDI_EVENT_TX_ERR_NO_EOP 0x2
1279 /* enum: Overlength packet. Specific to EF10-family NICs. */
1280 #define MCDI_EVENT_TX_ERR_2BIG 0x3
1281 /* enum: Malformed option descriptor. Specific to EF10-family NICs. */
1282 #define MCDI_EVENT_TX_BAD_OPTDESC 0x5
1283 /* enum: Option descriptor part way through a packet. Specific to EF10-family
1286 #define MCDI_EVENT_TX_OPT_IN_PKT 0x8
1287 /* enum: DMA or PIO data access error. Specific to EF10-family NICs */
1288 #define MCDI_EVENT_TX_ERR_BAD_DMA_OR_PIO 0x9
1289 #define MCDI_EVENT_TX_ERR_INFO_OFST 0
1292 #define MCDI_EVENT_TX_FLUSH_TO_DRIVER_OFST 0
1295 #define MCDI_EVENT_TX_FLUSH_TXQ_OFST 0
1296 #define MCDI_EVENT_TX_FLUSH_TXQ_LBN 0
1298 #define MCDI_EVENT_PTP_ERR_TYPE_OFST 0
1299 #define MCDI_EVENT_PTP_ERR_TYPE_LBN 0
1302 #define MCDI_EVENT_PTP_ERR_PLL_LOST 0x1
1304 #define MCDI_EVENT_PTP_ERR_FILTER 0x2
1306 #define MCDI_EVENT_PTP_ERR_FIFO 0x3
1308 #define MCDI_EVENT_PTP_ERR_QUEUE 0x4
1309 #define MCDI_EVENT_AOE_ERR_TYPE_OFST 0
1310 #define MCDI_EVENT_AOE_ERR_TYPE_LBN 0
1312 /* enum: AOE failed to load - no valid image? */
1313 #define MCDI_EVENT_AOE_NO_LOAD 0x1
1315 #define MCDI_EVENT_AOE_FC_ASSERT 0x2
1317 #define MCDI_EVENT_AOE_FC_WATCHDOG 0x3
1319 #define MCDI_EVENT_AOE_FC_NO_START 0x4
1320 /* enum: Generic AOE fault - likely to have been reported via other means too
1323 #define MCDI_EVENT_AOE_FAULT 0x5
1325 #define MCDI_EVENT_AOE_CPLD_REPROGRAMMED 0x6
1327 #define MCDI_EVENT_AOE_LOAD 0x7
1329 #define MCDI_EVENT_AOE_DMA 0x8
1333 #define MCDI_EVENT_AOE_BYTEBLASTER 0x9
1335 #define MCDI_EVENT_AOE_DDR_ECC_STATUS 0xa
1337 #define MCDI_EVENT_AOE_PTP_STATUS 0xb
1339 #define MCDI_EVENT_AOE_FPGA_LOAD_HEADER_ERR 0xc
1341 #define MCDI_EVENT_AOE_FPGA_POWER_OFF 0xd
1343 #define MCDI_EVENT_AOE_FPGA_LOAD_FAILED 0xe
1345 #define MCDI_EVENT_AOE_INVALID_FPGA_FLASH_TYPE 0xf
1347 #define MCDI_EVENT_AOE_FC_RUN_TIMEDOUT 0x10
1349 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_INVALID 0x11
1350 /* enum: FPGA boot-flash contains an invalid image header */
1351 #define MCDI_EVENT_AOE_FPGA_BOOT_FLASH_HDR_INVALID 0x12
1353 #define MCDI_EVENT_AOE_FPGA_CLOCKS_PROGRAM_FAILED 0x13
1355 #define MCDI_EVENT_AOE_FC_RUNNING 0x14
1356 #define MCDI_EVENT_AOE_ERR_DATA_OFST 0
1359 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_INFO_OFST 0
1363 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_SEEN 0x0
1366 #define MCDI_EVENT_AOE_ERR_FC_ASSERT_DATA_READY 0x1
1367 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_HEADER_VERIFY_FAILED_OFST 0
1371 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_NV_READ_FAIL 0x0
1373 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_MAGIC_FAIL 0x1
1375 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_SILICON_TYPE 0x2
1377 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_VRATIO 0x3
1379 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_TYPE 0x4
1381 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_VOLTAGE 0x5
1383 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SPEED 0x6
1385 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_SIZE 0x7
1387 #define MCDI_EVENT_AOE_ERR_FPGA_HEADER_DDR_RANK 0x8
1388 #define MCDI_EVENT_AOE_ERR_CODE_INVALID_FPGA_FLASH_TYPE_INFO_OFST 0
1392 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_PRIMARY 0x0
1394 #define MCDI_EVENT_AOE_FLASH_TYPE_BOOT_SECONDARY 0x1
1395 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_POWER_OFF_OFST 0
1398 #define MCDI_EVENT_AOE_ERR_CODE_FPGA_LOAD_FAILED_OFST 0
1401 #define MCDI_EVENT_RX_ERR_RXQ_OFST 0
1402 #define MCDI_EVENT_RX_ERR_RXQ_LBN 0
1404 #define MCDI_EVENT_RX_ERR_TYPE_OFST 0
1406 #define MCDI_EVENT_RX_ERR_TYPE_WIDTH 4
1407 #define MCDI_EVENT_RX_ERR_INFO_OFST 0
1410 #define MCDI_EVENT_RX_FLUSH_TO_DRIVER_OFST 0
1413 #define MCDI_EVENT_RX_FLUSH_RXQ_OFST 0
1414 #define MCDI_EVENT_RX_FLUSH_RXQ_LBN 0
1416 #define MCDI_EVENT_MC_REBOOT_COUNT_OFST 0
1417 #define MCDI_EVENT_MC_REBOOT_COUNT_LBN 0
1419 #define MCDI_EVENT_MUM_ERR_TYPE_OFST 0
1420 #define MCDI_EVENT_MUM_ERR_TYPE_LBN 0
1422 /* enum: MUM failed to load - no valid image? */
1423 #define MCDI_EVENT_MUM_NO_LOAD 0x1
1425 #define MCDI_EVENT_MUM_ASSERT 0x2
1427 #define MCDI_EVENT_MUM_WATCHDOG 0x3
1428 #define MCDI_EVENT_MUM_ERR_DATA_OFST 0
1431 #define MCDI_EVENT_DBRET_SEQ_OFST 0
1432 #define MCDI_EVENT_DBRET_SEQ_LBN 0
1434 #define MCDI_EVENT_SUC_ERR_TYPE_OFST 0
1435 #define MCDI_EVENT_SUC_ERR_TYPE_LBN 0
1438 #define MCDI_EVENT_SUC_BAD_APP 0x1
1440 #define MCDI_EVENT_SUC_ASSERT 0x2
1442 #define MCDI_EVENT_SUC_EXCEPTION 0x3
1444 #define MCDI_EVENT_SUC_WATCHDOG 0x4
1445 #define MCDI_EVENT_SUC_ERR_ADDRESS_OFST 0
1448 #define MCDI_EVENT_SUC_ERR_DATA_OFST 0
1451 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_OFST 0
1452 #define MCDI_EVENT_LINKCHANGE_V2_LP_CAP_LBN 0
1454 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_OFST 0
1456 #define MCDI_EVENT_LINKCHANGE_V2_SPEED_WIDTH 4
1459 #define MCDI_EVENT_LINKCHANGE_V2_FLAGS_LINK_UP_OFST 0
1462 #define MCDI_EVENT_LINKCHANGE_V2_FCNTL_OFST 0
1467 #define MCDI_EVENT_MODULECHANGE_LD_CAP_OFST 0
1468 #define MCDI_EVENT_MODULECHANGE_LD_CAP_LBN 0
1470 #define MCDI_EVENT_MODULECHANGE_SEQ_OFST 0
1473 #define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_OFST 0
1474 #define MCDI_EVENT_DESC_PROXY_VIRTQ_VI_ID_LBN 0
1476 #define MCDI_EVENT_DESC_PROXY_VIRTQ_ID_OFST 0
1479 #define MCDI_EVENT_DATA_LBN 0
1494 #define MCDI_EVENT_EV_CODE_WIDTH 4
1498 #define MCDI_EVENT_SW_EVENT 0x0
1500 #define MCDI_EVENT_CODE_BADSSERT 0x1
1502 #define MCDI_EVENT_CODE_PMNOTICE 0x2
1504 #define MCDI_EVENT_CODE_CMDDONE 0x3
1506 #define MCDI_EVENT_CODE_LINKCHANGE 0x4
1508 #define MCDI_EVENT_CODE_SENSOREVT 0x5
1510 #define MCDI_EVENT_CODE_SCHEDERR 0x6
1512 #define MCDI_EVENT_CODE_REBOOT 0x7
1514 #define MCDI_EVENT_CODE_MAC_STATS_DMA 0x8
1516 #define MCDI_EVENT_CODE_FWALERT 0x9
1518 #define MCDI_EVENT_CODE_FLR 0xa
1520 #define MCDI_EVENT_CODE_TX_ERR 0xb
1522 #define MCDI_EVENT_CODE_TX_FLUSH 0xc
1524 #define MCDI_EVENT_CODE_PTP_RX 0xd
1526 #define MCDI_EVENT_CODE_PTP_FAULT 0xe
1528 #define MCDI_EVENT_CODE_PTP_PPS 0xf
1530 #define MCDI_EVENT_CODE_RX_FLUSH 0x10
1532 #define MCDI_EVENT_CODE_RX_ERR 0x11
1534 #define MCDI_EVENT_CODE_AOE 0x12
1536 #define MCDI_EVENT_CODE_VCAL_FAIL 0x13
1538 #define MCDI_EVENT_CODE_HW_PPS 0x14
1542 #define MCDI_EVENT_CODE_MC_REBOOT 0x15
1544 #define MCDI_EVENT_CODE_PAR_ERR 0x16
1546 #define MCDI_EVENT_CODE_ECC_CORR_ERR 0x17
1548 #define MCDI_EVENT_CODE_ECC_FATAL_ERR 0x18
1550 #define MCDI_EVENT_CODE_MC_BIST 0x19
1552 #define MCDI_EVENT_CODE_PTP_TIME 0x1a
1554 #define MCDI_EVENT_CODE_MUM 0x1b
1556 #define MCDI_EVENT_CODE_PROXY_REQUEST 0x1c
1560 #define MCDI_EVENT_CODE_PROXY_RESPONSE 0x1d
1564 #define MCDI_EVENT_CODE_DBRET 0x1e
1566 #define MCDI_EVENT_CODE_SUC 0x1f
1570 #define MCDI_EVENT_CODE_LINKCHANGE_V2 0x20
1575 #define MCDI_EVENT_CODE_MODULECHANGE 0x21
1581 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_CHANGE 0x22
1587 #define MCDI_EVENT_CODE_DYNAMIC_SENSORS_STATE_CHANGE 0x23
1592 * MC_CMD_DESC_PROXY_FUNC_CONFIG_COMMIT and SF-122927-TC for details.
1594 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_CONFIG_COMMITTED 0x24
1597 * SF-122927-TC for details.
1599 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_RESET 0x25
1603 * first event's (CONT=1) DATA field carries negotiated virtio feature bits 0
1604 * to 31 and the second (CONT=0) carries bits 32 to 63. For EF100 proxy
1606 * SF-122927-TC for details.
1608 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_DRIVER_ATTACH 0x26
1614 #define MCDI_EVENT_CODE_MPORT_JOURNAL_CHANGE 0x27
1620 #define MCDI_EVENT_CODE_DESC_PROXY_FUNC_QUEUE_START 0x28
1626 #define MCDI_EVENT_CODE_PORT_LINKCHANGE 0x29
1633 #define MCDI_EVENT_CODE_PORT_MODULECHANGE 0x2a
1639 #define MCDI_EVENT_CODE_ENUM_PORTS_CHANGE 0x2b
1643 #define MCDI_EVENT_CODE_TESTGEN 0xfa
1644 #define MCDI_EVENT_CMDDONE_DATA_OFST 0
1645 #define MCDI_EVENT_CMDDONE_DATA_LEN 4
1646 #define MCDI_EVENT_CMDDONE_DATA_LBN 0
1648 #define MCDI_EVENT_LINKCHANGE_DATA_OFST 0
1649 #define MCDI_EVENT_LINKCHANGE_DATA_LEN 4
1650 #define MCDI_EVENT_LINKCHANGE_DATA_LBN 0
1652 #define MCDI_EVENT_PORT_LINKCHANGE_DATA_OFST 0
1653 #define MCDI_EVENT_PORT_LINKCHANGE_DATA_LEN 4
1654 #define MCDI_EVENT_PORT_LINKCHANGE_DATA_LBN 0
1656 #define MCDI_EVENT_PORT_MODULECHANGE_DATA_OFST 0
1657 #define MCDI_EVENT_PORT_MODULECHANGE_DATA_LEN 4
1658 #define MCDI_EVENT_PORT_MODULECHANGE_DATA_LBN 0
1660 #define MCDI_EVENT_SENSOREVT_DATA_OFST 0
1661 #define MCDI_EVENT_SENSOREVT_DATA_LEN 4
1662 #define MCDI_EVENT_SENSOREVT_DATA_LBN 0
1664 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_OFST 0
1665 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LEN 4
1666 #define MCDI_EVENT_MAC_STATS_DMA_GENERATION_LBN 0
1668 #define MCDI_EVENT_TX_ERR_DATA_OFST 0
1669 #define MCDI_EVENT_TX_ERR_DATA_LEN 4
1670 #define MCDI_EVENT_TX_ERR_DATA_LBN 0
1675 #define MCDI_EVENT_PTP_SECONDS_OFST 0
1676 #define MCDI_EVENT_PTP_SECONDS_LEN 4
1677 #define MCDI_EVENT_PTP_SECONDS_LBN 0
1682 #define MCDI_EVENT_PTP_MAJOR_OFST 0
1683 #define MCDI_EVENT_PTP_MAJOR_LEN 4
1684 #define MCDI_EVENT_PTP_MAJOR_LBN 0
1689 #define MCDI_EVENT_PTP_NANOSECONDS_OFST 0
1690 #define MCDI_EVENT_PTP_NANOSECONDS_LEN 4
1691 #define MCDI_EVENT_PTP_NANOSECONDS_LBN 0
1696 #define MCDI_EVENT_PTP_MINOR_OFST 0
1697 #define MCDI_EVENT_PTP_MINOR_LEN 4
1698 #define MCDI_EVENT_PTP_MINOR_LBN 0
1702 #define MCDI_EVENT_PTP_UUID_OFST 0
1703 #define MCDI_EVENT_PTP_UUID_LEN 4
1704 #define MCDI_EVENT_PTP_UUID_LBN 0
1706 #define MCDI_EVENT_RX_ERR_DATA_OFST 0
1707 #define MCDI_EVENT_RX_ERR_DATA_LEN 4
1708 #define MCDI_EVENT_RX_ERR_DATA_LBN 0
1710 #define MCDI_EVENT_PAR_ERR_DATA_OFST 0
1711 #define MCDI_EVENT_PAR_ERR_DATA_LEN 4
1712 #define MCDI_EVENT_PAR_ERR_DATA_LBN 0
1714 #define MCDI_EVENT_ECC_CORR_ERR_DATA_OFST 0
1715 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LEN 4
1716 #define MCDI_EVENT_ECC_CORR_ERR_DATA_LBN 0
1718 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_OFST 0
1719 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LEN 4
1720 #define MCDI_EVENT_ECC_FATAL_ERR_DATA_LBN 0
1723 #define MCDI_EVENT_PTP_TIME_MAJOR_OFST 0
1724 #define MCDI_EVENT_PTP_TIME_MAJOR_LEN 4
1725 #define MCDI_EVENT_PTP_TIME_MAJOR_LBN 0
1727 /* For CODE_PTP_TIME events, bits 19-26 of the minor value of the PTP clock */
1745 /* For CODE_PTP_TIME events where report sync status is enabled, bits 21-26 of
1755 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_OFST 0
1756 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LEN 4
1757 #define MCDI_EVENT_PROXY_REQUEST_BUFF_INDEX_LBN 0
1759 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_OFST 0
1760 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LEN 4
1761 #define MCDI_EVENT_PROXY_RESPONSE_HANDLE_LBN 0
1764 * should resend it. A non-zero value means that the authorization has been
1769 #define MCDI_EVENT_DBRET_DATA_OFST 0
1770 #define MCDI_EVENT_DBRET_DATA_LEN 4
1771 #define MCDI_EVENT_DBRET_DATA_LBN 0
1773 #define MCDI_EVENT_LINKCHANGE_V2_DATA_OFST 0
1774 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LEN 4
1775 #define MCDI_EVENT_LINKCHANGE_V2_DATA_LBN 0
1777 #define MCDI_EVENT_MODULECHANGE_DATA_OFST 0
1778 #define MCDI_EVENT_MODULECHANGE_DATA_LEN 4
1779 #define MCDI_EVENT_MODULECHANGE_DATA_LBN 0
1782 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_OFST 0
1783 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LEN 4
1784 #define MCDI_EVENT_DYNAMIC_SENSORS_GENERATION_LBN 0
1787 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_OFST 0
1788 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LEN 4
1789 #define MCDI_EVENT_DYNAMIC_SENSORS_HANDLE_LBN 0
1792 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_OFST 0
1793 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LEN 4
1794 #define MCDI_EVENT_DYNAMIC_SENSORS_VALUE_LBN 0
1799 #define MCDI_EVENT_DESC_PROXY_DATA_OFST 0
1800 #define MCDI_EVENT_DESC_PROXY_DATA_LEN 4
1801 #define MCDI_EVENT_DESC_PROXY_DATA_LBN 0
1804 #define MCDI_EVENT_DESC_PROXY_GENERATION_OFST 0
1805 #define MCDI_EVENT_DESC_PROXY_GENERATION_LEN 4
1806 #define MCDI_EVENT_DESC_PROXY_GENERATION_LBN 0
1809 * carries bits 0 to 31. Second event (CONT=0) carries bits 32 to 63.
1811 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_OFST 0
1812 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LEN 4
1813 #define MCDI_EVENT_DESC_PROXY_VIRTIO_FEATURES_LBN 0
1819 * Read multiple 32byte words from MC memory. Note - this command really
1823 #define MC_CMD_READ32 0x1
1830 #define MC_CMD_READ32_IN_ADDR_OFST 0
1831 #define MC_CMD_READ32_IN_ADDR_LEN 4
1832 #define MC_CMD_READ32_IN_NUMWORDS_OFST 4
1833 #define MC_CMD_READ32_IN_NUMWORDS_LEN 4
1836 #define MC_CMD_READ32_OUT_LENMIN 4
1839 #define MC_CMD_READ32_OUT_LEN(num) (0+4*(num))
1840 #define MC_CMD_READ32_OUT_BUFFER_NUM(len) (((len)-0)/4)
1841 #define MC_CMD_READ32_OUT_BUFFER_OFST 0
1842 #define MC_CMD_READ32_OUT_BUFFER_LEN 4
1852 #define MC_CMD_WRITE32 0x2
1861 #define MC_CMD_WRITE32_IN_LEN(num) (4+4*(num))
1862 #define MC_CMD_WRITE32_IN_BUFFER_NUM(len) (((len)-4)/4)
1863 #define MC_CMD_WRITE32_IN_ADDR_OFST 0
1864 #define MC_CMD_WRITE32_IN_ADDR_LEN 4
1865 #define MC_CMD_WRITE32_IN_BUFFER_OFST 4
1866 #define MC_CMD_WRITE32_IN_BUFFER_LEN 4
1872 #define MC_CMD_WRITE32_OUT_LEN 0
1879 #define MC_CMD_GET_BOOT_STATUS 0x5
1885 #define MC_CMD_GET_BOOT_STATUS_IN_LEN 0
1890 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_OFST 0
1891 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_LEN 4
1893 #define MC_CMD_GET_BOOT_STATUS_OUT_BOOT_OFFSET_NULL 0xdeadbeef
1894 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_OFST 4
1895 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_LEN 4
1896 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_OFST 4
1897 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_WATCHDOG_LBN 0
1899 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_PRIMARY_OFST 4
1902 #define MC_CMD_GET_BOOT_STATUS_OUT_FLAGS_BACKUP_OFST 4
1913 #define MC_CMD_GET_ASSERTS 0x6
1919 #define MC_CMD_GET_ASSERTS_IN_LEN 4
1921 #define MC_CMD_GET_ASSERTS_IN_CLEAR_OFST 0
1922 #define MC_CMD_GET_ASSERTS_IN_CLEAR_LEN 4
1927 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_OFST 0
1928 #define MC_CMD_GET_ASSERTS_OUT_GLOBAL_FLAGS_LEN 4
1930 #define MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1
1931 /* enum: A system-level assertion has failed. */
1932 #define MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2
1933 /* enum: A thread-level assertion has failed. */
1934 #define MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3
1936 #define MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4
1938 #define MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5
1940 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_OFST 4
1941 #define MC_CMD_GET_ASSERTS_OUT_SAVED_PC_OFFS_LEN 4
1944 #define MC_CMD_GET_ASSERTS_OUT_GP_REGS_OFFS_LEN 4
1949 #define MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057
1952 #define MC_CMD_GET_ASSERTS_OUT_THREAD_OFFS_LEN 4
1954 #define MC_CMD_GET_ASSERTS_OUT_RESERVED_LEN 4
1961 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_OFST 0
1962 #define MC_CMD_GET_ASSERTS_OUT_V2_GLOBAL_FLAGS_LEN 4
1964 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
1965 /* enum: A system-level assertion has failed. */
1966 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
1967 /* enum: A thread-level assertion has failed. */
1968 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
1970 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
1972 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
1974 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_OFST 4
1975 #define MC_CMD_GET_ASSERTS_OUT_V2_SAVED_PC_OFFS_LEN 4
1978 #define MC_CMD_GET_ASSERTS_OUT_V2_GP_REGS_OFFS_LEN 4
1983 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
1986 #define MC_CMD_GET_ASSERTS_OUT_V2_THREAD_OFFS_LEN 4
1988 #define MC_CMD_GET_ASSERTS_OUT_V2_RESERVED_LEN 4
1991 #define MC_CMD_GET_ASSERTS_OUT_V2_SF_REGS_OFFS_LEN 4
1999 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_OFST 0
2000 #define MC_CMD_GET_ASSERTS_OUT_V3_GLOBAL_FLAGS_LEN 4
2002 /* MC_CMD_GET_ASSERTS_FLAGS_NO_FAILS 0x1 */
2003 /* enum: A system-level assertion has failed. */
2004 /* MC_CMD_GET_ASSERTS_FLAGS_SYS_FAIL 0x2 */
2005 /* enum: A thread-level assertion has failed. */
2006 /* MC_CMD_GET_ASSERTS_FLAGS_THR_FAIL 0x3 */
2008 /* MC_CMD_GET_ASSERTS_FLAGS_WDOG_FIRED 0x4 */
2010 /* MC_CMD_GET_ASSERTS_FLAGS_ADDR_TRAP 0x5 */
2012 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_OFST 4
2013 #define MC_CMD_GET_ASSERTS_OUT_V3_SAVED_PC_OFFS_LEN 4
2016 #define MC_CMD_GET_ASSERTS_OUT_V3_GP_REGS_OFFS_LEN 4
2021 /* MC_CMD_GET_ASSERTS_REG_NO_DATA 0xda7a1057 */
2024 #define MC_CMD_GET_ASSERTS_OUT_V3_THREAD_OFFS_LEN 4
2026 #define MC_CMD_GET_ASSERTS_OUT_V3_RESERVED_LEN 4
2029 #define MC_CMD_GET_ASSERTS_OUT_V3_SF_REGS_OFFS_LEN 4
2031 /* MC firmware unique build ID (as binary SHA-1 value) */
2038 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_LO_LEN 4
2042 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_BUILD_TIMESTAMP_HI_LEN 4
2049 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_LO_LEN 4
2053 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_VERSION_HI_LEN 4
2058 #define MC_CMD_GET_ASSERTS_OUT_V3_MC_FW_SECURITY_LEVEL_LEN 4
2059 /* MC firmware extra version info (as null-terminated US-ASCII string) */
2062 /* MC firmware build name (as null-terminated US-ASCII string) */
2072 #define MC_CMD_LOG_CTRL 0x7
2080 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_OFST 0
2081 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_LEN 4
2084 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_UART 0x1
2086 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ 0x2
2088 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_OFST 4
2089 #define MC_CMD_LOG_CTRL_IN_LOG_DEST_EVQ_LEN 4
2092 #define MC_CMD_LOG_CTRL_OUT_LEN 0
2099 #define MC_CMD_GET_VERSION 0x8
2105 #define MC_CMD_GET_VERSION_IN_LEN 0
2108 #define MC_CMD_GET_VERSION_EXT_IN_LEN 4
2109 /* placeholder, set to 0 */
2110 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_OFST 0
2111 #define MC_CMD_GET_VERSION_EXT_IN_EXT_FLAGS_LEN 4
2114 #define MC_CMD_GET_VERSION_V0_OUT_LEN 4
2115 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0
2116 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4
2118 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_ANY 0xffffffff
2120 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_SIENA_BOOTROM 0xb0070000
2122 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_HUNT_BOOTROM 0xb0070001
2124 #define MC_CMD_GET_VERSION_OUT_FIRMWARE_MEDFORD2_BOOTROM 0xb0070002
2131 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2132 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2135 #define MC_CMD_GET_VERSION_OUT_PCOL_OFST 4
2136 #define MC_CMD_GET_VERSION_OUT_PCOL_LEN 4
2143 #define MC_CMD_GET_VERSION_OUT_VERSION_LO_LEN 4
2147 #define MC_CMD_GET_VERSION_OUT_VERSION_HI_LEN 4
2156 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2157 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2160 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_OFST 4
2161 #define MC_CMD_GET_VERSION_EXT_OUT_PCOL_LEN 4
2168 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_LO_LEN 4
2172 #define MC_CMD_GET_VERSION_EXT_OUT_VERSION_HI_LEN 4
2189 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2190 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2193 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_OFST 4
2194 #define MC_CMD_GET_VERSION_V2_OUT_PCOL_LEN 4
2201 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_LO_LEN 4
2205 #define MC_CMD_GET_VERSION_V2_OUT_VERSION_HI_LEN 4
2213 #define MC_CMD_GET_VERSION_V2_OUT_FLAGS_LEN 4
2215 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2227 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2256 /* MC firmware unique build ID (as binary SHA-1 value) */
2261 #define MC_CMD_GET_VERSION_V2_OUT_MCFW_SECURITY_LEVEL_LEN 4
2262 /* MC firmware build name (as null-terminated US-ASCII string) */
2265 /* The SUC firmware version as four numbers - a.b.c.d */
2267 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_LEN 4
2268 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_VERSION_NUM 4
2269 /* SUC firmware build date (as 64-bit Unix timestamp) */
2273 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2277 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2281 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2284 #define MC_CMD_GET_VERSION_V2_OUT_SUCFW_CHIP_ID_LEN 4
2285 /* The CMC firmware version as four numbers - a.b.c.d */
2287 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_LEN 4
2288 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_VERSION_NUM 4
2289 /* CMC firmware build date (as 64-bit Unix timestamp) */
2293 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2297 #define MC_CMD_GET_VERSION_V2_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2302 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2303 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2306 #define MC_CMD_GET_VERSION_V2_OUT_FPGA_VERSION_LEN 4
2308 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2311 /* Board name / adapter model (as null-terminated US-ASCII string) */
2316 #define MC_CMD_GET_VERSION_V2_OUT_BOARD_REVISION_LEN 4
2317 /* Board serial number (as null-terminated US-ASCII string) */
2331 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2332 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2335 #define MC_CMD_GET_VERSION_V3_OUT_PCOL_OFST 4
2336 #define MC_CMD_GET_VERSION_V3_OUT_PCOL_LEN 4
2343 #define MC_CMD_GET_VERSION_V3_OUT_VERSION_LO_LEN 4
2347 #define MC_CMD_GET_VERSION_V3_OUT_VERSION_HI_LEN 4
2355 #define MC_CMD_GET_VERSION_V3_OUT_FLAGS_LEN 4
2357 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2369 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2398 /* MC firmware unique build ID (as binary SHA-1 value) */
2403 #define MC_CMD_GET_VERSION_V3_OUT_MCFW_SECURITY_LEVEL_LEN 4
2404 /* MC firmware build name (as null-terminated US-ASCII string) */
2407 /* The SUC firmware version as four numbers - a.b.c.d */
2409 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_LEN 4
2410 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_VERSION_NUM 4
2411 /* SUC firmware build date (as 64-bit Unix timestamp) */
2415 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2419 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2423 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2426 #define MC_CMD_GET_VERSION_V3_OUT_SUCFW_CHIP_ID_LEN 4
2427 /* The CMC firmware version as four numbers - a.b.c.d */
2429 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_LEN 4
2430 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_VERSION_NUM 4
2431 /* CMC firmware build date (as 64-bit Unix timestamp) */
2435 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2439 #define MC_CMD_GET_VERSION_V3_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2444 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2445 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2448 #define MC_CMD_GET_VERSION_V3_OUT_FPGA_VERSION_LEN 4
2450 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2453 /* Board name / adapter model (as null-terminated US-ASCII string) */
2458 #define MC_CMD_GET_VERSION_V3_OUT_BOARD_REVISION_LEN 4
2459 /* Board serial number (as null-terminated US-ASCII string) */
2462 /* The version of the datapath hardware design as three number - a.b.c */
2464 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_HW_VERSION_LEN 4
2467 * number - a.b.c
2470 #define MC_CMD_GET_VERSION_V3_OUT_DATAPATH_FW_VERSION_LEN 4
2480 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2481 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2484 #define MC_CMD_GET_VERSION_V4_OUT_PCOL_OFST 4
2485 #define MC_CMD_GET_VERSION_V4_OUT_PCOL_LEN 4
2492 #define MC_CMD_GET_VERSION_V4_OUT_VERSION_LO_LEN 4
2496 #define MC_CMD_GET_VERSION_V4_OUT_VERSION_HI_LEN 4
2504 #define MC_CMD_GET_VERSION_V4_OUT_FLAGS_LEN 4
2506 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2518 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2547 /* MC firmware unique build ID (as binary SHA-1 value) */
2552 #define MC_CMD_GET_VERSION_V4_OUT_MCFW_SECURITY_LEVEL_LEN 4
2553 /* MC firmware build name (as null-terminated US-ASCII string) */
2556 /* The SUC firmware version as four numbers - a.b.c.d */
2558 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_LEN 4
2559 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_VERSION_NUM 4
2560 /* SUC firmware build date (as 64-bit Unix timestamp) */
2564 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2568 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2572 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2575 #define MC_CMD_GET_VERSION_V4_OUT_SUCFW_CHIP_ID_LEN 4
2576 /* The CMC firmware version as four numbers - a.b.c.d */
2578 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_LEN 4
2579 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_VERSION_NUM 4
2580 /* CMC firmware build date (as 64-bit Unix timestamp) */
2584 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2588 #define MC_CMD_GET_VERSION_V4_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2593 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2594 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2597 #define MC_CMD_GET_VERSION_V4_OUT_FPGA_VERSION_LEN 4
2599 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2602 /* Board name / adapter model (as null-terminated US-ASCII string) */
2607 #define MC_CMD_GET_VERSION_V4_OUT_BOARD_REVISION_LEN 4
2608 /* Board serial number (as null-terminated US-ASCII string) */
2611 /* The version of the datapath hardware design as three number - a.b.c */
2613 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_HW_VERSION_LEN 4
2616 * number - a.b.c
2619 #define MC_CMD_GET_VERSION_V4_OUT_DATAPATH_FW_VERSION_LEN 4
2621 /* The SOC boot version as four numbers - a.b.c.d */
2623 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_LEN 4
2624 #define MC_CMD_GET_VERSION_V4_OUT_SOC_BOOT_VERSION_NUM 4
2625 /* The SOC uboot version as four numbers - a.b.c.d */
2627 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_LEN 4
2628 #define MC_CMD_GET_VERSION_V4_OUT_SOC_UBOOT_VERSION_NUM 4
2629 /* The SOC main rootfs version as four numbers - a.b.c.d */
2631 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2632 #define MC_CMD_GET_VERSION_V4_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2633 /* The SOC recovery buildroot version as four numbers - a.b.c.d */
2635 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2636 #define MC_CMD_GET_VERSION_V4_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2645 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_OFST 0 */
2646 /* MC_CMD_GET_VERSION_OUT_FIRMWARE_LEN 4 */
2649 #define MC_CMD_GET_VERSION_V5_OUT_PCOL_OFST 4
2650 #define MC_CMD_GET_VERSION_V5_OUT_PCOL_LEN 4
2657 #define MC_CMD_GET_VERSION_V5_OUT_VERSION_LO_LEN 4
2661 #define MC_CMD_GET_VERSION_V5_OUT_VERSION_HI_LEN 4
2669 #define MC_CMD_GET_VERSION_V5_OUT_FLAGS_LEN 4
2671 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_EXT_INFO_PRESENT_LBN 0
2683 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_EXT_INFO_PRESENT_LBN 4
2712 /* MC firmware unique build ID (as binary SHA-1 value) */
2717 #define MC_CMD_GET_VERSION_V5_OUT_MCFW_SECURITY_LEVEL_LEN 4
2718 /* MC firmware build name (as null-terminated US-ASCII string) */
2721 /* The SUC firmware version as four numbers - a.b.c.d */
2723 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_LEN 4
2724 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_VERSION_NUM 4
2725 /* SUC firmware build date (as 64-bit Unix timestamp) */
2729 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_LO_LEN 4
2733 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_BUILD_DATE_HI_LEN 4
2737 * indicates family, memory sizes etc. See SF-116728-SW for further details.
2740 #define MC_CMD_GET_VERSION_V5_OUT_SUCFW_CHIP_ID_LEN 4
2741 /* The CMC firmware version as four numbers - a.b.c.d */
2743 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_LEN 4
2744 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_VERSION_NUM 4
2745 /* CMC firmware build date (as 64-bit Unix timestamp) */
2749 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_LO_LEN 4
2753 #define MC_CMD_GET_VERSION_V5_OUT_CMCFW_BUILD_DATE_HI_LEN 4
2758 * FPGA_VERSION[0]: x => Image H{x} FPGA_VERSION[1]: Revision letter (0 => A, 1
2759 * => B, ...) FPGA_VERSION[2]: Sub-revision number
2762 #define MC_CMD_GET_VERSION_V5_OUT_FPGA_VERSION_LEN 4
2764 /* Extra FPGA revision information (as null-terminated US-ASCII string) */
2767 /* Board name / adapter model (as null-terminated US-ASCII string) */
2772 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_REVISION_LEN 4
2773 /* Board serial number (as null-terminated US-ASCII string) */
2776 /* The version of the datapath hardware design as three number - a.b.c */
2778 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_HW_VERSION_LEN 4
2781 * number - a.b.c
2784 #define MC_CMD_GET_VERSION_V5_OUT_DATAPATH_FW_VERSION_LEN 4
2786 /* The SOC boot version as four numbers - a.b.c.d */
2788 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_LEN 4
2789 #define MC_CMD_GET_VERSION_V5_OUT_SOC_BOOT_VERSION_NUM 4
2790 /* The SOC uboot version as four numbers - a.b.c.d */
2792 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_LEN 4
2793 #define MC_CMD_GET_VERSION_V5_OUT_SOC_UBOOT_VERSION_NUM 4
2794 /* The SOC main rootfs version as four numbers - a.b.c.d */
2796 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_LEN 4
2797 #define MC_CMD_GET_VERSION_V5_OUT_SOC_MAIN_ROOTFS_VERSION_NUM 4
2798 /* The SOC recovery buildroot version as four numbers - a.b.c.d */
2800 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_LEN 4
2801 #define MC_CMD_GET_VERSION_V5_OUT_SOC_RECOVERY_BUILDROOT_VERSION_NUM 4
2802 /* Board version as four numbers - a.b.c.d. BOARD_VERSION[0] duplicates the
2806 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_LEN 4
2807 #define MC_CMD_GET_VERSION_V5_OUT_BOARD_VERSION_NUM 4
2808 /* Bundle version as four numbers - a.b.c.d */
2810 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_LEN 4
2811 #define MC_CMD_GET_VERSION_V5_OUT_BUNDLE_VERSION_NUM 4
2818 #define MC_CMD_PTP 0xb
2826 #define MC_CMD_PTP_IN_OP_OFST 0
2829 #define MC_CMD_PTP_OP_ENABLE 0x1
2831 #define MC_CMD_PTP_OP_DISABLE 0x2
2836 #define MC_CMD_PTP_OP_TRANSMIT 0x3
2838 #define MC_CMD_PTP_OP_READ_NIC_TIME 0x4
2842 #define MC_CMD_PTP_OP_STATUS 0x5
2844 #define MC_CMD_PTP_OP_ADJUST 0x6
2846 #define MC_CMD_PTP_OP_SYNCHRONIZE 0x7
2848 #define MC_CMD_PTP_OP_MANFTEST_BASIC 0x8
2850 #define MC_CMD_PTP_OP_MANFTEST_PACKET 0x9
2852 #define MC_CMD_PTP_OP_RESET_STATS 0xa
2854 #define MC_CMD_PTP_OP_DEBUG 0xb
2856 #define MC_CMD_PTP_OP_FPGAREAD 0xc
2858 #define MC_CMD_PTP_OP_FPGAWRITE 0xd
2860 #define MC_CMD_PTP_OP_CLOCK_OFFSET_ADJUST 0xe
2862 #define MC_CMD_PTP_OP_CLOCK_FREQ_ADJUST 0xf
2866 #define MC_CMD_PTP_OP_RX_SET_VLAN_FILTER 0x10
2870 #define MC_CMD_PTP_OP_RX_SET_UUID_FILTER 0x11
2874 #define MC_CMD_PTP_OP_RX_SET_DOMAIN_FILTER 0x12
2878 #define MC_CMD_PTP_OP_SET_CLK_SRC 0x13
2880 #define MC_CMD_PTP_OP_RST_CLK 0x14
2882 #define MC_CMD_PTP_OP_PPS_ENABLE 0x15
2884 #define MC_CMD_PTP_OP_GET_TIME_FORMAT 0x16
2885 /* enum: Get the clock attributes. NOTE- extended version of
2888 #define MC_CMD_PTP_OP_GET_ATTRIBUTES 0x16
2892 #define MC_CMD_PTP_OP_GET_TIMESTAMP_CORRECTIONS 0x17
2896 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE 0x18
2898 #define MC_CMD_PTP_OP_TIME_EVENT_UNSUBSCRIBE 0x19
2902 #define MC_CMD_PTP_OP_MANFTEST_PPS 0x1a
2906 #define MC_CMD_PTP_OP_SET_SYNC_STATUS 0x1b
2911 #define MC_CMD_PTP_OP_TIME_EVENT_SUBSCRIBE_V2 0x1c
2918 #define MC_CMD_PTP_OP_GET_SYNC_TIMEOUT 0x1d
2922 #define MC_CMD_PTP_IN_CMD_OFST 0
2923 #define MC_CMD_PTP_IN_CMD_LEN 4
2924 #define MC_CMD_PTP_IN_PERIPH_ID_OFST 4
2925 #define MC_CMD_PTP_IN_PERIPH_ID_LEN 4
2926 /* Not used, initialize to 0. Events are always sent to function relative queue
2927 * 0.
2930 #define MC_CMD_PTP_IN_ENABLE_QUEUE_LEN 4
2933 #define MC_CMD_PTP_IN_ENABLE_MODE_LEN 4
2935 #define MC_CMD_PTP_MODE_V1 0x0
2936 /* enum: PTP, version 1, with VLAN headers - deprecated */
2937 #define MC_CMD_PTP_MODE_V1_VLAN 0x1
2939 #define MC_CMD_PTP_MODE_V2 0x2
2940 /* enum: PTP, version 2, with VLAN headers - deprecated */
2941 #define MC_CMD_PTP_MODE_V2_VLAN 0x3
2943 #define MC_CMD_PTP_MODE_V2_ENHANCED 0x4
2945 #define MC_CMD_PTP_MODE_FCOE 0x5
2949 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2950 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2951 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2952 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2959 #define MC_CMD_PTP_IN_TRANSMIT_PACKET_NUM(len) (((len)-12)/1)
2960 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2961 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2962 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2963 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2966 #define MC_CMD_PTP_IN_TRANSMIT_LENGTH_LEN 4
2976 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2977 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2978 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2979 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2983 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2984 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2985 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2986 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2990 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2991 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2992 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
2993 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
2997 /* MC_CMD_PTP_IN_CMD_OFST 0 */
2998 /* MC_CMD_PTP_IN_CMD_LEN 4 */
2999 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3000 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3005 #define MC_CMD_PTP_IN_ADJUST_FREQ_LO_LEN 4
3009 #define MC_CMD_PTP_IN_ADJUST_FREQ_HI_LEN 4
3013 #define MC_CMD_PTP_IN_ADJUST_BITS 0x28
3018 #define MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c
3021 #define MC_CMD_PTP_IN_ADJUST_SECONDS_LEN 4
3024 #define MC_CMD_PTP_IN_ADJUST_MAJOR_LEN 4
3027 #define MC_CMD_PTP_IN_ADJUST_NANOSECONDS_LEN 4
3030 #define MC_CMD_PTP_IN_ADJUST_MINOR_LEN 4
3034 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3035 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3036 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3037 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3042 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_LO_LEN 4
3046 #define MC_CMD_PTP_IN_ADJUST_V2_FREQ_HI_LEN 4
3050 /* MC_CMD_PTP_IN_ADJUST_BITS 0x28 */
3055 /* MC_CMD_PTP_IN_ADJUST_BITS_FP44 0x2c */
3058 #define MC_CMD_PTP_IN_ADJUST_V2_SECONDS_LEN 4
3061 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_LEN 4
3064 #define MC_CMD_PTP_IN_ADJUST_V2_NANOSECONDS_LEN 4
3067 #define MC_CMD_PTP_IN_ADJUST_V2_MINOR_LEN 4
3070 #define MC_CMD_PTP_IN_ADJUST_V2_MAJOR_HI_LEN 4
3074 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3075 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3076 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3077 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3080 #define MC_CMD_PTP_IN_SYNCHRONIZE_NUMTIMESETS_LEN 4
3087 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_LO_LEN 4
3091 #define MC_CMD_PTP_IN_SYNCHRONIZE_START_ADDR_HI_LEN 4
3097 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3098 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3099 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3100 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3104 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3105 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3106 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3107 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3110 #define MC_CMD_PTP_IN_MANFTEST_PACKET_TEST_ENABLE_LEN 4
3114 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3115 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3116 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3117 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3121 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3122 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3123 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3124 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3127 #define MC_CMD_PTP_IN_DEBUG_DEBUG_PARAM_LEN 4
3131 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3132 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3133 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3134 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3136 #define MC_CMD_PTP_IN_FPGAREAD_ADDR_LEN 4
3138 #define MC_CMD_PTP_IN_FPGAREAD_NUMBYTES_LEN 4
3145 #define MC_CMD_PTP_IN_FPGAWRITE_BUFFER_NUM(len) (((len)-12)/1)
3146 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3147 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3148 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3149 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3151 #define MC_CMD_PTP_IN_FPGAWRITE_ADDR_LEN 4
3160 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3161 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3162 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3163 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3166 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_SECONDS_LEN 4
3169 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MAJOR_LEN 4
3172 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_NANOSECONDS_LEN 4
3175 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_MINOR_LEN 4
3179 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3180 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3181 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3182 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3185 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_SECONDS_LEN 4
3188 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_LEN 4
3191 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_NANOSECONDS_LEN 4
3194 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MINOR_LEN 4
3197 #define MC_CMD_PTP_IN_CLOCK_OFFSET_ADJUST_V2_MAJOR_HI_LEN 4
3201 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3202 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3203 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3204 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3209 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_LO_LEN 4
3213 #define MC_CMD_PTP_IN_CLOCK_FREQ_ADJUST_FREQ_HI_LEN 4
3221 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3222 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3223 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3224 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3225 /* Number of VLAN tags, 0 if not VLAN */
3227 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_NUM_VLAN_TAGS_LEN 4
3230 #define MC_CMD_PTP_IN_RX_SET_VLAN_FILTER_VLAN_TAG_LEN 4
3235 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3236 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3237 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3238 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3239 /* 1 to enable UUID filtering, 0 to disable */
3241 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_ENABLE_LEN 4
3246 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_LO_LEN 4
3250 #define MC_CMD_PTP_IN_RX_SET_UUID_FILTER_UUID_HI_LEN 4
3256 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3257 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3258 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3259 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3260 /* 1 to enable Domain filtering, 0 to disable */
3262 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_ENABLE_LEN 4
3265 #define MC_CMD_PTP_IN_RX_SET_DOMAIN_FILTER_DOMAIN_LEN 4
3269 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3270 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3271 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3272 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3275 #define MC_CMD_PTP_IN_SET_CLK_SRC_CLK_LEN 4
3277 #define MC_CMD_PTP_CLK_SRC_INTERNAL 0x0
3279 #define MC_CMD_PTP_CLK_SRC_EXTERNAL 0x1
3283 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3284 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3285 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3286 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3290 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3291 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3293 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_OFST 4
3294 #define MC_CMD_PTP_IN_PPS_ENABLE_OP_LEN 4
3296 #define MC_CMD_PTP_ENABLE_PPS 0x0
3298 #define MC_CMD_PTP_DISABLE_PPS 0x1
3299 /* Not used, initialize to 0. Events are always sent to function relative queue
3300 * 0.
3303 #define MC_CMD_PTP_IN_PPS_ENABLE_QUEUE_ID_LEN 4
3307 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3308 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3309 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3310 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3314 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3315 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3316 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3317 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3321 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3322 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3323 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3324 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3328 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3329 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3330 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3331 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3334 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_LEN 4
3336 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_QUEUE_ID_LBN 0
3344 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3345 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3346 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3347 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3350 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_CONTROL_LEN 4
3352 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_SINGLE 0x0
3354 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_ALL 0x1
3357 #define MC_CMD_PTP_IN_TIME_EVENT_UNSUBSCRIBE_QUEUE_LEN 4
3361 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3362 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3363 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3364 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3367 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_QUEUE_ID_LEN 4
3370 #define MC_CMD_PTP_IN_TIME_EVENT_SUBSCRIBE_V2_FLAGS_LEN 4
3377 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3378 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3379 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3380 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3381 /* 1 to enable PPS test mode, 0 to disable and return result. */
3383 #define MC_CMD_PTP_IN_MANFTEST_PPS_TEST_ENABLE_LEN 4
3387 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3388 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3389 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3390 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3391 /* NIC - Host System Clock Synchronization status */
3393 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_STATUS_LEN 4
3395 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_NOT_IN_SYNC 0x0
3397 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_IN_SYNC 0x1
3402 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_TIMEOUT_LEN 4
3404 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED0_LEN 4
3406 #define MC_CMD_PTP_IN_SET_SYNC_STATUS_RESERVED1_LEN 4
3410 /* MC_CMD_PTP_IN_CMD_OFST 0 */
3411 /* MC_CMD_PTP_IN_CMD_LEN 4 */
3412 /* MC_CMD_PTP_IN_PERIPH_ID_OFST 4 */
3413 /* MC_CMD_PTP_IN_PERIPH_ID_LEN 4 */
3416 #define MC_CMD_PTP_OUT_LEN 0
3421 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_OFST 0
3422 #define MC_CMD_PTP_OUT_TRANSMIT_SECONDS_LEN 4
3424 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_OFST 0
3425 #define MC_CMD_PTP_OUT_TRANSMIT_MAJOR_LEN 4
3427 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_OFST 4
3428 #define MC_CMD_PTP_OUT_TRANSMIT_NANOSECONDS_LEN 4
3430 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_OFST 4
3431 #define MC_CMD_PTP_OUT_TRANSMIT_MINOR_LEN 4
3434 #define MC_CMD_PTP_OUT_TIME_EVENT_SUBSCRIBE_LEN 0
3437 #define MC_CMD_PTP_OUT_TIME_EVENT_UNSUBSCRIBE_LEN 0
3442 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_OFST 0
3443 #define MC_CMD_PTP_OUT_READ_NIC_TIME_SECONDS_LEN 4
3445 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_OFST 0
3446 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MAJOR_LEN 4
3448 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_OFST 4
3449 #define MC_CMD_PTP_OUT_READ_NIC_TIME_NANOSECONDS_LEN 4
3451 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_OFST 4
3452 #define MC_CMD_PTP_OUT_READ_NIC_TIME_MINOR_LEN 4
3457 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_OFST 0
3458 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_SECONDS_LEN 4
3460 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_OFST 0
3461 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_LEN 4
3463 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_OFST 4
3464 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_NANOSECONDS_LEN 4
3466 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_OFST 4
3467 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MINOR_LEN 4
3470 #define MC_CMD_PTP_OUT_READ_NIC_TIME_V2_MAJOR_HI_LEN 4
3475 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_OFST 0
3476 #define MC_CMD_PTP_OUT_STATUS_CLOCK_FREQ_LEN 4
3478 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_OFST 4
3479 #define MC_CMD_PTP_OUT_STATUS_STATS_TX_LEN 4
3482 #define MC_CMD_PTP_OUT_STATUS_STATS_RX_LEN 4
3485 #define MC_CMD_PTP_OUT_STATUS_STATS_TS_LEN 4
3488 #define MC_CMD_PTP_OUT_STATUS_STATS_FM_LEN 4
3491 #define MC_CMD_PTP_OUT_STATUS_STATS_NFM_LEN 4
3494 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFLOW_LEN 4
3497 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_BAD_LEN 4
3500 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MIN_LEN 4
3503 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MAX_LEN 4
3506 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_LAST_LEN 4
3509 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_PER_MEAN_LEN 4
3512 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MIN_LEN 4
3515 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MAX_LEN 4
3518 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_LAST_LEN 4
3521 #define MC_CMD_PTP_OUT_STATUS_STATS_PPS_OFF_MEAN_LEN 4
3527 #define MC_CMD_PTP_OUT_SYNCHRONIZE_LEN(num) (0+20*(num))
3528 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_NUM(len) (((len)-0)/20)
3530 #define MC_CMD_PTP_OUT_SYNCHRONIZE_TIMESET_OFST 0
3536 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_OFST 0
3537 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTSTART_LEN 4
3539 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_OFST 4
3540 #define MC_CMD_PTP_OUT_SYNCHRONIZE_SECONDS_LEN 4
3542 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_OFST 4
3543 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MAJOR_LEN 4
3546 #define MC_CMD_PTP_OUT_SYNCHRONIZE_NANOSECONDS_LEN 4
3549 #define MC_CMD_PTP_OUT_SYNCHRONIZE_MINOR_LEN 4
3552 #define MC_CMD_PTP_OUT_SYNCHRONIZE_HOSTEND_LEN 4
3555 #define MC_CMD_PTP_OUT_SYNCHRONIZE_WAITNS_LEN 4
3560 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_OFST 0
3561 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_RESULT_LEN 4
3563 #define MC_CMD_PTP_MANF_SUCCESS 0x0
3565 #define MC_CMD_PTP_MANF_FPGA_LOAD 0x1
3567 #define MC_CMD_PTP_MANF_FPGA_VERSION 0x2
3569 #define MC_CMD_PTP_MANF_FPGA_REGISTERS 0x3
3571 #define MC_CMD_PTP_MANF_OSCILLATOR 0x4
3573 #define MC_CMD_PTP_MANF_TIMESTAMPS 0x5
3575 #define MC_CMD_PTP_MANF_PACKET_COUNT 0x6
3577 #define MC_CMD_PTP_MANF_FILTER_COUNT 0x7
3579 #define MC_CMD_PTP_MANF_PACKET_ENOUGH 0x8
3581 #define MC_CMD_PTP_MANF_GPIO_TRIGGER 0x9
3583 #define MC_CMD_PTP_MANF_PPS_ENOUGH 0xa
3585 #define MC_CMD_PTP_MANF_PPS_PERIOD 0xb
3587 #define MC_CMD_PTP_MANF_PPS_NS 0xc
3589 #define MC_CMD_PTP_MANF_REGISTERS 0xd
3591 #define MC_CMD_PTP_MANF_CLOCK_READ 0xe
3593 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_OFST 4
3594 #define MC_CMD_PTP_OUT_MANFTEST_BASIC_TEST_EXTOSC_LEN 4
3599 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_OFST 0
3600 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_RESULT_LEN 4
3602 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_OFST 4
3603 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FPGACOUNT_LEN 4
3606 #define MC_CMD_PTP_OUT_MANFTEST_PACKET_TEST_FILTERCOUNT_LEN 4
3612 #define MC_CMD_PTP_OUT_FPGAREAD_LEN(num) (0+1*(num))
3613 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_NUM(len) (((len)-0)/1)
3614 #define MC_CMD_PTP_OUT_FPGAREAD_BUFFER_OFST 0
3621 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_LEN 4
3625 * be assumed. Note this enum is deprecated. Do not add to it- use the
3628 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_OFST 0
3629 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_FORMAT_LEN 4
3631 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_NANOSECONDS 0x0
3633 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_16SECONDS_8NANOSECONDS 0x1
3634 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3635 #define MC_CMD_PTP_OUT_GET_TIME_FORMAT_SECONDS_27FRACTION 0x2
3644 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_OFST 0
3645 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_TIME_FORMAT_LEN 4
3647 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_NANOSECONDS 0x0
3649 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_16SECONDS_8NANOSECONDS 0x1
3650 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3651 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_27FRACTION 0x2
3654 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SECONDS_QTR_NANOSECONDS 0x3
3662 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_OFST 4
3663 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_SYNC_WINDOW_MIN_LEN 4
3666 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_CAPABILITIES_LEN 4
3668 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_REPORT_SYNC_STATUS_LBN 0
3680 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED0_LEN 4
3682 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED1_LEN 4
3684 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_RESERVED2_LEN 4
3693 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_OFST 0
3694 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_TIME_FORMAT_LEN 4
3696 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_NANOSECONDS 0x0
3698 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_16SECONDS_8NANOSECONDS 0x1
3699 /* enum: Major register has units of seconds, minor 2^-27s per tick */
3700 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_27FRACTION 0x2
3703 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SECONDS_QTR_NANOSECONDS 0x3
3711 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_OFST 4
3712 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_SYNC_WINDOW_MIN_LEN 4
3715 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_CAPABILITIES_LEN 4
3717 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_REPORT_SYNC_STATUS_LBN 0
3729 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED0_LEN 4
3731 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED1_LEN 4
3733 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_RESERVED2_LEN 4
3737 * response is not supported a value of -0.1 ns should be assumed, which is
3738 * equivalent to a -10% adjustment.
3743 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_LO_LEN 4
3747 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MIN_HI_LEN 4
3759 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_LO_LEN 4
3763 #define MC_CMD_PTP_OUT_GET_ATTRIBUTES_V2_FREQ_ADJ_MAX_HI_LEN 4
3770 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_OFST 0
3771 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_TRANSMIT_LEN 4
3773 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_OFST 4
3774 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_RECEIVE_LEN 4
3777 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_OUT_LEN 4
3780 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_PPS_IN_LEN 4
3785 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_OFST 0
3786 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_TX_LEN 4
3788 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_OFST 4
3789 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PTP_RX_LEN 4
3792 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_OUT_LEN 4
3795 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_PPS_IN_LEN 4
3796 /* Uncorrected error on non-PTP transmit timestamps in NIC clock format */
3798 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_TX_LEN 4
3799 /* Uncorrected error on non-PTP receive timestamps in NIC clock format */
3801 #define MC_CMD_PTP_OUT_GET_TIMESTAMP_CORRECTIONS_V2_GENERAL_RX_LEN 4
3804 #define MC_CMD_PTP_OUT_MANFTEST_PPS_LEN 4
3806 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_OFST 0
3807 #define MC_CMD_PTP_OUT_MANFTEST_PPS_TEST_RESULT_LEN 4
3812 #define MC_CMD_PTP_OUT_SET_SYNC_STATUS_LEN 0
3817 #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_CURRENT_OFST 0
3818 #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_CURRENT_LEN 4
3820 #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_MAXIMUM_OFST 4
3821 #define MC_CMD_PTP_OUT_GET_SYNC_TIMEOUT_MAXIMUM_LEN 4
3828 #define MC_CMD_GET_BOARD_CFG 0x18
3834 #define MC_CMD_GET_BOARD_CFG_IN_LEN 0
3841 #define MC_CMD_GET_BOARD_CFG_OUT_FW_SUBTYPE_LIST_NUM(len) (((len)-72)/2)
3842 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_OFST 0
3843 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_TYPE_LEN 4
3844 #define MC_CMD_GET_BOARD_CFG_OUT_BOARD_NAME_OFST 4
3850 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT0_LEN 4
3855 #define MC_CMD_GET_BOARD_CFG_OUT_CAPABILITIES_PORT1_LEN 4
3870 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT0_LEN 4
3875 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_COUNT_PORT1_LEN 4
3880 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT0_LEN 4
3885 #define MC_CMD_GET_BOARD_CFG_OUT_MAC_STRIDE_PORT1_LEN 4
3886 /* Siena only. This field contains a 16-bit value for each of the types of
3908 #define MC_CMD_DRV_ATTACH 0x1c
3916 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_OFST 0
3917 #define MC_CMD_DRV_ATTACH_IN_NEW_STATE_LEN 4
3918 #define MC_CMD_DRV_ATTACH_OFST 0
3919 #define MC_CMD_DRV_ATTACH_LBN 0
3921 #define MC_CMD_DRV_ATTACH_IN_ATTACH_OFST 0
3922 #define MC_CMD_DRV_ATTACH_IN_ATTACH_LBN 0
3924 #define MC_CMD_DRV_PREBOOT_OFST 0
3927 #define MC_CMD_DRV_ATTACH_IN_PREBOOT_OFST 0
3930 #define MC_CMD_DRV_ATTACH_IN_SUBVARIANT_AWARE_OFST 0
3933 #define MC_CMD_DRV_ATTACH_IN_WANT_VI_SPREADING_OFST 0
3936 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_OFST 0
3937 #define MC_CMD_DRV_ATTACH_IN_WANT_V2_LINKCHANGES_LBN 4
3939 #define MC_CMD_DRV_ATTACH_IN_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
3942 #define MC_CMD_DRV_ATTACH_IN_WANT_TX_ONLY_SPREADING_OFST 0
3945 /* 1 to set new state, or 0 to just report the existing state */
3946 #define MC_CMD_DRV_ATTACH_IN_UPDATE_OFST 4
3947 #define MC_CMD_DRV_ATTACH_IN_UPDATE_LEN 4
3950 #define MC_CMD_DRV_ATTACH_IN_FIRMWARE_ID_LEN 4
3952 #define MC_CMD_FW_FULL_FEATURED 0x0
3954 #define MC_CMD_FW_LOW_LATENCY 0x1
3956 #define MC_CMD_FW_PACKED_STREAM 0x2
3960 #define MC_CMD_FW_HIGH_TX_RATE 0x3
3962 #define MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4
3966 #define MC_CMD_FW_RULES_ENGINE 0x5
3968 #define MC_CMD_FW_DPDK 0x6
3969 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
3972 #define MC_CMD_FW_L3XUDP 0x7
3976 * (i.e. non-production) builds.
3978 #define MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe
3979 /* enum: Only this option is allowed for non-admin functions */
3980 #define MC_CMD_FW_DONT_CARE 0xffffffff
3987 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_OFST 0
3988 #define MC_CMD_DRV_ATTACH_IN_V2_NEW_STATE_LEN 4
3989 /* MC_CMD_DRV_ATTACH_OFST 0 */
3990 /* MC_CMD_DRV_ATTACH_LBN 0 */
3992 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_OFST 0
3993 #define MC_CMD_DRV_ATTACH_IN_V2_ATTACH_LBN 0
3995 /* MC_CMD_DRV_PREBOOT_OFST 0 */
3998 #define MC_CMD_DRV_ATTACH_IN_V2_PREBOOT_OFST 0
4001 #define MC_CMD_DRV_ATTACH_IN_V2_SUBVARIANT_AWARE_OFST 0
4004 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_VI_SPREADING_OFST 0
4007 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_OFST 0
4008 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_V2_LINKCHANGES_LBN 4
4010 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_RX_VI_SPREADING_INHIBIT_OFST 0
4013 #define MC_CMD_DRV_ATTACH_IN_V2_WANT_TX_ONLY_SPREADING_OFST 0
4016 /* 1 to set new state, or 0 to just report the existing state */
4017 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_OFST 4
4018 #define MC_CMD_DRV_ATTACH_IN_V2_UPDATE_LEN 4
4021 #define MC_CMD_DRV_ATTACH_IN_V2_FIRMWARE_ID_LEN 4
4023 /* MC_CMD_FW_FULL_FEATURED 0x0 */
4025 /* MC_CMD_FW_LOW_LATENCY 0x1 */
4027 /* MC_CMD_FW_PACKED_STREAM 0x2 */
4031 /* MC_CMD_FW_HIGH_TX_RATE 0x3 */
4033 /* MC_CMD_FW_PACKED_STREAM_HASH_MODE_1 0x4 */
4037 /* MC_CMD_FW_RULES_ENGINE 0x5 */
4039 /* MC_CMD_FW_DPDK 0x6 */
4040 /* enum: Prefer to use "l3xudp" custom datapath firmware (see SF-119495-PD and
4043 /* MC_CMD_FW_L3XUDP 0x7 */
4047 * (i.e. non-production) builds.
4049 /* MC_CMD_FW_KEEP_CURRENT_EFTEST_ONLY 0xfffffffe */
4050 /* enum: Only this option is allowed for non-admin functions */
4051 /* MC_CMD_FW_DONT_CARE 0xffffffff */
4052 /* Version of the driver to be reported by management protocols (e.g. NC-SI)
4053 * handled by the NIC. This is a zero-terminated ASCII string.
4059 #define MC_CMD_DRV_ATTACH_OUT_LEN 4
4061 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_OFST 0
4062 #define MC_CMD_DRV_ATTACH_OUT_OLD_STATE_LEN 4
4067 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_OFST 0
4068 #define MC_CMD_DRV_ATTACH_EXT_OUT_OLD_STATE_LEN 4
4070 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_OFST 4
4071 #define MC_CMD_DRV_ATTACH_EXT_OUT_FUNC_FLAGS_LEN 4
4073 /* enum: Labels the lowest-numbered function visible to the OS */
4074 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_PRIMARY 0x0
4078 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_LINKCTRL 0x1
4080 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TRUSTED 0x2
4084 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_NO_ACTIVE_PORT 0x3
4089 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_VI_SPREADING_ENABLED 0x4
4091 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_RX_VI_SPREADING_INHIBITED 0x5
4092 /* enum: If set, indicates that TX only spreading is enabled. Even-numbered
4093 * TXQs will use one engine, and odd-numbered TXQs will use the other. This
4094 * also has the effect that only even-numbered RXQs will receive traffic.
4096 #define MC_CMD_DRV_ATTACH_EXT_OUT_FLAG_TX_ONLY_VI_SPREADING_ENABLED 0x5
4101 * Generic per-port reset. There is no equivalent for per-board reset. Locks
4102 * required: None; Return code: 0, ETIME. NOTE: This command is deprecated -
4105 #define MC_CMD_PORT_RESET 0x20
4111 #define MC_CMD_PORT_RESET_IN_LEN 0
4114 #define MC_CMD_PORT_RESET_OUT_LEN 0
4119 * Generic per-resource reset. There is no equivalent for per-board reset.
4120 * Locks required: None; Return code: 0, ETIME. NOTE: This command is an
4123 #define MC_CMD_ENTITY_RESET 0x20
4127 #define MC_CMD_ENTITY_RESET_IN_LEN 4
4131 #define MC_CMD_ENTITY_RESET_IN_FLAG_OFST 0
4132 #define MC_CMD_ENTITY_RESET_IN_FLAG_LEN 4
4133 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_OFST 0
4134 #define MC_CMD_ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET_LBN 0
4138 #define MC_CMD_ENTITY_RESET_OUT_LEN 0
4145 #define MC_CMD_PUTS 0x23
4155 #define MC_CMD_PUTS_IN_STRING_NUM(len) (((len)-12)/1)
4156 #define MC_CMD_PUTS_IN_DEST_OFST 0
4157 #define MC_CMD_PUTS_IN_DEST_LEN 4
4158 #define MC_CMD_PUTS_IN_UART_OFST 0
4159 #define MC_CMD_PUTS_IN_UART_LBN 0
4161 #define MC_CMD_PUTS_IN_PORT_OFST 0
4164 #define MC_CMD_PUTS_IN_DHOST_OFST 4
4173 #define MC_CMD_PUTS_OUT_LEN 0
4181 #define MC_CMD_GET_PHY_CFG 0x24
4187 #define MC_CMD_GET_PHY_CFG_IN_LEN 0
4195 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_OFST 0
4197 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_OFST 0
4198 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_LEN 4
4199 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LO_LBN 0
4201 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_OFST 4
4202 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_HI_LEN 4
4206 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
4207 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
4208 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
4209 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
4212 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
4214 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
4215 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
4217 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
4219 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
4222 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
4224 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LINK_END_OFST 4
4225 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_LINK_END_LEN 4
4226 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_OFST 0
4228 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_OFST 0
4229 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_LEN 4
4230 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_LO_LBN 0
4232 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_OFST 4
4233 #define MC_CMD_GET_PHY_CFG_IN_V2_TARGET_FLAT_HI_LEN 4
4240 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_OFST 0
4241 #define MC_CMD_GET_PHY_CFG_OUT_FLAGS_LEN 4
4242 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_OFST 0
4243 #define MC_CMD_GET_PHY_CFG_OUT_PRESENT_LBN 0
4245 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_SHORT_OFST 0
4248 #define MC_CMD_GET_PHY_CFG_OUT_BIST_CABLE_LONG_OFST 0
4251 #define MC_CMD_GET_PHY_CFG_OUT_LOWPOWER_OFST 0
4254 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_OFST 0
4255 #define MC_CMD_GET_PHY_CFG_OUT_POWEROFF_LBN 4
4257 #define MC_CMD_GET_PHY_CFG_OUT_TXDIS_OFST 0
4260 #define MC_CMD_GET_PHY_CFG_OUT_BIST_OFST 0
4264 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_OFST 4
4265 #define MC_CMD_GET_PHY_CFG_OUT_TYPE_LEN 4
4268 #define MC_CMD_GET_PHY_CFG_OUT_SUPPORTED_CAP_LEN 4
4279 #define MC_CMD_PHY_CAP_100FDX_LBN 4
4337 #define MC_CMD_GET_PHY_CFG_OUT_CHANNEL_LEN 4
4340 #define MC_CMD_GET_PHY_CFG_OUT_PRT_LEN 4
4343 #define MC_CMD_GET_PHY_CFG_OUT_STATS_MASK_LEN 4
4349 #define MC_CMD_GET_PHY_CFG_OUT_MEDIA_TYPE_LEN 4
4351 #define MC_CMD_MEDIA_XAUI 0x1
4353 #define MC_CMD_MEDIA_CX4 0x2
4355 #define MC_CMD_MEDIA_KX4 0x3
4357 #define MC_CMD_MEDIA_XFP 0x4
4359 #define MC_CMD_MEDIA_SFP_PLUS 0x5
4361 #define MC_CMD_MEDIA_BASE_T 0x6
4363 #define MC_CMD_MEDIA_QSFP_PLUS 0x7
4365 #define MC_CMD_MEDIA_DSFP 0x8
4367 #define MC_CMD_GET_PHY_CFG_OUT_MMD_MASK_LEN 4
4370 #define MC_CMD_MMD_CLAUSE22 0x0
4371 #define MC_CMD_MMD_CLAUSE45_PMAPMD 0x1 /* enum */
4372 #define MC_CMD_MMD_CLAUSE45_WIS 0x2 /* enum */
4373 #define MC_CMD_MMD_CLAUSE45_PCS 0x3 /* enum */
4374 #define MC_CMD_MMD_CLAUSE45_PHYXS 0x4 /* enum */
4375 #define MC_CMD_MMD_CLAUSE45_DTEXS 0x5 /* enum */
4376 #define MC_CMD_MMD_CLAUSE45_TC 0x6 /* enum */
4377 #define MC_CMD_MMD_CLAUSE45_AN 0x7 /* enum */
4379 #define MC_CMD_MMD_CLAUSE45_C22EXT 0x1d
4380 #define MC_CMD_MMD_CLAUSE45_VEND1 0x1e /* enum */
4381 #define MC_CMD_MMD_CLAUSE45_VEND2 0x1f /* enum */
4389 * Return code: 0, EINVAL, EACCES (if PHY_LOCK is not held)
4391 #define MC_CMD_START_BIST 0x25
4397 #define MC_CMD_START_BIST_IN_LEN 4
4399 #define MC_CMD_START_BIST_IN_TYPE_OFST 0
4400 #define MC_CMD_START_BIST_IN_TYPE_LEN 4
4402 #define MC_CMD_PHY_BIST_CABLE_SHORT 0x1
4404 #define MC_CMD_PHY_BIST_CABLE_LONG 0x2
4406 #define MC_CMD_BPX_SERDES_BIST 0x3
4408 #define MC_CMD_MC_LOOPBACK_BIST 0x4
4410 #define MC_CMD_PHY_BIST 0x5
4412 #define MC_CMD_MC_MEM_BIST 0x6
4414 #define MC_CMD_PORT_MEM_BIST 0x7
4416 #define MC_CMD_REG_BIST 0x8
4419 #define MC_CMD_START_BIST_OUT_LEN 0
4428 * OUT.RESULT. Locks required: PHY_LOCK if doing a PHY BIST. Return code: 0,
4431 #define MC_CMD_POLL_BIST 0x26
4437 #define MC_CMD_POLL_BIST_IN_LEN 0
4442 #define MC_CMD_POLL_BIST_OUT_RESULT_OFST 0
4443 #define MC_CMD_POLL_BIST_OUT_RESULT_LEN 4
4445 #define MC_CMD_POLL_BIST_RUNNING 0x1
4447 #define MC_CMD_POLL_BIST_PASSED 0x2
4449 #define MC_CMD_POLL_BIST_FAILED 0x3
4450 /* enum: Timed-out. */
4451 #define MC_CMD_POLL_BIST_TIMEOUT 0x4
4452 #define MC_CMD_POLL_BIST_OUT_PRIVATE_OFST 4
4453 #define MC_CMD_POLL_BIST_OUT_PRIVATE_LEN 4
4458 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
4459 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
4462 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_OFST 4
4463 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_A_LEN 4
4465 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_B_LEN 4
4467 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_C_LEN 4
4469 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_LENGTH_D_LEN 4
4472 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_A_LEN 4
4474 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OK 0x1
4476 #define MC_CMD_POLL_BIST_SFT9001_PAIR_OPEN 0x2
4477 /* enum: Intra-pair short. */
4478 #define MC_CMD_POLL_BIST_SFT9001_INTRA_PAIR_SHORT 0x3
4479 /* enum: Inter-pair short. */
4480 #define MC_CMD_POLL_BIST_SFT9001_INTER_PAIR_SHORT 0x4
4482 #define MC_CMD_POLL_BIST_SFT9001_PAIR_BUSY 0x9
4485 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_B_LEN 4
4490 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_C_LEN 4
4495 #define MC_CMD_POLL_BIST_OUT_SFT9001_CABLE_STATUS_D_LEN 4
4502 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
4503 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
4506 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_OFST 4
4507 #define MC_CMD_POLL_BIST_OUT_MRSFP_TEST_LEN 4
4509 #define MC_CMD_POLL_BIST_MRSFP_TEST_COMPLETE 0x0
4511 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_WRITE 0x1
4513 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_IO_EXP 0x2
4515 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_OFF_I2C_NO_ACCESS_MODULE 0x3
4517 #define MC_CMD_POLL_BIST_MRSFP_TEST_IO_EXP_I2C_CONFIGURE 0x4
4519 #define MC_CMD_POLL_BIST_MRSFP_TEST_BUS_SWITCH_I2C_NO_CROSSTALK 0x5
4521 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_PRESENCE 0x6
4523 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_I2C_ACCESS 0x7
4525 #define MC_CMD_POLL_BIST_MRSFP_TEST_MODULE_ID_SANE_VALUE 0x8
4530 /* MC_CMD_POLL_BIST_OUT_RESULT_OFST 0 */
4531 /* MC_CMD_POLL_BIST_OUT_RESULT_LEN 4 */
4534 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_OFST 4
4535 #define MC_CMD_POLL_BIST_OUT_MEM_TEST_LEN 4
4537 #define MC_CMD_POLL_BIST_MEM_COMPLETE 0x0
4538 /* enum: RAM test - walk ones. */
4539 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ONES 0x1
4540 /* enum: RAM test - walk zeros. */
4541 #define MC_CMD_POLL_BIST_MEM_MEM_WALK_ZEROS 0x2
4542 /* enum: RAM test - walking inversions zeros/ones. */
4543 #define MC_CMD_POLL_BIST_MEM_MEM_INV_ZERO_ONE 0x3
4544 /* enum: RAM test - walking inversions checkerboard. */
4545 #define MC_CMD_POLL_BIST_MEM_MEM_INV_CHKBOARD 0x4
4546 /* enum: Register test - set / clear individual bits. */
4547 #define MC_CMD_POLL_BIST_MEM_REG 0x5
4549 #define MC_CMD_POLL_BIST_MEM_ECC 0x6
4552 #define MC_CMD_POLL_BIST_OUT_MEM_ADDR_LEN 4
4555 #define MC_CMD_POLL_BIST_OUT_MEM_BUS_LEN 4
4557 #define MC_CMD_POLL_BIST_MEM_BUS_MC 0x0
4559 #define MC_CMD_POLL_BIST_MEM_BUS_CSR 0x1
4561 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX 0x2
4563 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX0 0x3
4565 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_TX1 0x4
4567 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX 0x5
4569 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_TX 0x6
4571 #define MC_CMD_POLL_BIST_MEM_BUS_DPCPU_RX1 0x7
4573 #define MC_CMD_POLL_BIST_MEM_BUS_DICPU_RX1 0x8
4576 #define MC_CMD_POLL_BIST_OUT_MEM_EXPECT_LEN 4
4579 #define MC_CMD_POLL_BIST_OUT_MEM_ACTUAL_LEN 4
4582 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_LEN 4
4585 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_PARITY_LEN 4
4588 #define MC_CMD_POLL_BIST_OUT_MEM_ECC_FATAL_LEN 4
4595 #define MC_CMD_GET_LOOPBACK_MODES 0x28
4601 #define MC_CMD_GET_LOOPBACK_MODES_IN_LEN 0
4609 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_OFST 0
4611 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_OFST 0
4612 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_LEN 4
4613 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LO_LBN 0
4615 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_OFST 4
4616 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_HI_LEN 4
4620 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
4621 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
4622 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
4623 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
4626 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
4628 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
4629 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
4631 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
4633 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
4636 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
4638 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LINK_END_OFST 4
4639 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_LINK_END_LEN 4
4640 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_OFST 0
4642 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_OFST 0
4643 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_LEN 4
4644 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_LO_LBN 0
4646 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_OFST 4
4647 #define MC_CMD_GET_LOOPBACK_MODES_IN_V2_TARGET_FLAT_HI_LEN 4
4654 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_OFST 0
4656 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_OFST 0
4657 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LEN 4
4658 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_LO_LBN 0
4660 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_OFST 4
4661 #define MC_CMD_GET_LOOPBACK_MODES_OUT_100M_HI_LEN 4
4666 #define MC_CMD_LOOPBACK_NONE 0x0
4668 #define MC_CMD_LOOPBACK_DATA 0x1
4670 #define MC_CMD_LOOPBACK_GMAC 0x2
4672 #define MC_CMD_LOOPBACK_XGMII 0x3
4674 #define MC_CMD_LOOPBACK_XGXS 0x4
4676 #define MC_CMD_LOOPBACK_XAUI 0x5
4678 #define MC_CMD_LOOPBACK_GMII 0x6
4680 #define MC_CMD_LOOPBACK_SGMII 0x7
4682 #define MC_CMD_LOOPBACK_XGBR 0x8
4684 #define MC_CMD_LOOPBACK_XFI 0x9
4686 #define MC_CMD_LOOPBACK_XAUI_FAR 0xa
4688 #define MC_CMD_LOOPBACK_GMII_FAR 0xb
4690 #define MC_CMD_LOOPBACK_SGMII_FAR 0xc
4692 #define MC_CMD_LOOPBACK_XFI_FAR 0xd
4694 #define MC_CMD_LOOPBACK_GPHY 0xe
4696 #define MC_CMD_LOOPBACK_PHYXS 0xf
4698 #define MC_CMD_LOOPBACK_PCS 0x10
4699 /* enum: PMA-PMD. */
4700 #define MC_CMD_LOOPBACK_PMAPMD 0x11
4701 /* enum: Cross-Port. */
4702 #define MC_CMD_LOOPBACK_XPORT 0x12
4703 /* enum: XGMII-Wireside. */
4704 #define MC_CMD_LOOPBACK_XGMII_WS 0x13
4706 #define MC_CMD_LOOPBACK_XAUI_WS 0x14
4708 #define MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15
4710 #define MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16
4712 #define MC_CMD_LOOPBACK_GMII_WS 0x17
4714 #define MC_CMD_LOOPBACK_XFI_WS 0x18
4716 #define MC_CMD_LOOPBACK_XFI_WS_FAR 0x19
4718 #define MC_CMD_LOOPBACK_PHYXS_WS 0x1a
4719 /* enum: PMA lanes MAC-Serdes. */
4720 #define MC_CMD_LOOPBACK_PMA_INT 0x1b
4722 #define MC_CMD_LOOPBACK_SD_NEAR 0x1c
4724 #define MC_CMD_LOOPBACK_SD_FAR 0x1d
4725 /* enum: PMA lanes MAC-Serdes Wireside. */
4726 #define MC_CMD_LOOPBACK_PMA_INT_WS 0x1e
4728 #define MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f
4730 #define MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20
4732 #define MC_CMD_LOOPBACK_SD_FEP_WS 0x21
4734 #define MC_CMD_LOOPBACK_SD_FES_WS 0x22
4736 #define MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23
4738 #define MC_CMD_LOOPBACK_DATA_WS 0x24
4742 #define MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25
4747 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_LO_LEN 4
4751 #define MC_CMD_GET_LOOPBACK_MODES_OUT_1G_HI_LEN 4
4761 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_LO_LEN 4
4765 #define MC_CMD_GET_LOOPBACK_MODES_OUT_10G_HI_LEN 4
4775 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_LO_LEN 4
4779 #define MC_CMD_GET_LOOPBACK_MODES_OUT_SUGGESTED_HI_LEN 4
4789 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_LO_LEN 4
4793 #define MC_CMD_GET_LOOPBACK_MODES_OUT_40G_HI_LEN 4
4805 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_OFST 0
4807 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_OFST 0
4808 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LEN 4
4809 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_LO_LBN 0
4811 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_OFST 4
4812 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100M_HI_LEN 4
4817 /* MC_CMD_LOOPBACK_NONE 0x0 */
4819 /* MC_CMD_LOOPBACK_DATA 0x1 */
4821 /* MC_CMD_LOOPBACK_GMAC 0x2 */
4823 /* MC_CMD_LOOPBACK_XGMII 0x3 */
4825 /* MC_CMD_LOOPBACK_XGXS 0x4 */
4827 /* MC_CMD_LOOPBACK_XAUI 0x5 */
4829 /* MC_CMD_LOOPBACK_GMII 0x6 */
4831 /* MC_CMD_LOOPBACK_SGMII 0x7 */
4833 /* MC_CMD_LOOPBACK_XGBR 0x8 */
4835 /* MC_CMD_LOOPBACK_XFI 0x9 */
4837 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
4839 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
4841 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
4843 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
4845 /* MC_CMD_LOOPBACK_GPHY 0xe */
4847 /* MC_CMD_LOOPBACK_PHYXS 0xf */
4849 /* MC_CMD_LOOPBACK_PCS 0x10 */
4850 /* enum: PMA-PMD. */
4851 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
4852 /* enum: Cross-Port. */
4853 /* MC_CMD_LOOPBACK_XPORT 0x12 */
4854 /* enum: XGMII-Wireside. */
4855 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
4857 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
4859 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
4861 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
4863 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
4865 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
4867 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
4869 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
4870 /* enum: PMA lanes MAC-Serdes. */
4871 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
4873 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
4875 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
4876 /* enum: PMA lanes MAC-Serdes Wireside. */
4877 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
4879 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
4881 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
4883 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
4885 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
4887 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
4889 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
4893 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
4898 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_LO_LEN 4
4902 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_1G_HI_LEN 4
4912 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_LO_LEN 4
4916 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_10G_HI_LEN 4
4926 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_LO_LEN 4
4930 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_SUGGESTED_HI_LEN 4
4940 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_LO_LEN 4
4944 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_40G_HI_LEN 4
4954 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_LO_LEN 4
4958 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_25G_HI_LEN 4
4968 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_LO_LEN 4
4972 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_50G_HI_LEN 4
4982 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_LO_LEN 4
4986 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V2_100G_HI_LEN 4
4998 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_OFST 0
5000 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_OFST 0
5001 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_LEN 4
5002 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_LO_LBN 0
5004 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_OFST 4
5005 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100M_HI_LEN 4
5010 /* MC_CMD_LOOPBACK_NONE 0x0 */
5012 /* MC_CMD_LOOPBACK_DATA 0x1 */
5014 /* MC_CMD_LOOPBACK_GMAC 0x2 */
5016 /* MC_CMD_LOOPBACK_XGMII 0x3 */
5018 /* MC_CMD_LOOPBACK_XGXS 0x4 */
5020 /* MC_CMD_LOOPBACK_XAUI 0x5 */
5022 /* MC_CMD_LOOPBACK_GMII 0x6 */
5024 /* MC_CMD_LOOPBACK_SGMII 0x7 */
5026 /* MC_CMD_LOOPBACK_XGBR 0x8 */
5028 /* MC_CMD_LOOPBACK_XFI 0x9 */
5030 /* MC_CMD_LOOPBACK_XAUI_FAR 0xa */
5032 /* MC_CMD_LOOPBACK_GMII_FAR 0xb */
5034 /* MC_CMD_LOOPBACK_SGMII_FAR 0xc */
5036 /* MC_CMD_LOOPBACK_XFI_FAR 0xd */
5038 /* MC_CMD_LOOPBACK_GPHY 0xe */
5040 /* MC_CMD_LOOPBACK_PHYXS 0xf */
5042 /* MC_CMD_LOOPBACK_PCS 0x10 */
5043 /* enum: PMA-PMD. */
5044 /* MC_CMD_LOOPBACK_PMAPMD 0x11 */
5045 /* enum: Cross-Port. */
5046 /* MC_CMD_LOOPBACK_XPORT 0x12 */
5047 /* enum: XGMII-Wireside. */
5048 /* MC_CMD_LOOPBACK_XGMII_WS 0x13 */
5050 /* MC_CMD_LOOPBACK_XAUI_WS 0x14 */
5052 /* MC_CMD_LOOPBACK_XAUI_WS_FAR 0x15 */
5054 /* MC_CMD_LOOPBACK_XAUI_WS_NEAR 0x16 */
5056 /* MC_CMD_LOOPBACK_GMII_WS 0x17 */
5058 /* MC_CMD_LOOPBACK_XFI_WS 0x18 */
5060 /* MC_CMD_LOOPBACK_XFI_WS_FAR 0x19 */
5062 /* MC_CMD_LOOPBACK_PHYXS_WS 0x1a */
5063 /* enum: PMA lanes MAC-Serdes. */
5064 /* MC_CMD_LOOPBACK_PMA_INT 0x1b */
5066 /* MC_CMD_LOOPBACK_SD_NEAR 0x1c */
5068 /* MC_CMD_LOOPBACK_SD_FAR 0x1d */
5069 /* enum: PMA lanes MAC-Serdes Wireside. */
5070 /* MC_CMD_LOOPBACK_PMA_INT_WS 0x1e */
5072 /* MC_CMD_LOOPBACK_SD_FEP2_WS 0x1f */
5074 /* MC_CMD_LOOPBACK_SD_FEP1_5_WS 0x20 */
5076 /* MC_CMD_LOOPBACK_SD_FEP_WS 0x21 */
5078 /* MC_CMD_LOOPBACK_SD_FES_WS 0x22 */
5080 /* MC_CMD_LOOPBACK_AOE_INT_NEAR 0x23 */
5082 /* MC_CMD_LOOPBACK_DATA_WS 0x24 */
5086 /* MC_CMD_LOOPBACK_FORCE_EXT_LINK 0x25 */
5091 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_LO_LEN 4
5095 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_1G_HI_LEN 4
5105 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_LO_LEN 4
5109 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_10G_HI_LEN 4
5119 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_LO_LEN 4
5123 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_SUGGESTED_HI_LEN 4
5133 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_LO_LEN 4
5137 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_40G_HI_LEN 4
5147 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_LO_LEN 4
5151 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_25G_HI_LEN 4
5161 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_LO_LEN 4
5165 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_50G_HI_LEN 4
5175 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_LO_LEN 4
5179 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_100G_HI_LEN 4
5189 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_LO_LEN 4
5193 #define MC_CMD_GET_LOOPBACK_MODES_OUT_V3_200G_HI_LEN 4
5200 /* AN_TYPE structuredef: Auto-negotiation types defined in IEEE802.3 */
5201 #define AN_TYPE_LEN 4
5202 #define AN_TYPE_TYPE_OFST 0
5203 #define AN_TYPE_TYPE_LEN 4
5205 #define MC_CMD_AN_NONE 0x0
5206 /* enum: Clause 28 - BASE-T */
5207 #define MC_CMD_AN_CLAUSE28 0x1
5208 /* enum: Clause 37 - BASE-X */
5209 #define MC_CMD_AN_CLAUSE37 0x2
5210 /* enum: Clause 73 - BASE-R startup protocol for backplane and copper cable
5211 * assemblies. Includes Clause 72/Clause 92 link-training.
5213 #define MC_CMD_AN_CLAUSE73 0x3
5214 #define AN_TYPE_TYPE_LBN 0
5219 #define FEC_TYPE_LEN 4
5220 #define FEC_TYPE_TYPE_OFST 0
5221 #define FEC_TYPE_TYPE_LEN 4
5223 #define MC_CMD_FEC_NONE 0x0
5224 /* enum: IEEE 802.3, Clause 74 BASE-R FEC (a.k.a Firecode) */
5225 #define MC_CMD_FEC_BASER 0x1
5226 /* enum: IEEE 802.3, Clause 91/Clause 108 Reed-Solomon FEC */
5227 #define MC_CMD_FEC_RS 0x2
5228 /* enum: IEEE 802.3, Clause 161, interleaved RS-FEC sublayer for 100GBASE-R
5231 #define MC_CMD_FEC_IEEE_RS_INT 0x3
5232 /* enum: Ethernet Consortium, Low Latency RS-FEC. RS(272, 258). Replaces FEC
5236 #define MC_CMD_FEC_ETCS_RS_LL 0x4
5238 #define MC_CMD_FEC_AUTO 0x5
5239 #define FEC_TYPE_TYPE_LBN 0
5255 #define MC_CMD_ETH_TECH_TECH_OFST 0
5257 /* enum: 1000BASE-KX - 1000BASE-X PCS/PMA over an electrical backplane PMD. See
5260 #define MC_CMD_ETH_TECH_1000BASEKX 0x0
5261 /* enum: 10GBASE-R - PCS/PMA over an electrical backplane PMD. Refer to IEEE
5264 #define MC_CMD_ETH_TECH_10GBASE_KR 0x1
5265 /* enum: 40GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5268 #define MC_CMD_ETH_TECH_40GBASE_KR4 0x2
5269 /* enum: 40GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
5272 #define MC_CMD_ETH_TECH_40GBASE_CR4 0x3
5273 /* enum: 40GBASE-R PCS/PMA over 4 lane multimode fiber PMD as specified in
5276 #define MC_CMD_ETH_TECH_40GBASE_SR4 0x4
5277 /* enum: 40GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD with long
5280 #define MC_CMD_ETH_TECH_40GBASE_LR4 0x5
5281 /* enum: 25GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
5284 #define MC_CMD_ETH_TECH_25GBASE_CR 0x6
5285 /* enum: 25GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5288 #define MC_CMD_ETH_TECH_25GBASE_KR 0x7
5289 /* enum: 25GBASE-R PCS/PMA over multimode fiber PMD. Refer to IEEE 802.3 Clause
5292 #define MC_CMD_ETH_TECH_25GBASE_SR 0x8
5293 /* enum: An Ethernet Physical layer operating at 50 Gb/s on twin-axial copper
5296 #define MC_CMD_ETH_TECH_50GBASE_CR2 0x9
5300 #define MC_CMD_ETH_TECH_50GBASE_KR2 0xa
5301 /* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5304 #define MC_CMD_ETH_TECH_100GBASE_KR4 0xb
5305 /* enum: 100GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
5308 #define MC_CMD_ETH_TECH_100GBASE_SR4 0xc
5309 /* enum: 100GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD. See
5312 #define MC_CMD_ETH_TECH_100GBASE_CR4 0xd
5313 /* enum: 100GBASE-R PCS/PMA over 4 WDM lane single mode fiber PMD, with
5316 #define MC_CMD_ETH_TECH_100GBASE_LR4_ER4 0xe
5320 #define MC_CMD_ETH_TECH_50GBASE_SR2 0xf
5324 #define MC_CMD_ETH_TECH_1000BASEX 0x10
5325 /* enum: Non-standardised. 10G direct attach */
5326 #define MC_CMD_ETH_TECH_10GBASE_CR 0x11
5327 /* enum: 10GBASE-SR fiber over 850nm optics. See IEEE 802.3 Clause 52 */
5328 #define MC_CMD_ETH_TECH_10GBASE_SR 0x12
5329 /* enum: 10GBASE-LR fiber over 1310nm optics. See IEEE 802.3 Clause 52 */
5330 #define MC_CMD_ETH_TECH_10GBASE_LR 0x13
5331 /* enum: 10GBASE-LRM fiber over 1310 nm optics. See IEEE 802.3 Clause 68 */
5332 #define MC_CMD_ETH_TECH_10GBASE_LRM 0x14
5333 /* enum: 10GBASE-ER fiber over 1550nm optics. See IEEE 802.3 Clause 52 */
5334 #define MC_CMD_ETH_TECH_10GBASE_ER 0x15
5335 /* enum: 50GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5338 #define MC_CMD_ETH_TECH_50GBASE_KR 0x16
5339 /* enum: 50GBASE-SR PCS/PMA over multimode fiber PMD as specified in Clause 138
5341 #define MC_CMD_ETH_TECH_50GBASE_SR 0x17
5342 /* enum: 50GBASE-CR PCS/PMA over shielded copper balanced cable PMD. See IEEE
5345 #define MC_CMD_ETH_TECH_50GBASE_CR 0x18
5346 /* enum: 50GBASE-R PCS/PMA over single mode fiber PMD as specified in Clause
5349 #define MC_CMD_ETH_TECH_50GBASE_LR_ER_FR 0x19
5350 /* enum: 100 Gb/s PHY using 100GBASE-R encoding over single-mode fiber with
5353 #define MC_CMD_ETH_TECH_50GBASE_DR 0x1a
5354 /* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5357 #define MC_CMD_ETH_TECH_100GBASE_KR2 0x1b
5358 /* enum: 100GBASE-R PCS/PMA over 2 lane multimode fiber PMD. See IEEE 802.3
5361 #define MC_CMD_ETH_TECH_100GBASE_SR2 0x1c
5362 /* enum: 100GBASE-R PCS/PMA over 2 lane shielded copper balanced cable PMD. See
5365 #define MC_CMD_ETH_TECH_100GBASE_CR2 0x1d
5367 #define MC_CMD_ETH_TECH_100GBASE_LR2_ER2_FR2 0x1e
5369 #define MC_CMD_ETH_TECH_100GBASE_DR2 0x1f
5370 /* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5373 #define MC_CMD_ETH_TECH_200GBASE_KR4 0x20
5374 /* enum: 200GBASE-R PCS/PMA over 4 lane multimode fiber PMD. See IEEE 802.3
5377 #define MC_CMD_ETH_TECH_200GBASE_SR4 0x21
5378 /* enum: 200GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD as specified
5381 #define MC_CMD_ETH_TECH_200GBASE_LR4_ER4_FR4 0x22
5382 /* enum: 200GBASE-R PCS/PMA over 4-lane single-mode fiber PMD. See IEEE 802.3
5385 #define MC_CMD_ETH_TECH_200GBASE_DR4 0x23
5386 /* enum: 200GBASE-R PCS/PMA over 4 lane shielded copper balanced cable PMD as
5389 #define MC_CMD_ETH_TECH_200GBASE_CR4 0x24
5390 /* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-KR8 PMD uses
5393 #define MC_CMD_ETH_TECH_400GBASE_KR8 0x25
5394 /* enum: 400GBASE-R PCS/PMA over 8-lane multimode fiber PMD. See IEEE 802.3
5397 #define MC_CMD_ETH_TECH_400GBASE_SR8 0x26
5398 /* enum: 400GBASE-R PCS/PMA over 8 WDM lane single-mode fiber PMD. See IEEE
5401 #define MC_CMD_ETH_TECH_400GBASE_LR8_ER8_FR8 0x27
5403 #define MC_CMD_ETH_TECH_400GBASE_DR8 0x28
5404 /* enum: Ethernet Technology Consortium 400G AN Spec. 400GBASE-CR8 PMD uses
5407 #define MC_CMD_ETH_TECH_400GBASE_CR8 0x29
5408 /* enum: 100GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3ck
5411 #define MC_CMD_ETH_TECH_100GBASE_KR 0x2a
5415 #define MC_CMD_ETH_TECH_100GBASE_SR 0x2b
5416 /* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
5419 #define MC_CMD_ETH_TECH_100GBASE_LR_ER_FR 0x2c
5420 /* enum: 100GBASE-R PCS/PMA over shielded balanced copper cable PMD. See IEEE
5423 #define MC_CMD_ETH_TECH_100GBASE_CR 0x2d
5424 /* enum: 100G PMD together with single-mode fiber medium. See IEEE 802.3 Clause
5427 #define MC_CMD_ETH_TECH_100GBASE_DR 0x2e
5428 /* enum: 200GBASE-R PCS/PMA over an electrical backplane PMD as specified in
5431 #define MC_CMD_ETH_TECH_200GBASE_KR2 0x2f
5435 #define MC_CMD_ETH_TECH_200GBASE_SR2 0x30
5437 #define MC_CMD_ETH_TECH_200GBASE_LR2_ER2_FR2 0x31
5439 #define MC_CMD_ETH_TECH_200GBASE_DR2 0x32
5440 /* enum: 200GBASE-R PCS/PMA over 2 lane shielded balanced copper cable PMD as
5443 #define MC_CMD_ETH_TECH_200GBASE_CR2 0x33
5444 /* enum: 400GBASE-R PCS/PMA over an electrical backplane PMD. See IEEE 802.3
5447 #define MC_CMD_ETH_TECH_400GBASE_KR4 0x34
5451 #define MC_CMD_ETH_TECH_400GBASE_SR4 0x35
5452 /* enum: 400GBASE-R PCS/PMA over 4 WDM lane single-mode fiber PMD. See IEEE
5455 #define MC_CMD_ETH_TECH_400GBASE_LR4_ER4_FR4 0x36
5456 /* enum: 400GBASE-R PCS/PMA over 4-lane single-mode fiber PMD as specified in
5459 #define MC_CMD_ETH_TECH_400GBASE_DR4 0x37
5460 /* enum: 400GBASE-R PCS/PMA over 4 lane shielded balanced copper cable PMD as
5463 #define MC_CMD_ETH_TECH_400GBASE_CR4 0x38
5465 #define MC_CMD_ETH_TECH_AUTO 0x39
5466 /* enum: See IEEE 802.3cc-2017 Clause 114 */
5467 #define MC_CMD_ETH_TECH_25GBASE_LR_ER 0x3a
5469 * each) See IEEE 802.3ba-2010 Clause 85
5471 #define MC_CMD_ETH_TECH_100GBASE_CR10 0x3b
5473 #define MC_CMD_ETH_TECH_NONE 0x7f
5474 #define MC_CMD_ETH_TECH_TECH_LBN 0
5480 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_OFST 0
5482 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_OFST 0
5483 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LEN 4
5484 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LO_LBN 0
5486 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_OFST 4
5487 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_HI_LEN 4
5492 #define MC_CMD_LINK_STATUS_FLAGS_LINK_UP 0x0
5494 #define MC_CMD_LINK_STATUS_FLAGS_NO_PHY_LINK 0x1
5498 #define MC_CMD_LINK_STATUS_FLAGS_PMD_MDI_DISCONNECTED 0x2
5502 #define MC_CMD_LINK_STATUS_FLAGS_PMD_BAD 0x3
5506 #define MC_CMD_LINK_STATUS_FLAGS_PMD_UNSUPPORTED 0x4
5510 #define MC_CMD_LINK_STATUS_FLAGS_PMD_COMMS_FAULT 0x5
5512 #define MC_CMD_LINK_STATUS_FLAGS_PMD_POWER_FAULT 0x6
5514 #define MC_CMD_LINK_STATUS_FLAGS_PMD_THERMAL_FAULT 0x7
5516 #define MC_CMD_LINK_STATUS_FLAGS_PMD_LOS 0x8
5518 #define MC_CMD_LINK_STATUS_FLAGS_PMA_NO_CDR_LOCK 0x9
5520 #define MC_CMD_LINK_STATUS_FLAGS_PMA_LOS 0xa
5522 #define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_BLOCK_LOCK 0xb
5526 #define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_AM_LOCK 0xc
5528 #define MC_CMD_LINK_STATUS_FLAGS_PCS_NO_ALIGN_LOCK 0xd
5530 #define MC_CMD_LINK_STATUS_FLAGS_PCS_HI_BER 0xe
5532 #define MC_CMD_LINK_STATUS_FLAGS_FEC_NO_LOCK 0xf
5533 /* enum: If set, indicates that the number of symbol errors in a 8192-codeword
5536 #define MC_CMD_LINK_STATUS_FLAGS_FEC_HI_SER 0x10
5538 #define MC_CMD_LINK_STATUS_FLAGS_FEC_LOCAL_DEGRADED 0x11
5540 #define MC_CMD_LINK_STATUS_FLAGS_FEC_RM_DEGRADED 0x12
5542 #define MC_CMD_LINK_STATUS_FLAGS_FEC_DEGRADED_SER 0x13
5543 /* enum: If set, autonegotiation has detected an auto-negotiation capable link
5546 #define MC_CMD_LINK_STATUS_FLAGS_AN_ABLE 0x14
5548 #define MC_CMD_LINK_STATUS_FLAGS_AN_BP_FAILED 0x15
5550 #define MC_CMD_LINK_STATUS_FLAGS_AN_NP_FAILED 0x16
5554 #define MC_CMD_LINK_STATUS_FLAGS_AN_NO_HCD 0x17
5558 #define MC_CMD_LINK_STATUS_FLAGS_LT_NO_LOCAL_FRAME_LOCK 0x18
5562 #define MC_CMD_LINK_STATUS_FLAGS_LT_NO_RM_FRAME_LOCK 0x19
5566 #define MC_CMD_LINK_STATUS_FLAGS_LT_NO_RX_READY 0x1a
5567 #define MC_CMD_LINK_STATUS_FLAGS_STATUS_FLAGS_LBN 0
5572 #define MC_CMD_PAUSE_MODE_TYPE_OFST 0
5575 #define MC_CMD_PAUSE_MODE_AN_PAUSE 0x0
5577 #define MC_CMD_PAUSE_MODE_AN_ASYM_DIR 0x1
5578 #define MC_CMD_PAUSE_MODE_TYPE_LBN 0
5582 * Auto-Negotiation. Warning - This is fixed size and cannot be extended. This
5590 #define MC_CMD_ETH_AN_FIELDS_TECH_MASK_OFST 0
5595 #define MC_CMD_ETH_AN_FIELDS_TECH_MASK_LBN 0
5599 #define MC_CMD_ETH_AN_FIELDS_FEC_MASK_LEN 4
5607 #define MC_CMD_ETH_AN_FIELDS_FEC_REQ_LEN 4
5626 #define MC_CMD_LOOPBACK_V2_LEN 4
5627 #define MC_CMD_LOOPBACK_V2_MODE_OFST 0
5628 #define MC_CMD_LOOPBACK_V2_MODE_LEN 4
5630 #define MC_CMD_LOOPBACK_V2_NONE 0x0
5632 #define MC_CMD_LOOPBACK_V2_AUTO 0x1
5634 #define MC_CMD_LOOPBACK_V2_POST_MAC 0x2
5636 #define MC_CMD_LOOPBACK_V2_POST_PCS 0x3
5638 #define MC_CMD_LOOPBACK_V2_POST_PMA 0x4
5640 #define MC_CMD_LOOPBACK_V2_POST_MDI_WS 0x5
5642 #define MC_CMD_LOOPBACK_V2_POST_PMA_WS 0x6
5644 #define MC_CMD_LOOPBACK_V2_POST_PCS_WS 0x7
5646 #define MC_CMD_LOOPBACK_V2_POST_MAC_WS 0x8
5648 #define MC_CMD_LOOPBACK_V2_PRE_MAC 0x9
5649 #define MC_CMD_LOOPBACK_V2_MODE_LBN 0
5653 #define MC_CMD_FCNTL_LEN 4
5654 #define MC_CMD_FCNTL_MASK_OFST 0
5655 #define MC_CMD_FCNTL_MASK_LEN 4
5657 #define MC_CMD_FCNTL_OFF 0x0
5659 #define MC_CMD_FCNTL_RESPOND 0x1
5661 #define MC_CMD_FCNTL_BIDIR 0x2
5663 #define MC_CMD_FCNTL_AUTO 0x3
5665 #define MC_CMD_FCNTL_QBB 0x4
5667 #define MC_CMD_FCNTL_GENERATE 0x5
5668 #define MC_CMD_FCNTL_MASK_LBN 0
5672 #define MC_CMD_LINK_FLAGS_LEN 4
5676 #define MC_CMD_LINK_FLAGS_MASK_OFST 0
5677 #define MC_CMD_LINK_FLAGS_MASK_LEN 4
5679 /* enum: Enable auto-negotiation. If AN is enabled, link technology and FEC
5685 #define MC_CMD_LINK_FLAGS_AUTONEG_EN 0x0
5689 #define MC_CMD_LINK_FLAGS_PARALLEL_DETECT_EN 0x1
5691 #define MC_CMD_LINK_FLAGS_LINK_DISABLE 0x2
5693 #define MC_CMD_LINK_FLAGS_IGNORE_MODULE_SEQ 0x3
5694 #define MC_CMD_LINK_FLAGS_MASK_LBN 0
5701 * code: 0, EINVAL, ETIME, EAGAIN
5703 #define MC_CMD_LINK_CTRL 0x6b
5711 #define MC_CMD_LINK_CTRL_IN_PORT_HANDLE_OFST 0
5712 #define MC_CMD_LINK_CTRL_IN_PORT_HANDLE_LEN 4
5714 #define MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_OFST 4
5715 #define MC_CMD_LINK_CTRL_IN_CONTROL_FLAGS_LEN 4
5725 #define MC_CMD_LINK_CTRL_IN_RESERVED_LO_LEN 4
5729 #define MC_CMD_LINK_CTRL_IN_RESERVED_HI_LEN 4
5732 /* Technology abilities to advertise during auto-negotiation */
5738 /* Pause abilities to advertise during auto-negotiation. Valid when auto-
5740 * MC_CMD_FCNTL_AUTO. If auto-negotiation is disabled the driver must
5748 /* When auto-negotiation is enabled, this is the FEC mode to request. Note that
5751 * actual negotiated FEC mode. When auto-negotiation is disabled, this is the
5759 /* This is only to be used when auto-negotiation is disabled (forced speed or
5773 /* Loopback Mode. Only valid when auto-negotiation is disabled. */
5781 #define MC_CMD_LINK_CTRL_OUT_LEN 0
5787 #define MC_CMD_LINK_STATE 0x6c
5793 #define MC_CMD_LINK_STATE_IN_LEN 4
5795 #define MC_CMD_LINK_STATE_IN_PORT_HANDLE_OFST 0
5796 #define MC_CMD_LINK_STATE_IN_PORT_HANDLE_LEN 4
5801 #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_OFST 0
5803 #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_OFST 0
5804 #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LEN 4
5805 #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_LO_LBN 0
5807 #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_OFST 4
5808 #define MC_CMD_LINK_STATE_OUT_STATUS_FLAGS_HI_LEN 4
5828 /* Bitmask of auto-negotiated pause modes */
5840 /* Abilities requested by the driver to advertise during auto-negotiation */
5847 #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_MASK_LEN 4
5849 #define MC_CMD_LINK_STATE_OUT_ADVERTISED_ABILITIES_FEC_REQ_LEN 4
5852 /* Abilities advertised by the link partner during auto-negotiation */
5859 #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_MASK_LEN 4
5861 #define MC_CMD_LINK_STATE_OUT_LINK_PARTNER_ABILITIES_FEC_REQ_LEN 4
5873 #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_MASK_LEN 4
5875 #define MC_CMD_LINK_STATE_OUT_SUPPORTED_ABILITIES_FEC_REQ_LEN 4
5880 #define MC_CMD_LINK_STATE_OUT_CONTROL_FLAGS_LEN 4
5896 #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_OFST 0
5898 #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_OFST 0
5899 #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LEN 4
5900 #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_LO_LBN 0
5902 #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_OFST 4
5903 #define MC_CMD_LINK_STATE_OUT_V2_STATUS_FLAGS_HI_LEN 4
5923 /* Bitmask of auto-negotiated pause modes */
5935 /* Abilities requested by the driver to advertise during auto-negotiation */
5938 /* Abilities advertised by the link partner during auto-negotiation */
5948 #define MC_CMD_LINK_STATE_OUT_V2_CONTROL_FLAGS_LEN 4
5958 /* Reports the auto-negotiation supported by the local device. This depends on
5962 #define MC_CMD_LINK_STATE_OUT_V2_LOCAL_AN_SUPPORT_LEN 4
5971 #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_OFST 0
5973 #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_OFST 0
5974 #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LEN 4
5975 #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_LO_LBN 0
5977 #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_OFST 4
5978 #define MC_CMD_LINK_STATE_OUT_V3_STATUS_FLAGS_HI_LEN 4
5998 /* Bitmask of auto-negotiated pause modes */
6010 /* Abilities requested by the driver to advertise during auto-negotiation */
6013 /* Abilities advertised by the link partner during auto-negotiation */
6023 #define MC_CMD_LINK_STATE_OUT_V3_CONTROL_FLAGS_LEN 4
6033 /* Reports the auto-negotiation supported by the local device. This depends on
6037 #define MC_CMD_LINK_STATE_OUT_V3_LOCAL_AN_SUPPORT_LEN 4
6041 * reads non-zero. LINK_SPEED field is intended to be used by drivers without
6042 * the most up-to-date MCDI definitions, unable to deduce the link speed from
6046 #define MC_CMD_LINK_STATE_OUT_V3_LINK_SPEED_LEN 4
6048 #define MC_CMD_LINK_STATE_OUT_V3_FLAGS_LEN 4
6050 #define MC_CMD_LINK_STATE_OUT_V3_FULL_DUPLEX_LBN 0
6056 * Read the unified MAC/PHY link state. Locks required: None Return code: 0,
6059 #define MC_CMD_GET_LINK 0x29
6065 #define MC_CMD_GET_LINK_IN_LEN 0
6073 #define MC_CMD_GET_LINK_IN_V2_TARGET_OFST 0
6075 #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_OFST 0
6076 #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_LEN 4
6077 #define MC_CMD_GET_LINK_IN_V2_TARGET_LO_LBN 0
6079 #define MC_CMD_GET_LINK_IN_V2_TARGET_HI_OFST 4
6080 #define MC_CMD_GET_LINK_IN_V2_TARGET_HI_LEN 4
6084 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
6085 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
6086 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
6087 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6090 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
6092 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
6093 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6095 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6097 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6100 #define MC_CMD_GET_LINK_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
6102 #define MC_CMD_GET_LINK_IN_V2_TARGET_LINK_END_OFST 4
6103 #define MC_CMD_GET_LINK_IN_V2_TARGET_LINK_END_LEN 4
6104 #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_OFST 0
6106 #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_OFST 0
6107 #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_LEN 4
6108 #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_LO_LBN 0
6110 #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_OFST 4
6111 #define MC_CMD_GET_LINK_IN_V2_TARGET_FLAT_HI_LEN 4
6117 /* Near-side advertised capabilities. Refer to
6120 #define MC_CMD_GET_LINK_OUT_CAP_OFST 0
6121 #define MC_CMD_GET_LINK_OUT_CAP_LEN 4
6122 /* Link-partner advertised capabilities. Refer to
6125 #define MC_CMD_GET_LINK_OUT_LP_CAP_OFST 4
6126 #define MC_CMD_GET_LINK_OUT_LP_CAP_LEN 4
6128 * reads non-zero.
6131 #define MC_CMD_GET_LINK_OUT_LINK_SPEED_LEN 4
6134 #define MC_CMD_GET_LINK_OUT_LOOPBACK_MODE_LEN 4
6138 #define MC_CMD_GET_LINK_OUT_FLAGS_LEN 4
6140 #define MC_CMD_GET_LINK_OUT_LINK_UP_LBN 0
6165 #define MC_CMD_GET_LINK_OUT_FCNTL_LEN 4
6170 #define MC_CMD_GET_LINK_OUT_MAC_FAULT_LEN 4
6172 #define MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0
6186 /* Near-side advertised capabilities. Refer to
6189 #define MC_CMD_GET_LINK_OUT_V2_CAP_OFST 0
6190 #define MC_CMD_GET_LINK_OUT_V2_CAP_LEN 4
6191 /* Link-partner advertised capabilities. Refer to
6194 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_OFST 4
6195 #define MC_CMD_GET_LINK_OUT_V2_LP_CAP_LEN 4
6197 * reads non-zero.
6200 #define MC_CMD_GET_LINK_OUT_V2_LINK_SPEED_LEN 4
6203 #define MC_CMD_GET_LINK_OUT_V2_LOOPBACK_MODE_LEN 4
6207 #define MC_CMD_GET_LINK_OUT_V2_FLAGS_LEN 4
6209 #define MC_CMD_GET_LINK_OUT_V2_LINK_UP_LBN 0
6234 #define MC_CMD_GET_LINK_OUT_V2_FCNTL_LEN 4
6239 #define MC_CMD_GET_LINK_OUT_V2_MAC_FAULT_LEN 4
6241 /* MC_CMD_MAC_FAULT_XGMII_LOCAL_LBN 0 */
6253 * e.g. plugged-in module). In general, subset of
6255 * bits, if the PMD requires FEC. 0 if unknown (e.g. module unplugged). Equal
6256 * to SUPPORTED_CAP for non-pluggable PMDs. Refer to
6260 #define MC_CMD_GET_LINK_OUT_V2_LD_CAP_LEN 4
6261 /* Auto-negotiation type used on the link */
6263 #define MC_CMD_GET_LINK_OUT_V2_AN_TYPE_LEN 4
6268 #define MC_CMD_GET_LINK_OUT_V2_FEC_TYPE_LEN 4
6272 #define MC_CMD_GET_LINK_OUT_V2_EXT_FLAGS_LEN 4
6274 #define MC_CMD_GET_LINK_OUT_V2_PMD_MDI_CONNECTED_LBN 0
6286 #define MC_CMD_GET_LINK_OUT_V2_PCS_LOCK_LBN 4
6308 * code: 0, EINVAL, ETIME, EAGAIN
6310 #define MC_CMD_SET_LINK 0x2a
6317 /* Near-side advertised capabilities. Refer to
6320 #define MC_CMD_SET_LINK_IN_CAP_OFST 0
6321 #define MC_CMD_SET_LINK_IN_CAP_LEN 4
6323 #define MC_CMD_SET_LINK_IN_FLAGS_OFST 4
6324 #define MC_CMD_SET_LINK_IN_FLAGS_LEN 4
6325 #define MC_CMD_SET_LINK_IN_LOWPOWER_OFST 4
6326 #define MC_CMD_SET_LINK_IN_LOWPOWER_LBN 0
6328 #define MC_CMD_SET_LINK_IN_POWEROFF_OFST 4
6331 #define MC_CMD_SET_LINK_IN_TXDIS_OFST 4
6334 #define MC_CMD_SET_LINK_IN_LINKDOWN_OFST 4
6339 #define MC_CMD_SET_LINK_IN_LOOPBACK_MODE_LEN 4
6342 /* A loopback speed of "0" is supported, and means (choose any available
6346 #define MC_CMD_SET_LINK_IN_LOOPBACK_SPEED_LEN 4
6353 /* Near-side advertised capabilities. Refer to
6356 #define MC_CMD_SET_LINK_IN_V2_CAP_OFST 0
6357 #define MC_CMD_SET_LINK_IN_V2_CAP_LEN 4
6359 #define MC_CMD_SET_LINK_IN_V2_FLAGS_OFST 4
6360 #define MC_CMD_SET_LINK_IN_V2_FLAGS_LEN 4
6361 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_OFST 4
6362 #define MC_CMD_SET_LINK_IN_V2_LOWPOWER_LBN 0
6364 #define MC_CMD_SET_LINK_IN_V2_POWEROFF_OFST 4
6367 #define MC_CMD_SET_LINK_IN_V2_TXDIS_OFST 4
6370 #define MC_CMD_SET_LINK_IN_V2_LINKDOWN_OFST 4
6375 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_MODE_LEN 4
6378 /* A loopback speed of "0" is supported, and means (choose any available
6382 #define MC_CMD_SET_LINK_IN_V2_LOOPBACK_SPEED_LEN 4
6386 #define MC_CMD_SET_LINK_IN_V2_MODULE_SEQ_NUMBER_LBN 0
6394 /* Near-side advertised capabilities. Refer to
6397 #define MC_CMD_SET_LINK_IN_V3_CAP_OFST 0
6398 #define MC_CMD_SET_LINK_IN_V3_CAP_LEN 4
6400 #define MC_CMD_SET_LINK_IN_V3_FLAGS_OFST 4
6401 #define MC_CMD_SET_LINK_IN_V3_FLAGS_LEN 4
6402 #define MC_CMD_SET_LINK_IN_V3_LOWPOWER_OFST 4
6403 #define MC_CMD_SET_LINK_IN_V3_LOWPOWER_LBN 0
6405 #define MC_CMD_SET_LINK_IN_V3_POWEROFF_OFST 4
6408 #define MC_CMD_SET_LINK_IN_V3_TXDIS_OFST 4
6411 #define MC_CMD_SET_LINK_IN_V3_LINKDOWN_OFST 4
6416 #define MC_CMD_SET_LINK_IN_V3_LOOPBACK_MODE_LEN 4
6419 /* A loopback speed of "0" is supported, and means (choose any available
6423 #define MC_CMD_SET_LINK_IN_V3_LOOPBACK_SPEED_LEN 4
6427 #define MC_CMD_SET_LINK_IN_V3_MODULE_SEQ_NUMBER_LBN 0
6442 #define MC_CMD_SET_LINK_IN_V3_TARGET_LO_LEN 4
6446 #define MC_CMD_SET_LINK_IN_V3_TARGET_HI_LEN 4
6451 #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_LEN 4
6453 #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6459 #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6461 #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6463 #define MC_CMD_SET_LINK_IN_V3_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6469 #define MC_CMD_SET_LINK_IN_V3_TARGET_LINK_END_LEN 4
6473 #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_LO_LEN 4
6477 #define MC_CMD_SET_LINK_IN_V3_TARGET_FLAT_HI_LEN 4
6482 #define MC_CMD_SET_LINK_OUT_LEN 0
6487 * Set identification LED state. Locks required: None. Return code: 0, EINVAL
6489 #define MC_CMD_SET_ID_LED 0x2b
6495 #define MC_CMD_SET_ID_LED_IN_LEN 4
6497 #define MC_CMD_SET_ID_LED_IN_STATE_OFST 0
6498 #define MC_CMD_SET_ID_LED_IN_STATE_LEN 4
6499 #define MC_CMD_LED_OFF 0x0 /* enum */
6500 #define MC_CMD_LED_ON 0x1 /* enum */
6501 #define MC_CMD_LED_DEFAULT 0x2 /* enum */
6504 #define MC_CMD_SET_ID_LED_OUT_LEN 0
6509 * Set MAC configuration. Locks required: None. Return code: 0, EINVAL
6511 #define MC_CMD_SET_MAC 0x2c
6521 #define MC_CMD_SET_MAC_IN_MTU_OFST 0
6522 #define MC_CMD_SET_MAC_IN_MTU_LEN 4
6523 #define MC_CMD_SET_MAC_IN_DRAIN_OFST 4
6524 #define MC_CMD_SET_MAC_IN_DRAIN_LEN 4
6528 #define MC_CMD_SET_MAC_IN_ADDR_LO_LEN 4
6532 #define MC_CMD_SET_MAC_IN_ADDR_HI_LEN 4
6536 #define MC_CMD_SET_MAC_IN_REJECT_LEN 4
6538 #define MC_CMD_SET_MAC_IN_REJECT_UNCST_LBN 0
6544 #define MC_CMD_SET_MAC_IN_FCNTL_LEN 4
6546 /* MC_CMD_FCNTL_OFF 0x0 */
6548 /* MC_CMD_FCNTL_RESPOND 0x1 */
6550 /* MC_CMD_FCNTL_BIDIR 0x2 */
6552 /* MC_CMD_FCNTL_AUTO 0x3 */
6554 /* MC_CMD_FCNTL_QBB 0x4 */
6556 /* MC_CMD_FCNTL_GENERATE 0x5 */
6558 #define MC_CMD_SET_MAC_IN_FLAGS_LEN 4
6560 #define MC_CMD_SET_MAC_IN_FLAG_INCLUDE_FCS_LBN 0
6568 #define MC_CMD_SET_MAC_EXT_IN_MTU_OFST 0
6569 #define MC_CMD_SET_MAC_EXT_IN_MTU_LEN 4
6570 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_OFST 4
6571 #define MC_CMD_SET_MAC_EXT_IN_DRAIN_LEN 4
6575 #define MC_CMD_SET_MAC_EXT_IN_ADDR_LO_LEN 4
6579 #define MC_CMD_SET_MAC_EXT_IN_ADDR_HI_LEN 4
6583 #define MC_CMD_SET_MAC_EXT_IN_REJECT_LEN 4
6585 #define MC_CMD_SET_MAC_EXT_IN_REJECT_UNCST_LBN 0
6591 #define MC_CMD_SET_MAC_EXT_IN_FCNTL_LEN 4
6593 /* MC_CMD_FCNTL_OFF 0x0 */
6595 /* MC_CMD_FCNTL_RESPOND 0x1 */
6597 /* MC_CMD_FCNTL_BIDIR 0x2 */
6599 /* MC_CMD_FCNTL_AUTO 0x3 */
6601 /* MC_CMD_FCNTL_QBB 0x4 */
6603 /* MC_CMD_FCNTL_GENERATE 0x5 */
6605 #define MC_CMD_SET_MAC_EXT_IN_FLAGS_LEN 4
6607 #define MC_CMD_SET_MAC_EXT_IN_FLAG_INCLUDE_FCS_LBN 0
6615 #define MC_CMD_SET_MAC_EXT_IN_CONTROL_LEN 4
6617 #define MC_CMD_SET_MAC_EXT_IN_CFG_MTU_LBN 0
6629 #define MC_CMD_SET_MAC_EXT_IN_CFG_FCS_LBN 4
6637 #define MC_CMD_SET_MAC_V3_IN_MTU_OFST 0
6638 #define MC_CMD_SET_MAC_V3_IN_MTU_LEN 4
6639 #define MC_CMD_SET_MAC_V3_IN_DRAIN_OFST 4
6640 #define MC_CMD_SET_MAC_V3_IN_DRAIN_LEN 4
6644 #define MC_CMD_SET_MAC_V3_IN_ADDR_LO_LEN 4
6648 #define MC_CMD_SET_MAC_V3_IN_ADDR_HI_LEN 4
6652 #define MC_CMD_SET_MAC_V3_IN_REJECT_LEN 4
6654 #define MC_CMD_SET_MAC_V3_IN_REJECT_UNCST_LBN 0
6660 #define MC_CMD_SET_MAC_V3_IN_FCNTL_LEN 4
6662 /* MC_CMD_FCNTL_OFF 0x0 */
6664 /* MC_CMD_FCNTL_RESPOND 0x1 */
6666 /* MC_CMD_FCNTL_BIDIR 0x2 */
6668 /* MC_CMD_FCNTL_AUTO 0x3 */
6670 /* MC_CMD_FCNTL_QBB 0x4 */
6672 /* MC_CMD_FCNTL_GENERATE 0x5 */
6674 #define MC_CMD_SET_MAC_V3_IN_FLAGS_LEN 4
6676 #define MC_CMD_SET_MAC_V3_IN_FLAG_INCLUDE_FCS_LBN 0
6684 #define MC_CMD_SET_MAC_V3_IN_CONTROL_LEN 4
6686 #define MC_CMD_SET_MAC_V3_IN_CFG_MTU_LBN 0
6698 #define MC_CMD_SET_MAC_V3_IN_CFG_FCS_LBN 4
6707 #define MC_CMD_SET_MAC_V3_IN_TARGET_LO_LEN 4
6711 #define MC_CMD_SET_MAC_V3_IN_TARGET_HI_LEN 4
6716 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_LEN 4
6718 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6724 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6726 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6728 #define MC_CMD_SET_MAC_V3_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6734 #define MC_CMD_SET_MAC_V3_IN_TARGET_LINK_END_LEN 4
6738 #define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_LO_LEN 4
6742 #define MC_CMD_SET_MAC_V3_IN_TARGET_FLAT_HI_LEN 4
6747 #define MC_CMD_SET_MAC_OUT_LEN 0
6750 #define MC_CMD_SET_MAC_V2_OUT_LEN 4
6753 * to 0.
6755 #define MC_CMD_SET_MAC_V2_OUT_MTU_OFST 0
6756 #define MC_CMD_SET_MAC_V2_OUT_MTU_LEN 4
6763 * by a 32bit number. If the DMA_ADDR is 0, then no DMA is performed, and the
6764 * statistics may be read from the message response. If DMA_ADDR != 0, then the
6765 * statistics are dmad to that (page-aligned location). Locks required: None.
6766 * Returns: 0, ETIME
6768 #define MC_CMD_PHY_STATS 0x2d
6776 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_OFST 0
6778 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_OFST 0
6779 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LEN 4
6780 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_LO_LBN 0
6782 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_OFST 4
6783 #define MC_CMD_PHY_STATS_IN_DMA_ADDR_HI_LEN 4
6788 #define MC_CMD_PHY_STATS_OUT_DMA_LEN 0
6792 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_OFST 0
6793 #define MC_CMD_PHY_STATS_OUT_NO_DMA_STATISTICS_LEN 4
6796 #define MC_CMD_OUI 0x0
6797 /* enum: PMA-PMD Link Up. */
6798 #define MC_CMD_PMA_PMD_LINK_UP 0x1
6799 /* enum: PMA-PMD RX Fault. */
6800 #define MC_CMD_PMA_PMD_RX_FAULT 0x2
6801 /* enum: PMA-PMD TX Fault. */
6802 #define MC_CMD_PMA_PMD_TX_FAULT 0x3
6803 /* enum: PMA-PMD Signal */
6804 #define MC_CMD_PMA_PMD_SIGNAL 0x4
6805 /* enum: PMA-PMD SNR A. */
6806 #define MC_CMD_PMA_PMD_SNR_A 0x5
6807 /* enum: PMA-PMD SNR B. */
6808 #define MC_CMD_PMA_PMD_SNR_B 0x6
6809 /* enum: PMA-PMD SNR C. */
6810 #define MC_CMD_PMA_PMD_SNR_C 0x7
6811 /* enum: PMA-PMD SNR D. */
6812 #define MC_CMD_PMA_PMD_SNR_D 0x8
6814 #define MC_CMD_PCS_LINK_UP 0x9
6816 #define MC_CMD_PCS_RX_FAULT 0xa
6818 #define MC_CMD_PCS_TX_FAULT 0xb
6820 #define MC_CMD_PCS_BER 0xc
6822 #define MC_CMD_PCS_BLOCK_ERRORS 0xd
6824 #define MC_CMD_PHYXS_LINK_UP 0xe
6826 #define MC_CMD_PHYXS_RX_FAULT 0xf
6828 #define MC_CMD_PHYXS_TX_FAULT 0x10
6830 #define MC_CMD_PHYXS_ALIGN 0x11
6832 #define MC_CMD_PHYXS_SYNC 0x12
6833 /* enum: AN link-up. */
6834 #define MC_CMD_AN_LINK_UP 0x13
6836 #define MC_CMD_AN_COMPLETE 0x14
6838 #define MC_CMD_AN_10GBT_STATUS 0x15
6839 /* enum: Clause 22 Link-Up. */
6840 #define MC_CMD_CL22_LINK_UP 0x16
6842 #define MC_CMD_PHY_NSTATS 0x17
6850 * guarantee consistent results. If the DMA_ADDR is 0, then no DMA is
6852 * DMA_ADDR != 0, then the statistics are dmad to that (page-aligned location).
6854 * effect. Returns: 0, ETIME
6856 #define MC_CMD_MAC_STATS 0x2e
6864 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_OFST 0
6866 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_OFST 0
6867 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LEN 4
6868 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_LO_LBN 0
6870 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_OFST 4
6871 #define MC_CMD_MAC_STATS_IN_DMA_ADDR_HI_LEN 4
6875 #define MC_CMD_MAC_STATS_IN_CMD_LEN 4
6877 #define MC_CMD_MAC_STATS_IN_DMA_LBN 0
6889 #define MC_CMD_MAC_STATS_IN_PERIODIC_CLEAR_LBN 4
6903 #define MC_CMD_MAC_STATS_IN_DMA_LEN_LEN 4
6906 #define MC_CMD_MAC_STATS_IN_PORT_ID_LEN 4
6911 #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_OFST 0
6913 #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_OFST 0
6914 #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_LEN 4
6915 #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_LO_LBN 0
6917 #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_OFST 4
6918 #define MC_CMD_MAC_STATS_V2_IN_DMA_ADDR_HI_LEN 4
6922 #define MC_CMD_MAC_STATS_V2_IN_CMD_LEN 4
6924 #define MC_CMD_MAC_STATS_V2_IN_DMA_LBN 0
6936 #define MC_CMD_MAC_STATS_V2_IN_PERIODIC_CLEAR_LBN 4
6950 #define MC_CMD_MAC_STATS_V2_IN_DMA_LEN_LEN 4
6953 #define MC_CMD_MAC_STATS_V2_IN_PORT_ID_LEN 4
6961 #define MC_CMD_MAC_STATS_V2_IN_TARGET_LO_LEN 4
6965 #define MC_CMD_MAC_STATS_V2_IN_TARGET_HI_LEN 4
6970 #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_LEN 4
6972 #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FLAT_LEN 4
6978 #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
6980 #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
6982 #define MC_CMD_MAC_STATS_V2_IN_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
6988 #define MC_CMD_MAC_STATS_V2_IN_TARGET_LINK_END_LEN 4
6992 #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_LO_LEN 4
6996 #define MC_CMD_MAC_STATS_V2_IN_TARGET_FLAT_HI_LEN 4
7001 #define MC_CMD_MAC_STATS_OUT_DMA_LEN 0
7005 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_OFST 0
7007 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_OFST 0
7008 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LEN 4
7009 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_LO_LBN 0
7011 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_OFST 4
7012 #define MC_CMD_MAC_STATS_OUT_NO_DMA_STATISTICS_HI_LEN 4
7017 #define MC_CMD_MAC_GENERATION_START 0x0 /* enum */
7018 #define MC_CMD_MAC_DMABUF_START 0x1 /* enum */
7019 #define MC_CMD_MAC_TX_PKTS 0x1 /* enum */
7020 #define MC_CMD_MAC_TX_PAUSE_PKTS 0x2 /* enum */
7021 #define MC_CMD_MAC_TX_CONTROL_PKTS 0x3 /* enum */
7022 #define MC_CMD_MAC_TX_UNICAST_PKTS 0x4 /* enum */
7023 #define MC_CMD_MAC_TX_MULTICAST_PKTS 0x5 /* enum */
7024 #define MC_CMD_MAC_TX_BROADCAST_PKTS 0x6 /* enum */
7025 #define MC_CMD_MAC_TX_BYTES 0x7 /* enum */
7026 #define MC_CMD_MAC_TX_BAD_BYTES 0x8 /* enum */
7027 #define MC_CMD_MAC_TX_LT64_PKTS 0x9 /* enum */
7028 #define MC_CMD_MAC_TX_64_PKTS 0xa /* enum */
7029 #define MC_CMD_MAC_TX_65_TO_127_PKTS 0xb /* enum */
7030 #define MC_CMD_MAC_TX_128_TO_255_PKTS 0xc /* enum */
7031 #define MC_CMD_MAC_TX_256_TO_511_PKTS 0xd /* enum */
7032 #define MC_CMD_MAC_TX_512_TO_1023_PKTS 0xe /* enum */
7033 #define MC_CMD_MAC_TX_1024_TO_15XX_PKTS 0xf /* enum */
7034 #define MC_CMD_MAC_TX_15XX_TO_JUMBO_PKTS 0x10 /* enum */
7035 #define MC_CMD_MAC_TX_GTJUMBO_PKTS 0x11 /* enum */
7036 #define MC_CMD_MAC_TX_BAD_FCS_PKTS 0x12 /* enum */
7037 #define MC_CMD_MAC_TX_SINGLE_COLLISION_PKTS 0x13 /* enum */
7038 #define MC_CMD_MAC_TX_MULTIPLE_COLLISION_PKTS 0x14 /* enum */
7039 #define MC_CMD_MAC_TX_EXCESSIVE_COLLISION_PKTS 0x15 /* enum */
7040 #define MC_CMD_MAC_TX_LATE_COLLISION_PKTS 0x16 /* enum */
7041 #define MC_CMD_MAC_TX_DEFERRED_PKTS 0x17 /* enum */
7042 #define MC_CMD_MAC_TX_EXCESSIVE_DEFERRED_PKTS 0x18 /* enum */
7043 #define MC_CMD_MAC_TX_NON_TCPUDP_PKTS 0x19 /* enum */
7044 #define MC_CMD_MAC_TX_MAC_SRC_ERR_PKTS 0x1a /* enum */
7045 #define MC_CMD_MAC_TX_IP_SRC_ERR_PKTS 0x1b /* enum */
7046 #define MC_CMD_MAC_RX_PKTS 0x1c /* enum */
7047 #define MC_CMD_MAC_RX_PAUSE_PKTS 0x1d /* enum */
7048 #define MC_CMD_MAC_RX_GOOD_PKTS 0x1e /* enum */
7049 #define MC_CMD_MAC_RX_CONTROL_PKTS 0x1f /* enum */
7050 #define MC_CMD_MAC_RX_UNICAST_PKTS 0x20 /* enum */
7051 #define MC_CMD_MAC_RX_MULTICAST_PKTS 0x21 /* enum */
7052 #define MC_CMD_MAC_RX_BROADCAST_PKTS 0x22 /* enum */
7053 #define MC_CMD_MAC_RX_BYTES 0x23 /* enum */
7054 #define MC_CMD_MAC_RX_BAD_BYTES 0x24 /* enum */
7055 #define MC_CMD_MAC_RX_64_PKTS 0x25 /* enum */
7056 #define MC_CMD_MAC_RX_65_TO_127_PKTS 0x26 /* enum */
7057 #define MC_CMD_MAC_RX_128_TO_255_PKTS 0x27 /* enum */
7058 #define MC_CMD_MAC_RX_256_TO_511_PKTS 0x28 /* enum */
7059 #define MC_CMD_MAC_RX_512_TO_1023_PKTS 0x29 /* enum */
7060 #define MC_CMD_MAC_RX_1024_TO_15XX_PKTS 0x2a /* enum */
7061 #define MC_CMD_MAC_RX_15XX_TO_JUMBO_PKTS 0x2b /* enum */
7062 #define MC_CMD_MAC_RX_GTJUMBO_PKTS 0x2c /* enum */
7063 #define MC_CMD_MAC_RX_UNDERSIZE_PKTS 0x2d /* enum */
7064 #define MC_CMD_MAC_RX_BAD_FCS_PKTS 0x2e /* enum */
7065 #define MC_CMD_MAC_RX_OVERFLOW_PKTS 0x2f /* enum */
7066 #define MC_CMD_MAC_RX_FALSE_CARRIER_PKTS 0x30 /* enum */
7067 #define MC_CMD_MAC_RX_SYMBOL_ERROR_PKTS 0x31 /* enum */
7068 #define MC_CMD_MAC_RX_ALIGN_ERROR_PKTS 0x32 /* enum */
7069 #define MC_CMD_MAC_RX_LENGTH_ERROR_PKTS 0x33 /* enum */
7070 #define MC_CMD_MAC_RX_INTERNAL_ERROR_PKTS 0x34 /* enum */
7071 #define MC_CMD_MAC_RX_JABBER_PKTS 0x35 /* enum */
7072 #define MC_CMD_MAC_RX_NODESC_DROPS 0x36 /* enum */
7073 #define MC_CMD_MAC_RX_LANES01_CHAR_ERR 0x37 /* enum */
7074 #define MC_CMD_MAC_RX_LANES23_CHAR_ERR 0x38 /* enum */
7075 #define MC_CMD_MAC_RX_LANES01_DISP_ERR 0x39 /* enum */
7076 #define MC_CMD_MAC_RX_LANES23_DISP_ERR 0x3a /* enum */
7077 #define MC_CMD_MAC_RX_MATCH_FAULT 0x3b /* enum */
7081 #define MC_CMD_MAC_PM_TRUNC_BB_OVERFLOW 0x3c
7085 #define MC_CMD_MAC_PM_DISCARD_BB_OVERFLOW 0x3d
7089 #define MC_CMD_MAC_PM_TRUNC_VFIFO_FULL 0x3e
7093 #define MC_CMD_MAC_PM_DISCARD_VFIFO_FULL 0x3f
7097 #define MC_CMD_MAC_PM_TRUNC_QBB 0x40
7101 #define MC_CMD_MAC_PM_DISCARD_QBB 0x41
7105 #define MC_CMD_MAC_PM_DISCARD_MAPPING 0x42
7109 #define MC_CMD_MAC_RXDP_Q_DISABLED_PKTS 0x43
7113 #define MC_CMD_MAC_RXDP_DI_DROPPED_PKTS 0x45
7114 /* enum: RXDP counter: Number of non-host packets. Valid for EF10 with
7117 #define MC_CMD_MAC_RXDP_STREAMING_PKTS 0x46
7121 #define MC_CMD_MAC_RXDP_HLB_FETCH_CONDITIONS 0x47
7125 #define MC_CMD_MAC_RXDP_HLB_WAIT_CONDITIONS 0x48
7126 #define MC_CMD_MAC_VADAPTER_RX_DMABUF_START 0x4c /* enum */
7127 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_PACKETS 0x4c /* enum */
7128 #define MC_CMD_MAC_VADAPTER_RX_UNICAST_BYTES 0x4d /* enum */
7129 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_PACKETS 0x4e /* enum */
7130 #define MC_CMD_MAC_VADAPTER_RX_MULTICAST_BYTES 0x4f /* enum */
7131 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_PACKETS 0x50 /* enum */
7132 #define MC_CMD_MAC_VADAPTER_RX_BROADCAST_BYTES 0x51 /* enum */
7133 #define MC_CMD_MAC_VADAPTER_RX_BAD_PACKETS 0x52 /* enum */
7134 #define MC_CMD_MAC_VADAPTER_RX_BAD_BYTES 0x53 /* enum */
7135 #define MC_CMD_MAC_VADAPTER_RX_OVERFLOW 0x54 /* enum */
7136 #define MC_CMD_MAC_VADAPTER_TX_DMABUF_START 0x57 /* enum */
7137 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_PACKETS 0x57 /* enum */
7138 #define MC_CMD_MAC_VADAPTER_TX_UNICAST_BYTES 0x58 /* enum */
7139 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_PACKETS 0x59 /* enum */
7140 #define MC_CMD_MAC_VADAPTER_TX_MULTICAST_BYTES 0x5a /* enum */
7141 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_PACKETS 0x5b /* enum */
7142 #define MC_CMD_MAC_VADAPTER_TX_BROADCAST_BYTES 0x5c /* enum */
7143 #define MC_CMD_MAC_VADAPTER_TX_BAD_PACKETS 0x5d /* enum */
7144 #define MC_CMD_MAC_VADAPTER_TX_BAD_BYTES 0x5e /* enum */
7145 #define MC_CMD_MAC_VADAPTER_TX_OVERFLOW 0x5f /* enum */
7147 #define MC_CMD_GMAC_DMABUF_START 0x40
7149 #define MC_CMD_GMAC_DMABUF_END 0x5f
7155 * 64-bit word of the DMA buffer (at DMA_LEN - sizeof(uint64_t)). Note that
7157 * the last 64-bit word in the buffer when DMA_LEN == MC_CMD_MAC_NSTATS *
7158 * sizeof(uint64_t). See SF-109306-TC, Section 9.2 for details.
7160 #define MC_CMD_MAC_GENERATION_END 0x60
7161 #define MC_CMD_MAC_NSTATS 0x61 /* enum */
7164 #define MC_CMD_MAC_STATS_V2_OUT_DMA_LEN 0
7168 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_OFST 0
7170 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_OFST 0
7171 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LEN 4
7172 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_LO_LBN 0
7174 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_OFST 4
7175 #define MC_CMD_MAC_STATS_V2_OUT_NO_DMA_STATISTICS_HI_LEN 4
7181 #define MC_CMD_MAC_FEC_DMABUF_START 0x61
7182 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only for Medford2)
7184 #define MC_CMD_MAC_FEC_UNCORRECTED_ERRORS 0x61
7185 /* enum: Number of corrected FEC codewords on link (RS-FEC only for Medford2)
7187 #define MC_CMD_MAC_FEC_CORRECTED_ERRORS 0x62
7188 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
7189 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE0 0x63
7190 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
7191 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE1 0x64
7192 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
7193 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE2 0x65
7194 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
7195 #define MC_CMD_MAC_FEC_CORRECTED_SYMBOLS_LANE3 0x66
7199 #define MC_CMD_MAC_NSTATS_V2 0x68
7204 #define MC_CMD_MAC_STATS_V3_OUT_DMA_LEN 0
7208 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_OFST 0
7210 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_OFST 0
7211 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LEN 4
7212 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_LO_LBN 0
7214 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_OFST 4
7215 #define MC_CMD_MAC_STATS_V3_OUT_NO_DMA_STATISTICS_HI_LEN 4
7221 #define MC_CMD_MAC_CTPIO_DMABUF_START 0x68
7225 #define MC_CMD_MAC_CTPIO_VI_BUSY_FALLBACK 0x68
7229 #define MC_CMD_MAC_CTPIO_LONG_WRITE_SUCCESS 0x69
7233 #define MC_CMD_MAC_CTPIO_MISSING_DBELL_FAIL 0x6a
7235 #define MC_CMD_MAC_CTPIO_OVERFLOW_FAIL 0x6b
7239 #define MC_CMD_MAC_CTPIO_UNDERFLOW_FAIL 0x6c
7243 #define MC_CMD_MAC_CTPIO_TIMEOUT_FAIL 0x6d
7247 #define MC_CMD_MAC_CTPIO_NONCONTIG_WR_FAIL 0x6e
7251 #define MC_CMD_MAC_CTPIO_FRM_CLOBBER_FAIL 0x6f
7253 * or not 32-bit aligned
7255 #define MC_CMD_MAC_CTPIO_INVALID_WR_FAIL 0x70
7259 #define MC_CMD_MAC_CTPIO_VI_CLOBBER_FALLBACK 0x71
7262 #define MC_CMD_MAC_CTPIO_UNQUALIFIED_FALLBACK 0x72
7266 #define MC_CMD_MAC_CTPIO_RUNT_FALLBACK 0x73
7268 #define MC_CMD_MAC_CTPIO_SUCCESS 0x74
7270 #define MC_CMD_MAC_CTPIO_FALLBACK 0x75
7274 #define MC_CMD_MAC_CTPIO_POISON 0x76
7276 #define MC_CMD_MAC_CTPIO_ERASE 0x77
7280 #define MC_CMD_MAC_NSTATS_V3 0x79
7285 #define MC_CMD_MAC_STATS_V4_OUT_DMA_LEN 0
7289 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_OFST 0
7291 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_OFST 0
7292 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LEN 4
7293 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_LO_LBN 0
7295 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_OFST 4
7296 #define MC_CMD_MAC_STATS_V4_OUT_NO_DMA_STATISTICS_HI_LEN 4
7302 #define MC_CMD_MAC_V4_DMABUF_START 0x79
7306 #define MC_CMD_MAC_RXDP_SCATTER_DISABLED_TRUNC 0x79
7310 #define MC_CMD_MAC_RXDP_HLB_IDLE 0x7a
7314 #define MC_CMD_MAC_RXDP_HLB_TIMEOUT 0x7b
7318 #define MC_CMD_MAC_NSTATS_V4 0x7d
7323 #define MC_CMD_MAC_STATS_V5_OUT_DMA_LEN 0
7327 #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_OFST 0
7329 #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_OFST 0
7330 #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LEN 4
7331 #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_LO_LBN 0
7333 #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_OFST 4
7334 #define MC_CMD_MAC_STATS_V5_OUT_NO_DMA_STATISTICS_HI_LEN 4
7340 #define MC_CMD_MAC_V5_DMABUF_START 0x7c
7344 #define MC_CMD_MAC_LINK_TOGGLES 0x7c
7348 #define MC_CMD_MAC_NSTATS_V5 0x7e
7357 #define MC_CMD_WOL_FILTER_SET 0x32
7364 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0
7365 #define MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4
7366 #define MC_CMD_FILTER_MODE_SIMPLE 0x0 /* enum */
7367 #define MC_CMD_FILTER_MODE_STRUCTURED 0xffffffff /* enum */
7369 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4
7370 #define MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4
7372 #define MC_CMD_WOL_TYPE_MAGIC 0x0
7374 #define MC_CMD_WOL_TYPE_WIN_MAGIC 0x2
7376 #define MC_CMD_WOL_TYPE_IPV4_SYN 0x3
7378 #define MC_CMD_WOL_TYPE_IPV6_SYN 0x4
7380 #define MC_CMD_WOL_TYPE_BITMAP 0x5
7382 #define MC_CMD_WOL_TYPE_LINK 0x6
7384 #define MC_CMD_WOL_TYPE_MAX 0x7
7386 #define MC_CMD_WOL_FILTER_SET_IN_DATA_LEN 4
7391 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7392 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7393 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7394 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7398 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_LO_LEN 4
7402 #define MC_CMD_WOL_FILTER_SET_IN_MAGIC_MAC_HI_LEN 4
7408 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7409 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7410 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7411 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7413 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_SRC_IP_LEN 4
7415 #define MC_CMD_WOL_FILTER_SET_IN_IPV4_SYN_DST_IP_LEN 4
7423 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7424 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7425 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7426 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7438 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7439 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7440 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7441 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7455 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_OFST 0 */
7456 /* MC_CMD_WOL_FILTER_SET_IN_FILTER_MODE_LEN 4 */
7457 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_OFST 4 */
7458 /* MC_CMD_WOL_FILTER_SET_IN_WOL_TYPE_LEN 4 */
7460 #define MC_CMD_WOL_FILTER_SET_IN_LINK_MASK_LEN 4
7462 #define MC_CMD_WOL_FILTER_SET_IN_LINK_UP_LBN 0
7469 #define MC_CMD_WOL_FILTER_SET_OUT_LEN 4
7470 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_OFST 0
7471 #define MC_CMD_WOL_FILTER_SET_OUT_FILTER_ID_LEN 4
7476 * Remove a WoL filter. Locks required: None. Returns: 0, EINVAL, ENOSYS
7478 #define MC_CMD_WOL_FILTER_REMOVE 0x33
7484 #define MC_CMD_WOL_FILTER_REMOVE_IN_LEN 4
7485 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_OFST 0
7486 #define MC_CMD_WOL_FILTER_REMOVE_IN_FILTER_ID_LEN 4
7489 #define MC_CMD_WOL_FILTER_REMOVE_OUT_LEN 0
7494 * Reset (i.e. remove all) WoL filters. Locks required: None. Returns: 0,
7497 #define MC_CMD_WOL_FILTER_RESET 0x34
7503 #define MC_CMD_WOL_FILTER_RESET_IN_LEN 4
7504 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_OFST 0
7505 #define MC_CMD_WOL_FILTER_RESET_IN_MASK_LEN 4
7507 #define MC_CMD_WOL_FILTER_RESET_IN_WAKE_FILTERS 0x1 /* enum */
7508 #define MC_CMD_WOL_FILTER_RESET_IN_LIGHTSOUT_OFFLOADS 0x2 /* enum */
7511 #define MC_CMD_WOL_FILTER_RESET_OUT_LEN 0
7517 * Locks required: none. Returns: 0
7519 #define MC_CMD_NVRAM_TYPES 0x36
7525 #define MC_CMD_NVRAM_TYPES_IN_LEN 0
7528 #define MC_CMD_NVRAM_TYPES_OUT_LEN 4
7530 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_OFST 0
7531 #define MC_CMD_NVRAM_TYPES_OUT_TYPES_LEN 4
7534 #define MC_CMD_NVRAM_TYPE_DISABLED_CALLISTO 0x0
7536 #define MC_CMD_NVRAM_TYPE_MC_FW 0x1
7538 #define MC_CMD_NVRAM_TYPE_MC_FW_BACKUP 0x2
7540 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT0 0x3
7542 #define MC_CMD_NVRAM_TYPE_STATIC_CFG_PORT1 0x4
7544 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT0 0x5
7546 #define MC_CMD_NVRAM_TYPE_DYNAMIC_CFG_PORT1 0x6
7548 #define MC_CMD_NVRAM_TYPE_EXP_ROM 0x7
7550 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT0 0x8
7552 #define MC_CMD_NVRAM_TYPE_EXP_ROM_CFG_PORT1 0x9
7554 #define MC_CMD_NVRAM_TYPE_PHY_PORT0 0xa
7556 #define MC_CMD_NVRAM_TYPE_PHY_PORT1 0xb
7558 #define MC_CMD_NVRAM_TYPE_LOG 0xc
7560 #define MC_CMD_NVRAM_TYPE_FPGA 0xd
7562 #define MC_CMD_NVRAM_TYPE_FPGA_BACKUP 0xe
7564 #define MC_CMD_NVRAM_TYPE_FC_FW 0xf
7566 #define MC_CMD_NVRAM_TYPE_FC_FW_BACKUP 0x10
7568 #define MC_CMD_NVRAM_TYPE_CPLD 0x11
7570 #define MC_CMD_NVRAM_TYPE_LICENSE 0x12
7572 #define MC_CMD_NVRAM_TYPE_FC_LOG 0x13
7574 #define MC_CMD_NVRAM_TYPE_FC_EXTRA 0x14
7579 * Read info about a virtual NVRAM partition. Locks required: none. Returns: 0,
7582 #define MC_CMD_NVRAM_INFO 0x37
7588 #define MC_CMD_NVRAM_INFO_IN_LEN 4
7589 #define MC_CMD_NVRAM_INFO_IN_TYPE_OFST 0
7590 #define MC_CMD_NVRAM_INFO_IN_TYPE_LEN 4
7596 #define MC_CMD_NVRAM_INFO_OUT_TYPE_OFST 0
7597 #define MC_CMD_NVRAM_INFO_OUT_TYPE_LEN 4
7600 #define MC_CMD_NVRAM_INFO_OUT_SIZE_OFST 4
7601 #define MC_CMD_NVRAM_INFO_OUT_SIZE_LEN 4
7603 #define MC_CMD_NVRAM_INFO_OUT_ERASESIZE_LEN 4
7605 #define MC_CMD_NVRAM_INFO_OUT_FLAGS_LEN 4
7607 #define MC_CMD_NVRAM_INFO_OUT_PROTECTED_LBN 0
7628 #define MC_CMD_NVRAM_INFO_OUT_PHYSDEV_LEN 4
7630 #define MC_CMD_NVRAM_INFO_OUT_PHYSADDR_LEN 4
7634 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_OFST 0
7635 #define MC_CMD_NVRAM_INFO_V2_OUT_TYPE_LEN 4
7638 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_OFST 4
7639 #define MC_CMD_NVRAM_INFO_V2_OUT_SIZE_LEN 4
7641 #define MC_CMD_NVRAM_INFO_V2_OUT_ERASESIZE_LEN 4
7643 #define MC_CMD_NVRAM_INFO_V2_OUT_FLAGS_LEN 4
7645 #define MC_CMD_NVRAM_INFO_V2_OUT_PROTECTED_LBN 0
7666 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSDEV_LEN 4
7668 #define MC_CMD_NVRAM_INFO_V2_OUT_PHYSADDR_LEN 4
7672 #define MC_CMD_NVRAM_INFO_V2_OUT_WRITESIZE_LEN 4
7678 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type), EACCES (if
7685 #define MC_CMD_NVRAM_UPDATE_START 0x38
7693 #define MC_CMD_NVRAM_UPDATE_START_IN_LEN 4
7694 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_OFST 0
7695 #define MC_CMD_NVRAM_UPDATE_START_IN_TYPE_LEN 4
7705 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_OFST 0
7706 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_TYPE_LEN 4
7709 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_OFST 4
7710 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAGS_LEN 4
7711 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_OFST 4
7712 #define MC_CMD_NVRAM_UPDATE_START_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7716 #define MC_CMD_NVRAM_UPDATE_START_OUT_LEN 0
7722 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7725 #define MC_CMD_NVRAM_READ 0x39
7732 #define MC_CMD_NVRAM_READ_IN_TYPE_OFST 0
7733 #define MC_CMD_NVRAM_READ_IN_TYPE_LEN 4
7736 #define MC_CMD_NVRAM_READ_IN_OFFSET_OFST 4
7737 #define MC_CMD_NVRAM_READ_IN_OFFSET_LEN 4
7740 #define MC_CMD_NVRAM_READ_IN_LENGTH_LEN 4
7744 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_OFST 0
7745 #define MC_CMD_NVRAM_READ_IN_V2_TYPE_LEN 4
7748 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_OFST 4
7749 #define MC_CMD_NVRAM_READ_IN_V2_OFFSET_LEN 4
7752 #define MC_CMD_NVRAM_READ_IN_V2_LENGTH_LEN 4
7756 * from. This allows it to perform a read-modify-write-verify with the write
7762 #define MC_CMD_NVRAM_READ_IN_V2_MODE_LEN 4
7767 #define MC_CMD_NVRAM_READ_IN_V2_DEFAULT 0x0
7771 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_CURRENT 0x1
7772 /* enum: Read from the non-current (i.e. to be updated) partition of an A/B
7775 #define MC_CMD_NVRAM_READ_IN_V2_TARGET_BACKUP 0x2
7781 #define MC_CMD_NVRAM_READ_OUT_LEN(num) (0+1*(num))
7782 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_NUM(len) (((len)-0)/1)
7783 #define MC_CMD_NVRAM_READ_OUT_READ_BUFFER_OFST 0
7793 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7796 #define MC_CMD_NVRAM_WRITE 0x3a
7806 #define MC_CMD_NVRAM_WRITE_IN_WRITE_BUFFER_NUM(len) (((len)-12)/1)
7807 #define MC_CMD_NVRAM_WRITE_IN_TYPE_OFST 0
7808 #define MC_CMD_NVRAM_WRITE_IN_TYPE_LEN 4
7811 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_OFST 4
7812 #define MC_CMD_NVRAM_WRITE_IN_OFFSET_LEN 4
7814 #define MC_CMD_NVRAM_WRITE_IN_LENGTH_LEN 4
7822 #define MC_CMD_NVRAM_WRITE_OUT_LEN 0
7828 * type==*PHY*. Returns: 0, EINVAL (bad type/offset/length), EACCES (if
7831 #define MC_CMD_NVRAM_ERASE 0x3b
7838 #define MC_CMD_NVRAM_ERASE_IN_TYPE_OFST 0
7839 #define MC_CMD_NVRAM_ERASE_IN_TYPE_LEN 4
7842 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_OFST 4
7843 #define MC_CMD_NVRAM_ERASE_IN_OFFSET_LEN 4
7845 #define MC_CMD_NVRAM_ERASE_IN_LENGTH_LEN 4
7848 #define MC_CMD_NVRAM_ERASE_OUT_LEN 0
7854 * required: PHY_LOCK if type==*PHY*. Returns: 0, EINVAL (bad type/offset/
7861 #define MC_CMD_NVRAM_UPDATE_FINISH 0x3c
7870 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_OFST 0
7871 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_TYPE_LEN 4
7874 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_OFST 4
7875 #define MC_CMD_NVRAM_UPDATE_FINISH_IN_REBOOT_LEN 4
7883 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_OFST 0
7884 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_TYPE_LEN 4
7887 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_OFST 4
7888 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_REBOOT_LEN 4
7890 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAGS_LEN 4
7892 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_IN_FLAG_REPORT_VERIFY_RESULT_LBN 0
7907 #define MC_CMD_NVRAM_UPDATE_FINISH_OUT_LEN 0
7921 * per-partition nvram lock in firmware is only released after the verification
7924 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_LEN 4
7927 * the field are marked with a prefix 'Internal-error'.
7929 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_OFST 0
7930 #define MC_CMD_NVRAM_UPDATE_FINISH_V2_OUT_RESULT_CODE_LEN 4
7931 /* enum: Invalid return code; only non-zero values are defined. Defined as
7934 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0
7936 #define MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1
7938 #define MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2
7940 #define MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3
7942 #define MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4
7943 /* enum: Error in message digest calculated over the reflash-header, payload
7944 * and reflash-trailer.
7946 #define MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5
7948 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6
7950 #define MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7
7952 #define MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8
7954 #define MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9
7956 #define MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa
7960 #define MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb
7961 /* enum: The image contains a test-signed certificate, but the adapter accepts
7964 #define MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc
7966 #define MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd
7967 /* enum: Internal-error. The signed image is missing the 'contents' section,
7970 #define MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe
7971 /* enum: Internal-error. The bundle header is invalid. */
7972 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf
7973 /* enum: Internal-error. The bundle does not have a valid reflash image layout.
7975 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10
7976 /* enum: Internal-error. The bundle has an inconsistent layout of components or
7979 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11
7980 /* enum: Internal-error. The bundle manifest is inconsistent with components in
7983 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12
7984 /* enum: Internal-error. The number of components in a bundle do not match the
7987 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13
7988 /* enum: Internal-error. The bundle contains too many components for the MC
7991 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14
7992 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent
7995 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15
7996 /* enum: Internal-error. The hash of a component does not match the hash stored
7999 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16
8000 /* enum: Internal-error. Component hash calculation failed. */
8001 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17
8002 /* enum: Internal-error. The component does not have a valid reflash image
8005 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18
8009 #define MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19
8010 /* enum: The update operation is in-progress. */
8011 #define MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a
8013 #define MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG 0x1b
8017 #define MC_CMD_NVRAM_VERIFY_RC_UNKNOWN_TYPE 0x1c
8023 * the field are marked with a prefix 'Internal-error'.
8025 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_RESULT_CODE_OFST 0
8026 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_RESULT_CODE_LEN 4
8027 /* enum: Invalid return code; only non-zero values are defined. Defined as
8030 /* MC_CMD_NVRAM_VERIFY_RC_UNKNOWN 0x0 */
8032 /* MC_CMD_NVRAM_VERIFY_RC_SUCCESS 0x1 */
8034 /* MC_CMD_NVRAM_VERIFY_RC_CMS_CHECK_FAILED 0x2 */
8036 /* MC_CMD_NVRAM_VERIFY_RC_INVALID_CMS_FORMAT 0x3 */
8038 /* MC_CMD_NVRAM_VERIFY_RC_MESSAGE_DIGEST_CHECK_FAILED 0x4 */
8039 /* enum: Error in message digest calculated over the reflash-header, payload
8040 * and reflash-trailer.
8042 /* MC_CMD_NVRAM_VERIFY_RC_BAD_MESSAGE_DIGEST 0x5 */
8044 /* MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHECK_FAILED 0x6 */
8046 /* MC_CMD_NVRAM_VERIFY_RC_NO_VALID_SIGNATURES 0x7 */
8048 /* MC_CMD_NVRAM_VERIFY_RC_TRUSTED_APPROVERS_CHECK_FAILED 0x8 */
8050 /* MC_CMD_NVRAM_VERIFY_RC_NO_TRUSTED_APPROVERS 0x9 */
8052 /* MC_CMD_NVRAM_VERIFY_RC_SIGNATURE_CHAIN_CHECK_FAILED 0xa */
8056 /* MC_CMD_NVRAM_VERIFY_RC_NO_SIGNATURE_MATCH 0xb */
8057 /* enum: The image contains a test-signed certificate, but the adapter accepts
8060 /* MC_CMD_NVRAM_VERIFY_RC_REJECT_TEST_SIGNED 0xc */
8062 /* MC_CMD_NVRAM_VERIFY_RC_SECURITY_LEVEL_DOWNGRADE 0xd */
8063 /* enum: Internal-error. The signed image is missing the 'contents' section,
8066 /* MC_CMD_NVRAM_VERIFY_RC_CONTENT_NOT_FOUND 0xe */
8067 /* enum: Internal-error. The bundle header is invalid. */
8068 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_CONTENT_HEADER_INVALID 0xf */
8069 /* enum: Internal-error. The bundle does not have a valid reflash image layout.
8071 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_REFLASH_IMAGE_INVALID 0x10 */
8072 /* enum: Internal-error. The bundle has an inconsistent layout of components or
8075 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_IMAGE_LAYOUT_INVALID 0x11 */
8076 /* enum: Internal-error. The bundle manifest is inconsistent with components in
8079 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_INVALID 0x12 */
8080 /* enum: Internal-error. The number of components in a bundle do not match the
8083 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_NUM_COMPONENTS_MISMATCH 0x13 */
8084 /* enum: Internal-error. The bundle contains too many components for the MC
8087 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_TOO_MANY_COMPONENTS 0x14 */
8088 /* enum: Internal-error. The bundle manifest has an invalid/inconsistent
8091 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_INVALID 0x15 */
8092 /* enum: Internal-error. The hash of a component does not match the hash stored
8095 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_MISMATCH 0x16 */
8096 /* enum: Internal-error. Component hash calculation failed. */
8097 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_MANIFEST_COMPONENT_HASH_FAILED 0x17 */
8098 /* enum: Internal-error. The component does not have a valid reflash image
8101 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_REFLASH_IMAGE_INVALID 0x18 */
8105 /* MC_CMD_NVRAM_VERIFY_RC_BUNDLE_COMPONENT_COPY_FAILED 0x19 */
8106 /* enum: The update operation is in-progress. */
8107 /* MC_CMD_NVRAM_VERIFY_RC_PENDING 0x1a */
8109 /* MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG 0x1b */
8113 /* MC_CMD_NVRAM_VERIFY_RC_UNKNOWN_TYPE 0x1c */
8117 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ACTIONS_REQUIRED_OFST 4
8118 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_ACTIONS_REQUIRED_LEN 4
8120 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_NONE 0x0
8122 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_FIRMWARE_REBOOT 0x1
8124 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_HOST_REBOOT 0x2
8126 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_FIRMWARE_AND_HOST_REBOOT 0x3
8128 #define MC_CMD_NVRAM_UPDATE_FINISH_V3_OUT_HOST_POWERCYCLE 0x4
8129 /* If the update failed with MC_CMD_NVRAM_VERIFY_RC_BAD_CONFIG, a null-
8130 * terminated US-ASCII string suitable for showing to the user.
8149 * REBOOT_ON_ASSERT=0.
8152 * DATALEN=0
8154 #define MC_CMD_REBOOT 0x3d
8160 #define MC_CMD_REBOOT_IN_LEN 4
8161 #define MC_CMD_REBOOT_IN_FLAGS_OFST 0
8162 #define MC_CMD_REBOOT_IN_FLAGS_LEN 4
8163 #define MC_CMD_REBOOT_FLAGS_AFTER_ASSERTION 0x1 /* enum */
8166 #define MC_CMD_REBOOT_OUT_LEN 0
8187 * backward compatibility, older host software can only use sensors in page 0.
8192 * page 0 of sensor information, with bit 31 in the sensor mask cleared.
8198 * Locks required: None Returns: 0
8200 #define MC_CMD_SENSOR_INFO 0x41
8206 #define MC_CMD_SENSOR_INFO_IN_LEN 0
8209 #define MC_CMD_SENSOR_INFO_EXT_IN_LEN 4
8212 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
8216 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_OFST 0
8217 #define MC_CMD_SENSOR_INFO_EXT_IN_PAGE_LEN 4
8223 * Page 0 contains sensors 0 to 30 (sensor 31 is the next page bit).
8227 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_OFST 0
8228 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_PAGE_LEN 4
8230 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_OFST 4
8231 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_FLAGS_LEN 4
8232 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_OFST 4
8233 #define MC_CMD_SENSOR_INFO_EXT_IN_V2_ENGINEERING_LBN 0
8237 #define MC_CMD_SENSOR_INFO_OUT_LENMIN 4
8240 #define MC_CMD_SENSOR_INFO_OUT_LEN(num) (4+8*(num))
8241 #define MC_CMD_SENSOR_INFO_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
8242 #define MC_CMD_SENSOR_INFO_OUT_MASK_OFST 0
8243 #define MC_CMD_SENSOR_INFO_OUT_MASK_LEN 4
8245 #define MC_CMD_SENSOR_CONTROLLER_TEMP 0x0
8247 #define MC_CMD_SENSOR_PHY_COMMON_TEMP 0x1
8249 #define MC_CMD_SENSOR_CONTROLLER_COOLING 0x2
8250 /* enum: Phy 0 temperature: degC */
8251 #define MC_CMD_SENSOR_PHY0_TEMP 0x3
8252 /* enum: Phy 0 cooling: bool */
8253 #define MC_CMD_SENSOR_PHY0_COOLING 0x4
8255 #define MC_CMD_SENSOR_PHY1_TEMP 0x5
8257 #define MC_CMD_SENSOR_PHY1_COOLING 0x6
8259 #define MC_CMD_SENSOR_IN_1V0 0x7
8261 #define MC_CMD_SENSOR_IN_1V2 0x8
8263 #define MC_CMD_SENSOR_IN_1V8 0x9
8265 #define MC_CMD_SENSOR_IN_2V5 0xa
8267 #define MC_CMD_SENSOR_IN_3V3 0xb
8269 #define MC_CMD_SENSOR_IN_12V0 0xc
8271 #define MC_CMD_SENSOR_IN_1V2A 0xd
8273 #define MC_CMD_SENSOR_IN_VREF 0xe
8275 #define MC_CMD_SENSOR_OUT_VAOE 0xf
8277 #define MC_CMD_SENSOR_AOE_TEMP 0x10
8279 #define MC_CMD_SENSOR_PSU_AOE_TEMP 0x11
8281 #define MC_CMD_SENSOR_PSU_TEMP 0x12
8282 /* enum: Fan 0 speed: RPM */
8283 #define MC_CMD_SENSOR_FAN_0 0x13
8285 #define MC_CMD_SENSOR_FAN_1 0x14
8287 #define MC_CMD_SENSOR_FAN_2 0x15
8289 #define MC_CMD_SENSOR_FAN_3 0x16
8290 /* enum: Fan 4 speed: RPM */
8291 #define MC_CMD_SENSOR_FAN_4 0x17
8293 #define MC_CMD_SENSOR_IN_VAOE 0x18
8295 #define MC_CMD_SENSOR_OUT_IAOE 0x19
8297 #define MC_CMD_SENSOR_IN_IAOE 0x1a
8299 #define MC_CMD_SENSOR_NIC_POWER 0x1b
8301 #define MC_CMD_SENSOR_IN_0V9 0x1c
8303 #define MC_CMD_SENSOR_IN_I0V9 0x1d
8305 #define MC_CMD_SENSOR_IN_I1V2 0x1e
8307 #define MC_CMD_SENSOR_PAGE0_NEXT 0x1f
8309 #define MC_CMD_SENSOR_IN_0V9_ADC 0x20
8311 #define MC_CMD_SENSOR_CONTROLLER_2_TEMP 0x21
8313 #define MC_CMD_SENSOR_VREG_INTERNAL_TEMP 0x22
8315 #define MC_CMD_SENSOR_VREG_0V9_TEMP 0x23
8317 #define MC_CMD_SENSOR_VREG_1V2_TEMP 0x24
8319 #define MC_CMD_SENSOR_CONTROLLER_VPTAT 0x25
8321 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP 0x26
8323 #define MC_CMD_SENSOR_CONTROLLER_VPTAT_EXTADC 0x27
8325 #define MC_CMD_SENSOR_CONTROLLER_INTERNAL_TEMP_EXTADC 0x28
8327 #define MC_CMD_SENSOR_AMBIENT_TEMP 0x29
8329 #define MC_CMD_SENSOR_AIRFLOW 0x2a
8331 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR 0x2b
8333 #define MC_CMD_SENSOR_VDD08D_VSS08D_CSR_EXTADC 0x2c
8335 #define MC_CMD_SENSOR_HOTPOINT_TEMP 0x2d
8336 /* enum: Port 0 PHY power switch over-current: bool */
8337 #define MC_CMD_SENSOR_PHY_POWER_PORT0 0x2e
8338 /* enum: Port 1 PHY power switch over-current: bool */
8339 #define MC_CMD_SENSOR_PHY_POWER_PORT1 0x2f
8340 /* enum: Mop-up microcontroller reference voltage: mV */
8341 #define MC_CMD_SENSOR_MUM_VCC 0x30
8343 #define MC_CMD_SENSOR_IN_0V9_A 0x31
8345 #define MC_CMD_SENSOR_IN_I0V9_A 0x32
8347 #define MC_CMD_SENSOR_VREG_0V9_A_TEMP 0x33
8349 #define MC_CMD_SENSOR_IN_0V9_B 0x34
8351 #define MC_CMD_SENSOR_IN_I0V9_B 0x35
8353 #define MC_CMD_SENSOR_VREG_0V9_B_TEMP 0x36
8355 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY 0x37
8357 #define MC_CMD_SENSOR_CCOM_AVREG_1V2_SUPPLY_EXTADC 0x38
8359 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY 0x39
8361 #define MC_CMD_SENSOR_CCOM_AVREG_1V8_SUPPLY_EXTADC 0x3a
8363 #define MC_CMD_SENSOR_CONTROLLER_RTS 0x3b
8365 #define MC_CMD_SENSOR_PAGE1_NEXT 0x3f
8369 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT 0x40
8371 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP 0x41
8375 #define MC_CMD_SENSOR_CONTROLLER_MASTER_VPTAT_EXTADC 0x42
8377 #define MC_CMD_SENSOR_CONTROLLER_MASTER_INTERNAL_TEMP_EXTADC 0x43
8381 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT 0x44
8383 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP 0x45
8387 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_VPTAT_EXTADC 0x46
8389 #define MC_CMD_SENSOR_CONTROLLER_SLAVE_INTERNAL_TEMP_EXTADC 0x47
8391 #define MC_CMD_SENSOR_SODIMM_VOUT 0x49
8392 /* enum: Temperature of SODIMM 0 (if installed): degC */
8393 #define MC_CMD_SENSOR_SODIMM_0_TEMP 0x4a
8395 #define MC_CMD_SENSOR_SODIMM_1_TEMP 0x4b
8396 /* enum: Voltage supplied to the QSFP #0 from their power supply: mV */
8397 #define MC_CMD_SENSOR_PHY0_VCC 0x4c
8399 #define MC_CMD_SENSOR_PHY1_VCC 0x4d
8401 #define MC_CMD_SENSOR_CONTROLLER_TDIODE_TEMP 0x4e
8403 #define MC_CMD_SENSOR_BOARD_FRONT_TEMP 0x4f
8405 #define MC_CMD_SENSOR_BOARD_BACK_TEMP 0x50
8407 #define MC_CMD_SENSOR_IN_I1V8 0x51
8409 #define MC_CMD_SENSOR_IN_I2V5 0x52
8411 #define MC_CMD_SENSOR_IN_I3V3 0x53
8413 #define MC_CMD_SENSOR_IN_I12V0 0x54
8415 #define MC_CMD_SENSOR_IN_1V3 0x55
8417 #define MC_CMD_SENSOR_IN_I1V3 0x56
8419 #define MC_CMD_SENSOR_ENGINEERING_1 0x57
8421 #define MC_CMD_SENSOR_ENGINEERING_2 0x58
8423 #define MC_CMD_SENSOR_ENGINEERING_3 0x59
8424 /* enum: Engineering sensor 4 */
8425 #define MC_CMD_SENSOR_ENGINEERING_4 0x5a
8427 #define MC_CMD_SENSOR_ENGINEERING_5 0x5b
8429 #define MC_CMD_SENSOR_ENGINEERING_6 0x5c
8431 #define MC_CMD_SENSOR_ENGINEERING_7 0x5d
8433 #define MC_CMD_SENSOR_ENGINEERING_8 0x5e
8435 #define MC_CMD_SENSOR_PAGE2_NEXT 0x5f
8437 #define MC_CMD_SENSOR_ENTRY_OFST 4
8439 #define MC_CMD_SENSOR_ENTRY_LO_OFST 4
8440 #define MC_CMD_SENSOR_ENTRY_LO_LEN 4
8444 #define MC_CMD_SENSOR_ENTRY_HI_LEN 4
8447 #define MC_CMD_SENSOR_ENTRY_MINNUM 0
8452 #define MC_CMD_SENSOR_INFO_EXT_OUT_LENMIN 4
8455 #define MC_CMD_SENSOR_INFO_EXT_OUT_LEN(num) (4+8*(num))
8456 #define MC_CMD_SENSOR_INFO_EXT_OUT_MC_CMD_SENSOR_ENTRY_NUM(len) (((len)-4)/8)
8457 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_OFST 0
8458 #define MC_CMD_SENSOR_INFO_EXT_OUT_MASK_LEN 4
8461 #define MC_CMD_SENSOR_INFO_EXT_OUT_NEXT_PAGE_OFST 0
8465 /* MC_CMD_SENSOR_ENTRY_OFST 4 */
8467 /* MC_CMD_SENSOR_ENTRY_LO_OFST 4 */
8468 /* MC_CMD_SENSOR_ENTRY_LO_LEN 4 */
8472 /* MC_CMD_SENSOR_ENTRY_HI_LEN 4 */
8475 /* MC_CMD_SENSOR_ENTRY_MINNUM 0 */
8481 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_OFST 0
8483 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN1_LBN 0
8489 #define MC_CMD_SENSOR_INFO_ENTRY_TYPEDEF_MIN2_OFST 4
8506 * If the request does not contain the LENGTH field then only sensors 0 to 30
8516 #define MC_CMD_READ_SENSORS 0x42
8523 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
8525 * If the address is 0xffffffffffffffff send the readings in the response (used
8528 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_OFST 0
8530 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_OFST 0
8531 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LEN 4
8532 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_LO_LBN 0
8534 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_OFST 4
8535 #define MC_CMD_READ_SENSORS_IN_DMA_ADDR_HI_LEN 4
8541 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
8543 * If the address is 0xffffffffffffffff send the readings in the response (used
8546 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_OFST 0
8548 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_OFST 0
8549 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LEN 4
8550 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_LO_LBN 0
8552 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_OFST 4
8553 #define MC_CMD_READ_SENSORS_EXT_IN_DMA_ADDR_HI_LEN 4
8558 #define MC_CMD_READ_SENSORS_EXT_IN_LENGTH_LEN 4
8562 /* DMA address of host buffer for sensor readings (must be 4Kbyte aligned).
8564 * If the address is 0xffffffffffffffff send the readings in the response (used
8567 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_OFST 0
8569 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_OFST 0
8570 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LEN 4
8571 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_LO_LBN 0
8573 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_OFST 4
8574 #define MC_CMD_READ_SENSORS_EXT_IN_V2_DMA_ADDR_HI_LEN 4
8579 #define MC_CMD_READ_SENSORS_EXT_IN_V2_LENGTH_LEN 4
8582 #define MC_CMD_READ_SENSORS_EXT_IN_V2_FLAGS_LEN 4
8584 #define MC_CMD_READ_SENSORS_EXT_IN_V2_ENGINEERING_LBN 0
8588 #define MC_CMD_READ_SENSORS_OUT_LEN 0
8591 #define MC_CMD_READ_SENSORS_EXT_OUT_LEN 0
8594 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_LEN 4
8595 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_OFST 0
8597 #define MC_CMD_SENSOR_VALUE_ENTRY_TYPEDEF_VALUE_LBN 0
8602 #define MC_CMD_SENSOR_STATE_OK 0x0
8604 #define MC_CMD_SENSOR_STATE_WARNING 0x1
8606 #define MC_CMD_SENSOR_STATE_FATAL 0x2
8608 #define MC_CMD_SENSOR_STATE_BROKEN 0x3
8610 #define MC_CMD_SENSOR_STATE_NO_READING 0x4
8612 #define MC_CMD_SENSOR_STATE_INIT_FAILED 0x5
8627 * code: 0
8629 #define MC_CMD_GET_PHY_STATE 0x43
8635 #define MC_CMD_GET_PHY_STATE_IN_LEN 0
8643 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_OFST 0
8645 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_OFST 0
8646 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_LEN 4
8647 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LO_LBN 0
8649 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_OFST 4
8650 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_HI_LEN 4
8654 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_OFST 0
8655 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
8656 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 0
8657 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
8660 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 0
8662 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_LBN 0
8663 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
8665 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
8667 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
8670 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
8672 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LINK_END_OFST 4
8673 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_LINK_END_LEN 4
8674 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_OFST 0
8676 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_OFST 0
8677 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_LEN 4
8678 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_LO_LBN 0
8680 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_OFST 4
8681 #define MC_CMD_GET_PHY_STATE_IN_V2_TARGET_FLAT_HI_LEN 4
8686 #define MC_CMD_GET_PHY_STATE_OUT_LEN 4
8687 #define MC_CMD_GET_PHY_STATE_OUT_STATE_OFST 0
8688 #define MC_CMD_GET_PHY_STATE_OUT_STATE_LEN 4
8690 #define MC_CMD_PHY_STATE_OK 0x1
8692 #define MC_CMD_PHY_STATE_ZOMBIE 0x2
8697 * Retrieve ID of any WoL filters. Locks required: None. Returns: 0, ENOSYS
8699 #define MC_CMD_WOL_FILTER_GET 0x45
8705 #define MC_CMD_WOL_FILTER_GET_IN_LEN 0
8708 #define MC_CMD_WOL_FILTER_GET_OUT_LEN 4
8709 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_OFST 0
8710 #define MC_CMD_WOL_FILTER_GET_OUT_FILTER_ID_LEN 4
8716 * understand the given workaround number - which should not be treated as a
8718 * workaround, that's between the driver and the mcfw on a per-workaround
8719 * basis. Locks required: None. Returns: 0, EINVAL .
8721 #define MC_CMD_WORKAROUND 0x4a
8729 #define MC_CMD_WORKAROUND_IN_TYPE_OFST 0
8730 #define MC_CMD_WORKAROUND_IN_TYPE_LEN 4
8732 #define MC_CMD_WORKAROUND_BUG17230 0x1
8734 #define MC_CMD_WORKAROUND_BUG35388 0x2
8736 #define MC_CMD_WORKAROUND_BUG35017 0x3
8738 #define MC_CMD_WORKAROUND_BUG41750 0x4
8740 * - before adding code that queries this workaround, remember that there's
8744 #define MC_CMD_WORKAROUND_BUG42008 0x5
8752 #define MC_CMD_WORKAROUND_BUG26807 0x6
8754 #define MC_CMD_WORKAROUND_BUG61265 0x7
8755 /* 0 = disable the workaround indicated by TYPE; any non-zero value = enable
8758 #define MC_CMD_WORKAROUND_IN_ENABLED_OFST 4
8759 #define MC_CMD_WORKAROUND_IN_ENABLED_LEN 4
8762 #define MC_CMD_WORKAROUND_OUT_LEN 0
8767 #define MC_CMD_WORKAROUND_EXT_OUT_LEN 4
8768 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_OFST 0
8769 #define MC_CMD_WORKAROUND_EXT_OUT_FLAGS_LEN 4
8770 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_OFST 0
8771 #define MC_CMD_WORKAROUND_EXT_OUT_FLR_DONE_LBN 0
8777 * Read media-specific data from PHY (e.g. SFP/SFP+ module ID information for
8780 * output data, are interpreted on a per-type basis. For SFP+, PAGE=0 or 1
8781 * returns a 128-byte block read from module I2C address 0xA0 offset 0 or 0x80.
8782 * For QSFP, PAGE=-1 is the lower (unbanked) page. PAGE=2 is the EEPROM and
8786 * of "0xffff:0xffff" retrieves the lower (unbanked) page. Locks required -
8787 * None. Return code - 0.
8789 #define MC_CMD_GET_PHY_MEDIA_INFO 0x4b
8795 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_LEN 4
8796 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_OFST 0
8797 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_PAGE_LEN 4
8798 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_OFST 0
8799 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_PAGE_LBN 0
8801 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_DSFP_BANK_OFST 0
8807 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_PAGE_OFST 0
8808 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_PAGE_LEN 4
8809 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_OFST 0
8810 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_PAGE_LBN 0
8812 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_DSFP_BANK_OFST 0
8819 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_OFST 4
8821 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_OFST 4
8822 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LO_LEN 4
8826 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_HI_LEN 4
8830 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_OFST 4
8831 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_LEN 4
8832 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FLAT_OFST 4
8833 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FLAT_LEN 4
8836 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_MPORT_ID_OFST 4
8839 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_PPORT_ID_WIDTH 4
8841 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
8843 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
8846 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_MPORT_SELECTOR_FUNC_VF_ID_OFST 4
8849 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_LINK_END_LEN 4
8850 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_OFST 4
8852 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_OFST 4
8853 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_LO_LEN 4
8857 #define MC_CMD_GET_PHY_MEDIA_INFO_IN_V2_TARGET_FLAT_HI_LEN 4
8865 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_LEN(num) (4+1*(num))
8866 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_NUM(len) (((len)-4)/1)
8868 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_OFST 0
8869 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATALEN_LEN 4
8870 #define MC_CMD_GET_PHY_MEDIA_INFO_OUT_DATA_OFST 4
8882 #define MC_CMD_NVRAM_TEST 0x4c
8888 #define MC_CMD_NVRAM_TEST_IN_LEN 4
8889 #define MC_CMD_NVRAM_TEST_IN_TYPE_OFST 0
8890 #define MC_CMD_NVRAM_TEST_IN_TYPE_LEN 4
8895 #define MC_CMD_NVRAM_TEST_OUT_LEN 4
8896 #define MC_CMD_NVRAM_TEST_OUT_RESULT_OFST 0
8897 #define MC_CMD_NVRAM_TEST_OUT_RESULT_LEN 4
8899 #define MC_CMD_NVRAM_TEST_PASS 0x0
8901 #define MC_CMD_NVRAM_TEST_FAIL 0x1
8903 #define MC_CMD_NVRAM_TEST_NOTSUPP 0x2
8909 * none. Returns: 0, EINVAL (bad type).
8911 #define MC_CMD_NVRAM_PARTITIONS 0x51
8917 #define MC_CMD_NVRAM_PARTITIONS_IN_LEN 0
8920 #define MC_CMD_NVRAM_PARTITIONS_OUT_LENMIN 4
8923 #define MC_CMD_NVRAM_PARTITIONS_OUT_LEN(num) (4+4*(num))
8924 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_NUM(len) (((len)-4)/4)
8926 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_OFST 0
8927 #define MC_CMD_NVRAM_PARTITIONS_OUT_NUM_PARTITIONS_LEN 4
8929 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_OFST 4
8930 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_LEN 4
8931 #define MC_CMD_NVRAM_PARTITIONS_OUT_TYPE_ID_MINNUM 0
8939 * none. Returns: 0, EINVAL (bad type).
8941 #define MC_CMD_NVRAM_METADATA 0x52
8947 #define MC_CMD_NVRAM_METADATA_IN_LEN 4
8949 #define MC_CMD_NVRAM_METADATA_IN_TYPE_OFST 0
8950 #define MC_CMD_NVRAM_METADATA_IN_TYPE_LEN 4
8957 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_NUM(len) (((len)-20)/1)
8959 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_OFST 0
8960 #define MC_CMD_NVRAM_METADATA_OUT_TYPE_LEN 4
8961 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_OFST 4
8962 #define MC_CMD_NVRAM_METADATA_OUT_FLAGS_LEN 4
8963 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_OFST 4
8964 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_VALID_LBN 0
8966 #define MC_CMD_NVRAM_METADATA_OUT_VERSION_VALID_OFST 4
8969 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_VALID_OFST 4
8974 #define MC_CMD_NVRAM_METADATA_OUT_SUBTYPE_LEN 4
8984 /* 4th component of W.X.Y.Z version number for content of this partition */
8987 /* Zero-terminated string describing the content of this partition */
8990 #define MC_CMD_NVRAM_METADATA_OUT_DESCRIPTION_MINNUM 0
8999 #define MC_CMD_GET_MAC_ADDRESSES 0x55
9005 #define MC_CMD_GET_MAC_ADDRESSES_IN_LEN 0
9010 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE_OFST 0
9017 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_COUNT_LEN 4
9020 #define MC_CMD_GET_MAC_ADDRESSES_OUT_MAC_STRIDE_LEN 4
9027 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_OFST 0
9028 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LEN 4
9029 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_WARNING_LBN 0
9032 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_OFST 4
9033 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_CRITICAL_LEN 4
9038 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_LO_FATAL_LEN 4
9043 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_WARNING_LEN 4
9048 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_CRITICAL_LEN 4
9053 #define MC_CMD_DYNAMIC_SENSORS_LIMITS_HI_FATAL_LEN 4
9065 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_OFST 0
9066 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LEN 4
9067 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_HANDLE_LBN 0
9069 /* A human-readable name for the sensor (zero terminated string, max 32 bytes)
9071 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_NAME_OFST 4
9079 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TYPE_LEN 4
9081 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_VOLTAGE 0x0
9083 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_CURRENT 0x1
9085 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_POWER 0x2
9087 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_TEMPERATURE 0x3
9089 #define MC_CMD_DYNAMIC_SENSORS_DESCRIPTION_FAN 0x4
9104 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_OFST 0
9105 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LEN 4
9106 #define MC_CMD_DYNAMIC_SENSORS_READING_HANDLE_LBN 0
9109 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_OFST 4
9110 #define MC_CMD_DYNAMIC_SENSORS_READING_VALUE_LEN 4
9115 #define MC_CMD_DYNAMIC_SENSORS_READING_STATE_LEN 4
9117 #define MC_CMD_DYNAMIC_SENSORS_READING_OK 0x0
9119 #define MC_CMD_DYNAMIC_SENSORS_READING_WARNING 0x1
9121 #define MC_CMD_DYNAMIC_SENSORS_READING_CRITICAL 0x2
9123 #define MC_CMD_DYNAMIC_SENSORS_READING_FATAL 0x3
9125 #define MC_CMD_DYNAMIC_SENSORS_READING_BROKEN 0x4
9127 #define MC_CMD_DYNAMIC_SENSORS_READING_NO_READING 0x5
9129 #define MC_CMD_DYNAMIC_SENSORS_READING_INIT_FAILED 0x6
9139 * MC_CMD_READ_SENSORS command. On multi-MC systems this may include sensors
9157 #define MC_CMD_DYNAMIC_SENSORS_LIST 0x66
9163 #define MC_CMD_DYNAMIC_SENSORS_LIST_IN_LEN 0
9169 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_LEN(num) (8+4*(num))
9170 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_NUM(len) (((len)-8)/4)
9174 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_OFST 0
9175 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_GENERATION_LEN 4
9179 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_OFST 4
9180 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_COUNT_LEN 4
9183 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_LEN 4
9184 #define MC_CMD_DYNAMIC_SENSORS_LIST_OUT_HANDLES_MINNUM 0
9200 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS 0x67
9206 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LENMIN 0
9209 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_LEN(num) (0+4*(num))
9210 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_NUM(len) (((len)-0)/4)
9212 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_OFST 0
9213 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_LEN 4
9214 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_IN_HANDLES_MINNUM 0
9219 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LENMIN 0
9222 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_LEN(num) (0+64*(num))
9223 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_NUM(len) (((len)-0)/64)
9225 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_OFST 0
9227 #define MC_CMD_DYNAMIC_SENSORS_GET_DESCRIPTIONS_OUT_SENSORS_MINNUM 0
9245 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS 0x68
9251 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LENMIN 0
9254 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_LEN(num) (0+4*(num))
9255 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_NUM(len) (((len)-0)/4)
9257 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_OFST 0
9258 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_LEN 4
9259 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_IN_HANDLES_MINNUM 0
9264 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LENMIN 0
9267 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_LEN(num) (0+12*(num))
9268 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_NUM(len) (((len)-0)/12)
9270 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_OFST 0
9272 #define MC_CMD_DYNAMIC_SENSORS_GET_READINGS_OUT_VALUES_MINNUM 0
9277 #define MC_CMD_MAC_FLAGS_LEN 4
9281 #define MC_CMD_MAC_FLAGS_MASK_OFST 0
9282 #define MC_CMD_MAC_FLAGS_MASK_LEN 4
9287 #define MC_CMD_MAC_FLAGS_FLAG_INCLUDE_FCS 0x0
9288 #define MC_CMD_MAC_FLAGS_MASK_LBN 0
9292 #define MC_CMD_TRANSMISSION_MODE_LEN 4
9293 #define MC_CMD_TRANSMISSION_MODE_MASK_OFST 0
9294 #define MC_CMD_TRANSMISSION_MODE_MASK_LEN 4
9296 #define MC_CMD_TRANSMISSION_MODE_PROMSC_MODE 0x0 /* enum */
9297 #define MC_CMD_TRANSMISSION_MODE_UNCST_MODE 0x1 /* enum */
9298 #define MC_CMD_TRANSMISSION_MODE_BRDCST_MODE 0x2 /* enum */
9299 #define MC_CMD_TRANSMISSION_MODE_MASK_LBN 0
9303 #define MC_CMD_MAC_CONFIG_OPTIONS_LEN 4
9304 #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_OFST 0
9305 #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_LEN 4
9308 #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_ADDR 0x0
9310 #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_MAX_FRAME_LEN 0x1
9312 #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_FCNTL 0x2
9314 #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_TRANSMISSION_MODE 0x3
9316 #define MC_CMD_MAC_CONFIG_OPTIONS_CFG_INCLUDE_FCS 0x4
9317 #define MC_CMD_MAC_CONFIG_OPTIONS_MASK_LBN 0
9323 * Set MAC configuration. Return code: 0, EINVAL, ENOTSUP
9325 #define MC_CMD_MAC_CTRL 0x1df
9333 #define MC_CMD_MAC_CTRL_IN_PORT_HANDLE_OFST 0
9334 #define MC_CMD_MAC_CTRL_IN_PORT_HANDLE_LEN 4
9338 #define MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_OFST 4
9339 #define MC_CMD_MAC_CTRL_IN_CONTROL_FLAGS_LEN 4
9347 #define MC_CMD_MAC_CTRL_IN_ADDR_LO_LEN 4
9351 #define MC_CMD_MAC_CTRL_IN_ADDR_HI_LEN 4
9356 #define MC_CMD_MAC_CTRL_IN_MAX_FRAME_LEN_LEN 4
9359 #define MC_CMD_MAC_CTRL_IN_FCNTL_LEN 4
9367 #define MC_CMD_MAC_CTRL_IN_TRANSMISSION_MODE_LEN 4
9373 #define MC_CMD_MAC_CTRL_IN_FLAGS_LEN 4
9381 #define MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_OFST 0
9382 #define MC_CMD_MAC_CTRL_IN_V2_PORT_HANDLE_LEN 4
9386 #define MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_OFST 4
9387 #define MC_CMD_MAC_CTRL_IN_V2_CONTROL_FLAGS_LEN 4
9395 #define MC_CMD_MAC_CTRL_IN_V2_ADDR_LO_LEN 4
9399 #define MC_CMD_MAC_CTRL_IN_V2_ADDR_HI_LEN 4
9404 #define MC_CMD_MAC_CTRL_IN_V2_MAX_FRAME_LEN_LEN 4
9407 #define MC_CMD_MAC_CTRL_IN_V2_FCNTL_LEN 4
9415 #define MC_CMD_MAC_CTRL_IN_V2_TRANSMISSION_MODE_LEN 4
9421 #define MC_CMD_MAC_CTRL_IN_V2_FLAGS_LEN 4
9425 /* Priority-based flow control mask (QBB). PRIO7 corresponds to the highest
9432 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO0 0x0 /* enum */
9433 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO1 0x1 /* enum */
9434 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO2 0x2 /* enum */
9435 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO3 0x3 /* enum */
9436 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO4 0x4 /* enum */
9437 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO5 0x5 /* enum */
9438 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO6 0x6 /* enum */
9439 #define MC_CMD_MAC_CTRL_IN_V2_QBB_PRIO7 0x7 /* enum */
9442 #define MC_CMD_MAC_CTRL_OUT_LEN 0
9447 * Read the MAC state. Return code: 0, ETIME.
9449 #define MC_CMD_MAC_STATE 0x1e0
9455 #define MC_CMD_MAC_STATE_IN_LEN 4
9457 #define MC_CMD_MAC_STATE_IN_PORT_HANDLE_OFST 0
9458 #define MC_CMD_MAC_STATE_IN_PORT_HANDLE_LEN 4
9463 #define MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_OFST 0
9464 #define MC_CMD_MAC_STATE_OUT_MAX_FRAME_LEN_LEN 4
9466 #define MC_CMD_MAC_STATE_OUT_FCNTL_OFST 4
9467 #define MC_CMD_MAC_STATE_OUT_FCNTL_LEN 4
9475 #define MC_CMD_MAC_STATE_OUT_ADDR_LO_LEN 4
9479 #define MC_CMD_MAC_STATE_OUT_ADDR_HI_LEN 4
9484 #define MC_CMD_MAC_STATE_OUT_MAC_FAULT_FLAGS_LEN 4
9487 #define MC_CMD_MAC_STATE_OUT_LOCAL 0x0
9489 #define MC_CMD_MAC_STATE_OUT_REMOTE 0x1
9491 #define MC_CMD_MAC_STATE_OUT_PENDING_RECONFIG 0x2
9496 #define MC_CMD_MAC_STATE_OUT_FLAGS_LEN 4
9504 #define MC_CMD_MAC_STATE_OUT_TRANSMISSION_MODE_LEN 4
9512 #define MC_CMD_MAC_STATE_OUT_CONTROL_FLAGS_LEN 4
9522 * code: 0, ENOENT
9524 #define MC_CMD_GET_ASSIGNED_PORT_HANDLE 0x1e2
9530 #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_IN_LEN 0
9533 #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_LEN 4
9535 #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_OFST 0
9536 #define MC_CMD_GET_ASSIGNED_PORT_HANDLE_OUT_PORT_HANDLE_LEN 4
9539 #define MC_CMD_STAT_ID_LEN 4
9540 #define MC_CMD_STAT_ID_SOURCE_ID_OFST 0
9544 #define MC_CMD_STAT_ID_MARKER 0x1
9546 #define MC_CMD_STAT_ID_MAC 0x2
9548 #define MC_CMD_STAT_ID_PHY 0x3
9549 #define MC_CMD_STAT_ID_SOURCE_ID_LBN 0
9558 #define MC_CMD_STAT_ID_GENERATION_START 0x1
9567 #define MC_CMD_STAT_ID_GENERATION_END 0x2
9574 #define MC_CMD_STAT_ID_TX_PKTS 0x1
9576 #define MC_CMD_STAT_ID_TX_PAUSE_PKTS 0x2
9578 #define MC_CMD_STAT_ID_TX_CONTROL_PKTS 0x3
9580 #define MC_CMD_STAT_ID_TX_UNICAST_PKTS 0x4
9582 #define MC_CMD_STAT_ID_TX_MULTICAST_PKTS 0x5
9584 #define MC_CMD_STAT_ID_TX_BROADCAST_PKTS 0x6
9586 #define MC_CMD_STAT_ID_TX_BYTES 0x7
9588 #define MC_CMD_STAT_ID_TX_BAD_BYTES 0x8
9590 #define MC_CMD_STAT_ID_TX_GOOD_BYTES 0x9
9592 #define MC_CMD_STAT_ID_TX_LT64_PKTS 0xa
9594 #define MC_CMD_STAT_ID_TX_64_PKTS 0xb
9596 #define MC_CMD_STAT_ID_TX_65_TO_127_PKTS 0xc
9598 #define MC_CMD_STAT_ID_TX_128_TO_255_PKTS 0xd
9600 #define MC_CMD_STAT_ID_TX_256_TO_511_PKTS 0xe
9602 #define MC_CMD_STAT_ID_TX_512_TO_1023_PKTS 0xf
9604 #define MC_CMD_STAT_ID_TX_1024_TO_15XX_PKTS 0x10
9606 #define MC_CMD_STAT_ID_TX_15XX_TO_JUMBO_PKTS 0x11
9608 #define MC_CMD_STAT_ID_TX_GTJUMBO_PKTS 0x12
9610 #define MC_CMD_STAT_ID_TX_BAD_FCS_PKTS 0x13
9612 #define MC_CMD_STAT_ID_TX_GOOD_FCS_PKTS 0x14
9614 #define MC_CMD_STAT_ID_RX_PKTS 0x15
9616 #define MC_CMD_STAT_ID_RX_PAUSE_PKTS 0x16
9618 #define MC_CMD_STAT_ID_RX_GOOD_PKTS 0x17
9620 #define MC_CMD_STAT_ID_RX_BAD_PKTS 0x18
9622 #define MC_CMD_STAT_ID_RX_CONTROL_PKTS 0x19
9624 #define MC_CMD_STAT_ID_RX_UNICAST_PKTS 0x1a
9626 #define MC_CMD_STAT_ID_RX_MULTICAST_PKTS 0x1b
9628 #define MC_CMD_STAT_ID_RX_BROADCAST_PKTS 0x1c
9630 #define MC_CMD_STAT_ID_RX_BYTES 0x1d
9632 #define MC_CMD_STAT_ID_RX_BAD_BYTES 0x1e
9634 #define MC_CMD_STAT_ID_RX_GOOD_BYTES 0x1f
9636 #define MC_CMD_STAT_ID_RX_64_PKTS 0x20
9638 #define MC_CMD_STAT_ID_RX_65_TO_127_PKTS 0x21
9640 #define MC_CMD_STAT_ID_RX_128_TO_255_PKTS 0x22
9642 #define MC_CMD_STAT_ID_RX_256_TO_511_PKTS 0x23
9644 #define MC_CMD_STAT_ID_RX_512_TO_1023_PKTS 0x24
9646 #define MC_CMD_STAT_ID_RX_1024_TO_15XX_PKTS 0x25
9648 #define MC_CMD_STAT_ID_RX_15XX_TO_JUMBO_PKTS 0x26
9650 #define MC_CMD_STAT_ID_RX_GTJUMBO_PKTS 0x27
9652 #define MC_CMD_STAT_ID_RX_UNDERSIZE_PKTS 0x28
9654 #define MC_CMD_STAT_ID_RX_BAD_FCS_PKTS 0x29
9656 #define MC_CMD_STAT_ID_RX_GOOD_FCS_PKTS 0x2a
9658 #define MC_CMD_STAT_ID_RX_OVERFLOW_PKTS 0x2b
9660 #define MC_CMD_STAT_ID_RX_SYMBOL_ERROR_PKTS 0x2c
9662 #define MC_CMD_STAT_ID_RX_ALIGN_ERROR_PKTS 0x2d
9664 #define MC_CMD_STAT_ID_RX_LENGTH_ERROR_PKTS 0x2e
9666 #define MC_CMD_STAT_ID_RX_INTERNAL_ERROR_PKTS 0x2f
9671 #define MC_CMD_STAT_ID_RX_JABBER_PKTS 0x30
9674 #define MC_CMD_STAT_ID_RX_NODESC_DROPS 0x31
9675 /* enum: Packets received with lanes 0 and 1 character error. */
9676 #define MC_CMD_STAT_ID_RX_LANES01_CHAR_ERR 0x32
9678 #define MC_CMD_STAT_ID_RX_LANES23_CHAR_ERR 0x33
9679 /* enum: Packets received with lanes 0 and 1 disparity error. */
9680 #define MC_CMD_STAT_ID_RX_LANES01_DISP_ERR 0x34
9682 #define MC_CMD_STAT_ID_RX_LANES23_DISP_ERR 0x35
9684 #define MC_CMD_STAT_ID_RX_MATCH_FAULT 0x36
9691 /* enum: Number of uncorrected FEC codewords on link (RS-FEC only from Medford2
9694 #define MC_CMD_STAT_ID_FEC_UNCORRECTED_ERRORS 0x1
9695 /* enum: Number of corrected FEC codewords on link (RS-FEC only from Medford2
9698 #define MC_CMD_STAT_ID_FEC_CORRECTED_ERRORS 0x2
9699 /* enum: Number of corrected 10-bit symbol errors, lane 0 (RS-FEC only) */
9700 #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE0 0x3
9701 /* enum: Number of corrected 10-bit symbol errors, lane 1 (RS-FEC only) */
9702 #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE1 0x4
9703 /* enum: Number of corrected 10-bit symbol errors, lane 2 (RS-FEC only) */
9704 #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE2 0x5
9705 /* enum: Number of corrected 10-bit symbol errors, lane 3 (RS-FEC only) */
9706 #define MC_CMD_STAT_ID_FEC_CORRECTED_SYMBOLS_LANE3 0x6
9715 #define MC_CMD_STAT_DESC_STAT_ID_OFST 0
9716 #define MC_CMD_STAT_DESC_STAT_ID_LEN 4
9717 #define MC_CMD_STAT_DESC_STAT_ID_LBN 0
9720 #define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_OFST 0
9722 #define MC_CMD_STAT_DESC_STAT_ID_SOURCE_ID_LBN 0
9737 #define MC_CMD_STAT_DESC_STAT_INDEX_OFST 4
9741 /* Reserved for future extension (e.g. flags field) - currently always 0. */
9762 * size, as well as the dynamic runtime updates of the list. Returns: 0 on
9763 * success, ENOENT on non-existent port handle
9765 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR 0x1e3
9773 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_OFST 0
9774 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_PORT_HANDLE_LEN 4
9776 * the MCDI response. Should be set to 0 on initial request, and on subsequent
9780 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_OFST 4
9781 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_IN_OFFSET_LEN 4
9788 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_NUM(len) (((len)-20)/8)
9792 * always set to 0.
9794 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_OFST 0
9795 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_GENERATION_LEN 4
9802 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_OFST 4
9803 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_DMA_BUFFER_SIZE_LEN 4
9805 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_FLAGS_LEN 4
9807 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_MORE_ENTRIES_LBN 0
9815 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_SIZE_LEN 4
9818 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRY_COUNT_LEN 4
9827 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_LO_LEN 4
9831 #define MC_CMD_MAC_STATISTICS_DESCRIPTOR_OUT_ENTRIES_HI_LEN 4
9846 * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
9847 * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
9850 #define MC_CMD_MAC_STATISTICS 0x1e4
9858 #define MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_OFST 0
9859 #define MC_CMD_MAC_STATISTICS_IN_PORT_HANDLE_LEN 4
9861 #define MC_CMD_MAC_STATISTICS_IN_CMD_OFST 4
9862 #define MC_CMD_MAC_STATISTICS_IN_CMD_LEN 4
9863 #define MC_CMD_MAC_STATISTICS_IN_DMA_OFST 4
9864 #define MC_CMD_MAC_STATISTICS_IN_DMA_LBN 0
9866 #define MC_CMD_MAC_STATISTICS_IN_CLEAR_OFST 4
9869 #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
9872 #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
9875 #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
9876 #define MC_CMD_MAC_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
9878 #define MC_CMD_MAC_STATISTICS_IN_PERIOD_MS_OFST 4
9887 #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_LO_LEN 4
9891 #define MC_CMD_MAC_STATISTICS_IN_DMA_ADDR_HI_LEN 4
9900 #define MC_CMD_MAC_STATISTICS_IN_DMA_LEN_LEN 4
9906 #define MC_CMD_MAC_STATISTICS_OUT_LEN(num) (4+1*(num))
9907 #define MC_CMD_MAC_STATISTICS_OUT_DATA_NUM(len) (((len)-4)/1)
9909 #define MC_CMD_MAC_STATISTICS_OUT_DATALEN_OFST 0
9910 #define MC_CMD_MAC_STATISTICS_OUT_DATALEN_LEN 4
9911 #define MC_CMD_MAC_STATISTICS_OUT_DATA_OFST 4
9922 #define NET_PORT_HANDLE_DESC_PORT_HANDLE_OFST 0
9923 #define NET_PORT_HANDLE_DESC_PORT_HANDLE_LEN 4
9924 #define NET_PORT_HANDLE_DESC_PORT_HANDLE_LBN 0
9929 #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_OFST 4
9931 #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_OFST 4
9932 #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_LO_LEN 4
9936 #define NET_PORT_HANDLE_DESC_PORT_PROPERTIES_HI_LEN 4
9939 #define NET_PORT_HANDLE_DESC_PORT_TYPE_OFST 4
9940 #define NET_PORT_HANDLE_DESC_PORT_TYPE_LBN 0
9942 #define NET_PORT_HANDLE_DESC_PHYSICAL 0x0 /* enum */
9943 #define NET_PORT_HANDLE_DESC_VIRTUAL 0x1 /* enum */
9944 #define NET_PORT_HANDLE_DESC_MPORT 0x2 /* enum */
9945 #define NET_PORT_HANDLE_DESC_IS_ZOMBIE_OFST 4
9954 #define NET_PORT_HANDLE_DESC_UNKNOWN 0x0
9956 #define NET_PORT_HANDLE_DESC_PRESENT 0x1
9958 #define NET_PORT_HANDLE_DESC_ADDED 0x2
9960 #define NET_PORT_HANDLE_DESC_DELETED 0x3
9964 * the port. It is represented as a zero-terminated ASCII string and assigned
9980 * After a start-of-day port enumeration, firmware keeps track of all available
9984 * ports. The command is also clear-on-read and repeated calls will drain the
9987 #define MC_CMD_ENUM_PORTS 0x1e5
9993 #define MC_CMD_ENUM_PORTS_IN_LEN 0
10000 #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_NUM(len) (((len)-12)/1)
10002 #define MC_CMD_ENUM_PORTS_OUT_FLAGS_OFST 0
10003 #define MC_CMD_ENUM_PORTS_OUT_FLAGS_LEN 4
10004 #define MC_CMD_ENUM_PORTS_OUT_MORE_OFST 0
10005 #define MC_CMD_ENUM_PORTS_OUT_MORE_LBN 0
10008 #define MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_OFST 4
10009 #define MC_CMD_ENUM_PORTS_OUT_PORT_COUNT_LEN 4
10011 #define MC_CMD_ENUM_PORTS_OUT_SIZEOF_NET_PORT_HANDLE_DESC_LEN 4
10019 #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_MINNUM 0
10024 #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_HANDLE_LEN 4
10028 #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_LO_LEN 4
10032 #define MC_CMD_ENUM_PORTS_OUT_PORT_HANDLES_PORT_PROPERTIES_HI_LEN 4
10052 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES 0x1e6
10058 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_LEN 4
10060 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_OFST 0
10061 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_IN_PORT_HANDLE_LEN 4
10066 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_TECH_ABILITIES_MASK_OFST 0
10078 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_PREFERRED_FEC_MASK_LEN 4
10082 /* SFF-8042 code reported by the module. */
10089 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 /* enum */
10090 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_COPPER 0x1 /* enum */
10091 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_OPTICAL 0x2 /* enum */
10092 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BACKPLANE 0x3 /* enum */
10097 /* MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_UNKNOWN 0x0 */
10098 /* enum: Ethernet over twisted-pair copper cables for distances up to 100
10101 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASET 0x1
10102 /* enum: Ethernet over twin-axial, balanced copper cable. */
10103 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_CR 0x2
10105 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KX 0x3
10109 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KR 0x4
10111 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_KP 0x5
10113 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_BASEX 0x6
10117 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_SR 0x7
10121 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LR_ER_FR 0x8
10123 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_LRM 0x9
10127 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_VR 0xa
10128 /* enum: BASE-R encoding and PAM4 over single-mode fiber with reach up to at
10131 #define MC_CMD_GET_TRANSCEIVER_PROPERTIES_OUT_DR 0xb
10136 * connected module. See SFF-8472/CMIS specifications for details.
10150 * for the connected module. See SFF-8472/CMIS specifications for details.
10163 #define MC_CMD_GET_FIXED_PORT_PROPERTIES 0x1e7
10175 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_LEN 4
10177 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_OFST 0
10178 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_IN_PORT_HANDLE_LEN 4
10183 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_OFST 0
10186 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_TECH_MASK_OFST 0
10189 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_MASK_LEN 4
10191 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_ABILITIES_FEC_REQ_LEN 4
10219 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_MAX_FRAME_LEN_LEN 4
10224 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_ABILITIES_OFST 0
10251 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_MAX_FRAME_LEN_LEN 4
10258 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_LO_LEN 4
10262 #define MC_CMD_GET_FIXED_PORT_PROPERTIES_OUT_V2_LOOPBACK_MODES_MASK_V2_HI_LEN 4
10272 * Read media-specific data from the PHY (e.g. SFP/SFP+ module ID information
10275 * get interpreted data. Return code: 0, ENOENT
10277 #define MC_CMD_GET_MODULE_DATA 0x1e8
10285 #define MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_OFST 0
10286 #define MC_CMD_GET_MODULE_DATA_IN_PORT_HANDLE_LEN 4
10293 /* 0 if the page does not support banked access, non-zero otherwise. Non-zero
10294 * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
10299 /* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
10300 * valid if OFFSET is in the range 80h - ffh.
10304 /* Offset in the range 00h - 7fh to access lower memory. Offset in the range
10305 * 80h - ffh to access upper memory
10310 #define MC_CMD_GET_MODULE_DATA_IN_LENGTH_LEN 4
10313 * 8-bit wide ADDRESSING field. This new field provides a correctly aligned
10314 * container for the 7-bit DEVADDR field from V1, now renamed MODULE_ADDR, to
10319 #define MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_OFST 0
10320 #define MC_CMD_GET_MODULE_DATA_IN_V2_PORT_HANDLE_LEN 4
10327 /* 0 if the page does not support banked access, non-zero otherwise. Non-zero
10328 * BANK is valid if OFFSET is in the range 80h - ffh, i.e. in the Upper Memory
10333 /* 0 if paged access is not supported, non-zero otherwise. Non-zero PAGE is
10334 * valid if OFFSET is in the range 80h - ffh.
10338 /* Offset in the range 00h - 7fh to access lower memory. Offset in the range
10339 * 80h - ffh to access upper memory
10344 #define MC_CMD_GET_MODULE_DATA_IN_V2_LENGTH_LEN 4
10346 #define MC_CMD_GET_MODULE_DATA_IN_V2_ADDRESSING_OFST 4
10348 #define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_OFST 4
10349 #define MC_CMD_GET_MODULE_DATA_IN_V2_MODULE_ADDR_LBN 0
10356 #define MC_CMD_GET_MODULE_DATA_OUT_LEN(num) (4+1*(num))
10357 #define MC_CMD_GET_MODULE_DATA_OUT_DATA_NUM(len) (((len)-4)/1)
10359 #define MC_CMD_GET_MODULE_DATA_OUT_DATALEN_OFST 0
10360 #define MC_CMD_GET_MODULE_DATA_OUT_DATALEN_LEN 4
10361 #define MC_CMD_GET_MODULE_DATA_OUT_DATA_OFST 4
10368 #define EVENT_MASK_LEN 4
10369 #define EVENT_MASK_TYPE_OFST 0
10370 #define EVENT_MASK_TYPE_LEN 4
10372 #define EVENT_MASK_PORT_LINKCHANGE 0x0
10374 #define EVENT_MASK_PORT_MODULECHANGE 0x1
10375 #define EVENT_MASK_TYPE_LBN 0
10382 #define MC_CMD_SET_NETPORT_EVENTS_MASK 0x1e9
10395 #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
10396 #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
10398 * bit is 1, disabled when 0.
10400 #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_OFST 4
10401 #define MC_CMD_SET_NETPORT_EVENTS_MASK_IN_EVENT_MASK_LEN 4
10407 #define MC_CMD_SET_NETPORT_EVENTS_MASK_OUT_LEN 0
10413 #define MC_CMD_GET_NETPORT_EVENTS_MASK 0x1ea
10421 #define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_LEN 4
10423 #define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_OFST 0
10424 #define MC_CMD_GET_NETPORT_EVENTS_MASK_IN_PORT_HANDLE_LEN 4
10427 #define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_LEN 4
10429 * is 1, disabled when 0.
10431 #define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_OFST 0
10432 #define MC_CMD_GET_NETPORT_EVENTS_MASK_OUT_EVENT_MASK_LEN 4
10441 #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS 0x1eb
10450 #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_IN_LEN 0
10453 #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_LEN 4
10455 * is 1, disabled when 0.
10457 #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_OFST 0
10458 #define MC_CMD_GET_SUPPORTED_NETPORT_EVENTS_OUT_EVENT_MASK_LEN 4
10471 * initialize the DMA buffer with zeros when DMA mode is used. Returns: 0 on
10472 * success, ETIME if the DMA buffer is not ready, ENOENT on non-existent port
10475 #define MC_CMD_GET_NETPORT_STATISTICS 0x1fa
10483 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_OFST 0
10484 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PORT_HANDLE_LEN 4
10486 #define MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_OFST 4
10487 #define MC_CMD_GET_NETPORT_STATISTICS_IN_CMD_LEN 4
10488 #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_OFST 4
10489 #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LBN 0
10491 #define MC_CMD_GET_NETPORT_STATISTICS_IN_CLEAR_OFST 4
10494 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_CHANGE_OFST 4
10497 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_ENABLE_OFST 4
10500 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_OFST 4
10501 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIODIC_NOEVENT_LBN 4
10503 #define MC_CMD_GET_NETPORT_STATISTICS_IN_PERIOD_MS_OFST 4
10514 #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_LO_LEN 4
10518 #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_ADDR_HI_LEN 4
10529 #define MC_CMD_GET_NETPORT_STATISTICS_IN_DMA_LEN_LEN 4
10532 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_LENMIN 0
10535 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_LEN(num) (0+8*(num))
10536 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_NUM(len) (((len)-0)/8)
10537 /* Statistics buffer. Zero-length if DMA mode is used. The statistics buffer is
10538 * an array of 8-byte counter values, containing the generation start marker,
10543 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_OFST 0
10545 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_OFST 0
10546 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LEN 4
10547 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_LO_LBN 0
10549 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_OFST 4
10550 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_HI_LEN 4
10553 #define MC_CMD_GET_NETPORT_STATISTICS_OUT_STATS_MINNUM 0
10558 #define EVB_PORT_ID_LEN 4
10559 #define EVB_PORT_ID_PORT_ID_OFST 0
10560 #define EVB_PORT_ID_PORT_ID_LEN 4
10562 #define EVB_PORT_ID_NULL 0x0
10564 #define EVB_PORT_ID_ASSIGNED 0x1000000
10565 /* enum: External network port 0 */
10566 #define EVB_PORT_ID_MAC0 0x2000000
10568 #define EVB_PORT_ID_MAC1 0x2000001
10570 #define EVB_PORT_ID_MAC2 0x2000002
10572 #define EVB_PORT_ID_MAC3 0x2000003
10573 #define EVB_PORT_ID_PORT_ID_LBN 0
10578 #define NVRAM_PARTITION_TYPE_ID_OFST 0
10581 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE 0x100
10584 #define NVRAM_PARTITION_TYPE_NMC_FIRMWARE 0x100
10586 #define NVRAM_PARTITION_TYPE_MC_FIRMWARE_BACKUP 0x200
10588 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM 0x300
10590 #define NVRAM_PARTITION_TYPE_STATIC_CONFIG 0x400
10594 #define NVRAM_PARTITION_TYPE_FACTORY_CONFIG 0x400
10596 #define NVRAM_PARTITION_TYPE_DYNAMIC_CONFIG 0x500
10600 #define NVRAM_PARTITION_TYPE_USER_CONFIG 0x500
10601 /* enum: Expansion ROM configuration data for port 0 */
10602 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT0 0x600
10604 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG 0x600
10606 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT1 0x601
10608 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT2 0x602
10610 #define NVRAM_PARTITION_TYPE_EXPROM_CONFIG_PORT3 0x603
10611 /* enum: Non-volatile log output partition */
10612 #define NVRAM_PARTITION_TYPE_LOG 0x700
10613 /* enum: Non-volatile log output partition for NMC firmware (this is
10616 #define NVRAM_PARTITION_TYPE_NMC_LOG 0x700
10617 /* enum: Non-volatile log output of second core on dual-core device */
10618 #define NVRAM_PARTITION_TYPE_LOG_SLAVE 0x701
10620 #define NVRAM_PARTITION_TYPE_RAM_LOG 0x702
10622 #define NVRAM_PARTITION_TYPE_DUMP 0x800
10624 #define NVRAM_PARTITION_TYPE_NMC_CRASH_LOG 0x801
10626 #define NVRAM_PARTITION_TYPE_LICENSE 0x900
10628 #define NVRAM_PARTITION_TYPE_PHY_MIN 0xa00
10630 #define NVRAM_PARTITION_TYPE_PHY_MAX 0xaff
10632 #define NVRAM_PARTITION_TYPE_FPGA 0xb00
10634 #define NVRAM_PARTITION_TYPE_FPGA_BACKUP 0xb01
10636 #define NVRAM_PARTITION_TYPE_FC_FIRMWARE 0xb02
10638 #define NVRAM_PARTITION_TYPE_FC_LICENSE 0xb03
10639 /* enum: Non-volatile log output partition for FC */
10640 #define NVRAM_PARTITION_TYPE_FC_LOG 0xb04
10642 #define NVRAM_PARTITION_TYPE_FPGA_STAGE1 0xb05
10644 #define NVRAM_PARTITION_TYPE_FPGA_STAGE2 0xb06
10645 /* enum: FPGA User XCLBIN / Programmable Region 0 bitstream */
10646 #define NVRAM_PARTITION_TYPE_FPGA_REGION0 0xb07
10648 #define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_USER 0xb07
10652 #define NVRAM_PARTITION_TYPE_FPGA_JUMP 0xb08
10654 #define NVRAM_PARTITION_TYPE_FPGA_XCLBIN_VALIDATE 0xb09
10656 #define NVRAM_PARTITION_TYPE_FPGA_XOCL_CONFIG 0xb0a
10658 #define NVRAM_PARTITION_TYPE_MUM_FIRMWARE 0xc00
10662 #define NVRAM_PARTITION_TYPE_SUC_FIRMWARE 0xc00
10663 /* enum: MUM Non-volatile log output partition. */
10664 #define NVRAM_PARTITION_TYPE_MUM_LOG 0xc01
10665 /* enum: SUC Non-volatile log output partition (this is intentionally an alias
10668 #define NVRAM_PARTITION_TYPE_SUC_LOG 0xc01
10670 #define NVRAM_PARTITION_TYPE_MUM_APPTABLE 0xc02
10672 #define NVRAM_PARTITION_TYPE_MUM_BOOT_ROM 0xc03
10674 #define NVRAM_PARTITION_TYPE_MUM_PROD_ROM 0xc04
10676 #define NVRAM_PARTITION_TYPE_MUM_USER_ROM 0xc05
10678 #define NVRAM_PARTITION_TYPE_MUM_FUSELOCK 0xc06
10680 #define NVRAM_PARTITION_TYPE_EXPANSION_UEFI 0xd00
10682 #define NVRAM_PARTITION_TYPE_PXE_LOG 0x1000
10683 /* enum: Non-volatile log output partition for Expansion ROM (this is
10686 #define NVRAM_PARTITION_TYPE_EXPROM_LOG 0x1000
10688 #define NVRAM_PARTITION_TYPE_XIP_SCRATCH 0x1100
10690 #define NVRAM_PARTITION_TYPE_SPARE_2 0x1200
10694 #define NVRAM_PARTITION_TYPE_MANUFACTURING 0x1300
10698 #define NVRAM_PARTITION_TYPE_DEPLOYMENT_CONFIG 0x1300
10699 /* enum: Spare partition 4 */
10700 #define NVRAM_PARTITION_TYPE_SPARE_4 0x1400
10702 #define NVRAM_PARTITION_TYPE_SPARE_5 0x1500
10706 #define NVRAM_PARTITION_TYPE_STATUS 0x1600
10708 #define NVRAM_PARTITION_TYPE_SPARE_13 0x1700
10710 #define NVRAM_PARTITION_TYPE_SPARE_14 0x1800
10712 #define NVRAM_PARTITION_TYPE_SPARE_15 0x1900
10714 #define NVRAM_PARTITION_TYPE_SPARE_16 0x1a00
10716 #define NVRAM_PARTITION_TYPE_DYNCONFIG_DEFAULTS 0x1b00
10718 #define NVRAM_PARTITION_TYPE_ROMCONFIG_DEFAULTS 0x1c00
10720 * platforms. See SF-119124-PS. The STATIC_CONFIG partition may contain a
10723 #define NVRAM_PARTITION_TYPE_FRU_INFORMATION 0x1d00
10725 #define NVRAM_PARTITION_TYPE_BUNDLE 0x1e00
10729 #define NVRAM_PARTITION_TYPE_BUNDLE_METADATA 0x1e01
10730 /* enum: Bundle update non-volatile log output partition */
10731 #define NVRAM_PARTITION_TYPE_BUNDLE_LOG 0x1e02
10733 #define NVRAM_PARTITION_TYPE_EXPANSION_ROM_INTERNAL 0x1e03
10735 #define NVRAM_PARTITION_TYPE_BUNDLE_SIGNATURE 0x1e04
10737 #define NVRAM_PARTITION_TYPE_SUC_TEST 0x1f00
10739 #define NVRAM_PARTITION_TYPE_SUC_FPGA_PRIMARY 0x1f01
10741 #define NVRAM_PARTITION_TYPE_SUC_FPGA_SECONDARY 0x1f02
10742 /* enum: System microcontroller access to primary System-on-Chip flash */
10743 #define NVRAM_PARTITION_TYPE_SUC_SOC_PRIMARY 0x1f03
10744 /* enum: System microcontroller access to secondary System-on-Chip flash (if
10747 #define NVRAM_PARTITION_TYPE_SUC_SOC_SECONDARY 0x1f04
10752 #define NVRAM_PARTITION_TYPE_SUC_FAILURE_LOG 0x1f05
10753 /* enum: System-on-Chip configuration information (see XN-200467-PS). */
10754 #define NVRAM_PARTITION_TYPE_SUC_SOC_CONFIG 0x1f07
10755 /* enum: System-on-Chip update information. */
10756 #define NVRAM_PARTITION_TYPE_SOC_UPDATE 0x2003
10757 /* enum: Virtual partition. Write-only. Writes will actually be sent to an
10762 #define NVRAM_PARTITION_TYPE_AUTO 0x2100
10763 /* enum: MC/NMC (first stage) bootloader firmware. (For X4, see XN-202072-PS
10764 * and XN-202084-SW section 3.1).
10766 #define NVRAM_PARTITION_TYPE_BOOTLOADER 0x2200
10768 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MIN 0xff00
10770 #define NVRAM_PARTITION_TYPE_RESERVED_VALUES_MAX 0xfffd
10772 #define NVRAM_PARTITION_TYPE_RECOVERY_MAP 0xfffe
10773 /* enum: Recovery Flash Partition Table, see SF-122606-TC. (this is
10776 #define NVRAM_PARTITION_TYPE_RECOVERY_FPT 0xfffe
10778 #define NVRAM_PARTITION_TYPE_PARTITION_MAP 0xffff
10779 /* enum: Flash Partition Table, see SF-122606-TC. (this is intentionally an
10782 #define NVRAM_PARTITION_TYPE_FPT 0xffff
10783 #define NVRAM_PARTITION_TYPE_ID_LBN 0
10787 #define LICENSED_APP_ID_LEN 4
10788 #define LICENSED_APP_ID_ID_OFST 0
10789 #define LICENSED_APP_ID_ID_LEN 4
10791 #define LICENSED_APP_ID_ONLOAD 0x1
10793 #define LICENSED_APP_ID_PTP 0x2
10795 #define LICENSED_APP_ID_SOLARCAPTURE_PRO 0x4
10797 #define LICENSED_APP_ID_SOLARSECURE 0x8
10799 #define LICENSED_APP_ID_PERF_MONITOR 0x10
10801 #define LICENSED_APP_ID_SOLARCAPTURE_LIVE 0x20
10803 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM 0x40
10805 #define LICENSED_APP_ID_NETWORK_ACCESS_CONTROL 0x80
10807 #define LICENSED_APP_ID_TCP_DIRECT 0x100
10809 #define LICENSED_APP_ID_LOW_LATENCY 0x200
10811 #define LICENSED_APP_ID_SOLARCAPTURE_TAP 0x400
10813 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_40G 0x800
10815 #define LICENSED_APP_ID_CAPTURE_SOLARSYSTEM_1G 0x1000
10817 #define LICENSED_APP_ID_SCALEOUT_ONLOAD 0x2000
10819 #define LICENSED_APP_ID_DSHBRD 0x4000
10821 #define LICENSED_APP_ID_SCATRD 0x8000
10822 #define LICENSED_APP_ID_ID_LBN 0
10828 #define LICENSED_V3_FEATURES_MASK_OFST 0
10830 #define LICENSED_V3_FEATURES_MASK_LO_OFST 0
10831 #define LICENSED_V3_FEATURES_MASK_LO_LEN 4
10832 #define LICENSED_V3_FEATURES_MASK_LO_LBN 0
10834 #define LICENSED_V3_FEATURES_MASK_HI_OFST 4
10835 #define LICENSED_V3_FEATURES_MASK_HI_LEN 4
10838 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_OFST 0
10839 #define LICENSED_V3_FEATURES_RX_CUT_THROUGH_LBN 0
10841 #define LICENSED_V3_FEATURES_PIO_OFST 0
10844 #define LICENSED_V3_FEATURES_EVQ_TIMER_OFST 0
10847 #define LICENSED_V3_FEATURES_CLOCK_OFST 0
10850 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_OFST 0
10851 #define LICENSED_V3_FEATURES_RX_TIMESTAMPS_LBN 4
10853 #define LICENSED_V3_FEATURES_TX_TIMESTAMPS_OFST 0
10856 #define LICENSED_V3_FEATURES_RX_SNIFF_OFST 0
10859 #define LICENSED_V3_FEATURES_TX_SNIFF_OFST 0
10862 #define LICENSED_V3_FEATURES_PROXY_FILTER_OPS_OFST 0
10865 #define LICENSED_V3_FEATURES_EVENT_CUT_THROUGH_OFST 0
10868 #define LICENSED_V3_FEATURES_MASK_LBN 0
10874 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_OFST 0
10876 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_LO_LBN 0
10883 #define TX_TIMESTAMP_EVENT_TX_EV_COMPLETION 0x0
10887 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_COMPLETION 0x11
10891 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_LO 0x12
10895 #define TX_TIMESTAMP_EVENT_TX_EV_CTPIO_TS_HI 0x13
10897 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_LO 0x51
10899 #define TX_TIMESTAMP_EVENT_TX_EV_TSTAMP_HI 0x52
10903 #define TX_TIMESTAMP_EVENT_TSTAMP_DATA_HI_OFST 4
10910 /* The RSS mode for a particular packet type is a value from 0 - 15 which can
10911 * be considered as 4 bits selecting which fields are included in the hash. (A
10912 * value 0 effectively disables RSS spreading for the packet type.) The YAML
10914 * but only 4 bits are relevant.
10916 #define RSS_MODE_HASH_SELECTOR_OFST 0
10918 #define RSS_MODE_HASH_SRC_ADDR_OFST 0
10919 #define RSS_MODE_HASH_SRC_ADDR_LBN 0
10921 #define RSS_MODE_HASH_DST_ADDR_OFST 0
10924 #define RSS_MODE_HASH_SRC_PORT_OFST 0
10927 #define RSS_MODE_HASH_DST_PORT_OFST 0
10930 #define RSS_MODE_HASH_SELECTOR_LBN 0
10937 * end with an address for each 4k of host memory required to back the EVQ.
10939 #define MC_CMD_INIT_EVQ 0x80
10949 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
10951 #define MC_CMD_INIT_EVQ_IN_SIZE_OFST 0
10952 #define MC_CMD_INIT_EVQ_IN_SIZE_LEN 4
10954 * local queue index. The calling client must be the currently-assigned user of
10957 #define MC_CMD_INIT_EVQ_IN_INSTANCE_OFST 4
10958 #define MC_CMD_INIT_EVQ_IN_INSTANCE_LEN 4
10962 #define MC_CMD_INIT_EVQ_IN_TMR_LOAD_LEN 4
10963 /* The reload value is ignored in one-shot modes */
10965 #define MC_CMD_INIT_EVQ_IN_TMR_RELOAD_LEN 4
10968 #define MC_CMD_INIT_EVQ_IN_FLAGS_LEN 4
10970 #define MC_CMD_INIT_EVQ_IN_FLAG_INTERRUPTING_LBN 0
10982 #define MC_CMD_INIT_EVQ_IN_FLAG_RX_MERGE_LBN 4
10991 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_LEN 4
10993 #define MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS 0x0
10995 #define MC_CMD_INIT_EVQ_IN_TMR_IMMED_START 0x1
10997 #define MC_CMD_INIT_EVQ_IN_TMR_TRIG_START 0x2
10998 /* enum: Hold-off */
10999 #define MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF 0x3
11002 #define MC_CMD_INIT_EVQ_IN_TARGET_EVQ_LEN 4
11008 #define MC_CMD_INIT_EVQ_IN_IRQ_NUM_LEN 4
11011 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_LEN 4
11013 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS 0x0
11015 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RX 0x1
11017 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_TX 0x2
11019 #define MC_CMD_INIT_EVQ_IN_COUNT_MODE_RXTX 0x3
11022 #define MC_CMD_INIT_EVQ_IN_COUNT_THRSHLD_LEN 4
11023 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11027 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_LO_LEN 4
11031 #define MC_CMD_INIT_EVQ_IN_DMA_ADDR_HI_LEN 4
11039 #define MC_CMD_INIT_EVQ_OUT_LEN 4
11041 #define MC_CMD_INIT_EVQ_OUT_IRQ_OFST 0
11042 #define MC_CMD_INIT_EVQ_OUT_IRQ_LEN 4
11049 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_NUM(len) (((len)-36)/8)
11051 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_OFST 0
11052 #define MC_CMD_INIT_EVQ_V2_IN_SIZE_LEN 4
11054 * local queue index. The calling client must be the currently-assigned user of
11057 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_OFST 4
11058 #define MC_CMD_INIT_EVQ_V2_IN_INSTANCE_LEN 4
11062 #define MC_CMD_INIT_EVQ_V2_IN_TMR_LOAD_LEN 4
11063 /* The reload value is ignored in one-shot modes */
11065 #define MC_CMD_INIT_EVQ_V2_IN_TMR_RELOAD_LEN 4
11068 #define MC_CMD_INIT_EVQ_V2_IN_FLAGS_LEN 4
11070 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_INTERRUPTING_LBN 0
11082 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_RX_MERGE_LBN 4
11092 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_WIDTH 4
11094 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_MANUAL 0x0
11096 * over-ridden by firmware based on licenses and firmware variant in order to
11100 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_LOW_LATENCY 0x1
11102 * over-ridden by firmware based on licenses and firmware variant in order to
11106 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_THROUGHPUT 0x2
11107 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
11111 #define MC_CMD_INIT_EVQ_V2_IN_FLAG_TYPE_AUTO 0x3
11116 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_LEN 4
11118 #define MC_CMD_INIT_EVQ_V2_IN_TMR_MODE_DIS 0x0
11120 #define MC_CMD_INIT_EVQ_V2_IN_TMR_IMMED_START 0x1
11122 #define MC_CMD_INIT_EVQ_V2_IN_TMR_TRIG_START 0x2
11123 /* enum: Hold-off */
11124 #define MC_CMD_INIT_EVQ_V2_IN_TMR_INT_HLDOFF 0x3
11127 #define MC_CMD_INIT_EVQ_V2_IN_TARGET_EVQ_LEN 4
11133 #define MC_CMD_INIT_EVQ_V2_IN_IRQ_NUM_LEN 4
11136 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_LEN 4
11138 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_DIS 0x0
11140 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RX 0x1
11142 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_TX 0x2
11144 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_MODE_RXTX 0x3
11147 #define MC_CMD_INIT_EVQ_V2_IN_COUNT_THRSHLD_LEN 4
11148 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11152 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_LO_LEN 4
11156 #define MC_CMD_INIT_EVQ_V2_IN_DMA_ADDR_HI_LEN 4
11166 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_OFST 0
11167 #define MC_CMD_INIT_EVQ_V2_OUT_IRQ_LEN 4
11169 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_OFST 4
11170 #define MC_CMD_INIT_EVQ_V2_OUT_FLAGS_LEN 4
11171 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_OFST 4
11172 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_CUT_THRU_LBN 0
11174 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RX_MERGE_OFST 4
11177 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_TX_MERGE_OFST 4
11180 #define MC_CMD_INIT_EVQ_V2_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
11184 /* MC_CMD_INIT_EVQ_V3_IN msgrequest: Extended request to specify per-queue
11189 #define MC_CMD_INIT_EVQ_V3_IN_SIZE_OFST 0
11190 #define MC_CMD_INIT_EVQ_V3_IN_SIZE_LEN 4
11192 * local queue index. The calling client must be the currently-assigned user of
11195 #define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_OFST 4
11196 #define MC_CMD_INIT_EVQ_V3_IN_INSTANCE_LEN 4
11200 #define MC_CMD_INIT_EVQ_V3_IN_TMR_LOAD_LEN 4
11201 /* The reload value is ignored in one-shot modes */
11203 #define MC_CMD_INIT_EVQ_V3_IN_TMR_RELOAD_LEN 4
11206 #define MC_CMD_INIT_EVQ_V3_IN_FLAGS_LEN 4
11208 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_INTERRUPTING_LBN 0
11220 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_RX_MERGE_LBN 4
11230 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_WIDTH 4
11232 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_MANUAL 0x0
11234 * over-ridden by firmware based on licenses and firmware variant in order to
11238 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_LOW_LATENCY 0x1
11240 * over-ridden by firmware based on licenses and firmware variant in order to
11244 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_THROUGHPUT 0x2
11245 /* enum: MEDFORD only. Certain initialisation flags may be over-ridden by
11249 #define MC_CMD_INIT_EVQ_V3_IN_FLAG_TYPE_AUTO 0x3
11254 #define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_LEN 4
11256 #define MC_CMD_INIT_EVQ_V3_IN_TMR_MODE_DIS 0x0
11258 #define MC_CMD_INIT_EVQ_V3_IN_TMR_IMMED_START 0x1
11260 #define MC_CMD_INIT_EVQ_V3_IN_TMR_TRIG_START 0x2
11261 /* enum: Hold-off */
11262 #define MC_CMD_INIT_EVQ_V3_IN_TMR_INT_HLDOFF 0x3
11265 #define MC_CMD_INIT_EVQ_V3_IN_TARGET_EVQ_LEN 4
11271 #define MC_CMD_INIT_EVQ_V3_IN_IRQ_NUM_LEN 4
11274 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_LEN 4
11276 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_DIS 0x0
11278 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RX 0x1
11280 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_TX 0x2
11282 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_MODE_RXTX 0x3
11285 #define MC_CMD_INIT_EVQ_V3_IN_COUNT_THRSHLD_LEN 4
11286 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11290 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_LO_LEN 4
11294 #define MC_CMD_INIT_EVQ_V3_IN_DMA_ADDR_HI_LEN 4
11301 * and granularity are device specific. Specify 0 to use the firmware's default
11302 * value. This field is ignored and per-queue merging is disabled if
11306 #define MC_CMD_INIT_EVQ_V3_IN_RX_MERGE_TIMEOUT_NS_LEN 4
11308 * and granularity are device specific. Specify 0 to use the firmware's default
11309 * value. This field is ignored and per-queue merging is disabled if
11313 #define MC_CMD_INIT_EVQ_V3_IN_TX_MERGE_TIMEOUT_NS_LEN 4
11318 #define MC_CMD_INIT_EVQ_V3_OUT_IRQ_OFST 0
11319 #define MC_CMD_INIT_EVQ_V3_OUT_IRQ_LEN 4
11321 #define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_OFST 4
11322 #define MC_CMD_INIT_EVQ_V3_OUT_FLAGS_LEN 4
11323 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_OFST 4
11324 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_CUT_THRU_LBN 0
11326 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RX_MERGE_OFST 4
11329 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_TX_MERGE_OFST 4
11332 #define MC_CMD_INIT_EVQ_V3_OUT_FLAG_RXQ_FORCE_EV_MERGING_OFST 4
11340 * arguments end with an address for each 4k of host memory required to back
11343 #define MC_CMD_INIT_RXQ 0x81
11355 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
11357 #define MC_CMD_INIT_RXQ_IN_SIZE_OFST 0
11358 #define MC_CMD_INIT_RXQ_IN_SIZE_LEN 4
11361 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_OFST 4
11362 #define MC_CMD_INIT_RXQ_IN_TARGET_EVQ_LEN 4
11365 #define MC_CMD_INIT_RXQ_IN_LABEL_LEN 4
11367 * local queue index. The calling client must be the currently-assigned user of
11371 #define MC_CMD_INIT_RXQ_IN_INSTANCE_LEN 4
11374 #define MC_CMD_INIT_RXQ_IN_FLAGS_LEN 4
11376 #define MC_CMD_INIT_RXQ_IN_FLAG_BUFF_MODE_LBN 0
11386 #define MC_CMD_INIT_RXQ_IN_CRC_MODE_WIDTH 4
11401 #define MC_CMD_INIT_RXQ_IN_OWNER_ID_LEN 4
11402 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11404 #define MC_CMD_INIT_RXQ_IN_PORT_ID_LEN 4
11405 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11409 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_LO_LEN 4
11413 #define MC_CMD_INIT_RXQ_IN_DMA_ADDR_HI_LEN 4
11425 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_OFST 0
11426 #define MC_CMD_INIT_RXQ_EXT_IN_SIZE_LEN 4
11430 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_OFST 4
11431 #define MC_CMD_INIT_RXQ_EXT_IN_TARGET_EVQ_LEN 4
11437 #define MC_CMD_INIT_RXQ_EXT_IN_LABEL_LEN 4
11439 * local queue index. The calling client must be the currently-assigned user of
11443 #define MC_CMD_INIT_RXQ_EXT_IN_INSTANCE_LEN 4
11446 #define MC_CMD_INIT_RXQ_EXT_IN_FLAGS_LEN 4
11448 #define MC_CMD_INIT_RXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
11458 #define MC_CMD_INIT_RXQ_EXT_IN_CRC_MODE_WIDTH 4
11470 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_MODE_WIDTH 4
11472 #define MC_CMD_INIT_RXQ_EXT_IN_SINGLE_PACKET 0x0
11474 #define MC_CMD_INIT_RXQ_EXT_IN_PACKED_STREAM 0x1
11477 * multiple fixed-size packet buffers within each bucket. For a full
11478 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11481 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11483 #define MC_CMD_INIT_RXQ_EXT_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11490 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_1M 0x0 /* enum */
11491 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_512K 0x1 /* enum */
11492 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_256K 0x2 /* enum */
11493 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_128K 0x3 /* enum */
11494 #define MC_CMD_INIT_RXQ_EXT_IN_PS_BUFF_64K 0x4 /* enum */
11509 #define MC_CMD_INIT_RXQ_EXT_IN_OWNER_ID_LEN 4
11510 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11512 #define MC_CMD_INIT_RXQ_EXT_IN_PORT_ID_LEN 4
11513 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11517 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_LO_LEN 4
11521 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_HI_LEN 4
11524 #define MC_CMD_INIT_RXQ_EXT_IN_DMA_ADDR_MINNUM 0
11529 #define MC_CMD_INIT_RXQ_EXT_IN_SNAPSHOT_LENGTH_LEN 4
11534 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_OFST 0
11535 #define MC_CMD_INIT_RXQ_V3_IN_SIZE_LEN 4
11539 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_OFST 4
11540 #define MC_CMD_INIT_RXQ_V3_IN_TARGET_EVQ_LEN 4
11546 #define MC_CMD_INIT_RXQ_V3_IN_LABEL_LEN 4
11548 * local queue index. The calling client must be the currently-assigned user of
11552 #define MC_CMD_INIT_RXQ_V3_IN_INSTANCE_LEN 4
11555 #define MC_CMD_INIT_RXQ_V3_IN_FLAGS_LEN 4
11557 #define MC_CMD_INIT_RXQ_V3_IN_FLAG_BUFF_MODE_LBN 0
11567 #define MC_CMD_INIT_RXQ_V3_IN_CRC_MODE_WIDTH 4
11579 #define MC_CMD_INIT_RXQ_V3_IN_DMA_MODE_WIDTH 4
11581 #define MC_CMD_INIT_RXQ_V3_IN_SINGLE_PACKET 0x0
11583 #define MC_CMD_INIT_RXQ_V3_IN_PACKED_STREAM 0x1
11586 * multiple fixed-size packet buffers within each bucket. For a full
11587 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11590 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11592 #define MC_CMD_INIT_RXQ_V3_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11599 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_1M 0x0 /* enum */
11600 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_512K 0x1 /* enum */
11601 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_256K 0x2 /* enum */
11602 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_128K 0x3 /* enum */
11603 #define MC_CMD_INIT_RXQ_V3_IN_PS_BUFF_64K 0x4 /* enum */
11618 #define MC_CMD_INIT_RXQ_V3_IN_OWNER_ID_LEN 4
11619 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11621 #define MC_CMD_INIT_RXQ_V3_IN_PORT_ID_LEN 4
11622 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11626 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_LO_LEN 4
11630 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_HI_LEN 4
11633 #define MC_CMD_INIT_RXQ_V3_IN_DMA_ADDR_MINNUM 0
11638 #define MC_CMD_INIT_RXQ_V3_IN_SNAPSHOT_LENGTH_LEN 4
11644 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11651 #define MC_CMD_INIT_RXQ_V3_IN_ES_MAX_DMA_LEN_LEN 4
11657 #define MC_CMD_INIT_RXQ_V3_IN_ES_PACKET_STRIDE_LEN 4
11660 * are still no descriptors then the packet will be dropped. A timeout of 0
11665 #define MC_CMD_INIT_RXQ_V3_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11672 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_OFST 0
11673 #define MC_CMD_INIT_RXQ_V4_IN_SIZE_LEN 4
11677 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_OFST 4
11678 #define MC_CMD_INIT_RXQ_V4_IN_TARGET_EVQ_LEN 4
11684 #define MC_CMD_INIT_RXQ_V4_IN_LABEL_LEN 4
11686 * local queue index. The calling client must be the currently-assigned user of
11690 #define MC_CMD_INIT_RXQ_V4_IN_INSTANCE_LEN 4
11693 #define MC_CMD_INIT_RXQ_V4_IN_FLAGS_LEN 4
11695 #define MC_CMD_INIT_RXQ_V4_IN_FLAG_BUFF_MODE_LBN 0
11705 #define MC_CMD_INIT_RXQ_V4_IN_CRC_MODE_WIDTH 4
11717 #define MC_CMD_INIT_RXQ_V4_IN_DMA_MODE_WIDTH 4
11719 #define MC_CMD_INIT_RXQ_V4_IN_SINGLE_PACKET 0x0
11721 #define MC_CMD_INIT_RXQ_V4_IN_PACKED_STREAM 0x1
11724 * multiple fixed-size packet buffers within each bucket. For a full
11725 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11728 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11730 #define MC_CMD_INIT_RXQ_V4_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11737 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_1M 0x0 /* enum */
11738 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_512K 0x1 /* enum */
11739 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_256K 0x2 /* enum */
11740 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_128K 0x3 /* enum */
11741 #define MC_CMD_INIT_RXQ_V4_IN_PS_BUFF_64K 0x4 /* enum */
11756 #define MC_CMD_INIT_RXQ_V4_IN_OWNER_ID_LEN 4
11757 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11759 #define MC_CMD_INIT_RXQ_V4_IN_PORT_ID_LEN 4
11760 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11764 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_LO_LEN 4
11768 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_HI_LEN 4
11771 #define MC_CMD_INIT_RXQ_V4_IN_DMA_ADDR_MINNUM 0
11776 #define MC_CMD_INIT_RXQ_V4_IN_SNAPSHOT_LENGTH_LEN 4
11782 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11789 #define MC_CMD_INIT_RXQ_V4_IN_ES_MAX_DMA_LEN_LEN 4
11795 #define MC_CMD_INIT_RXQ_V4_IN_ES_PACKET_STRIDE_LEN 4
11798 * are still no descriptors then the packet will be dropped. A timeout of 0
11803 #define MC_CMD_INIT_RXQ_V4_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11806 #define MC_CMD_INIT_RXQ_V4_IN_V4_DATA_LEN 4
11808 * to zero if using this message on non-QDMA based platforms. Currently in
11810 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11816 #define MC_CMD_INIT_RXQ_V4_IN_BUFFER_SIZE_BYTES_LEN 4
11823 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_OFST 0
11824 #define MC_CMD_INIT_RXQ_V5_IN_SIZE_LEN 4
11828 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_OFST 4
11829 #define MC_CMD_INIT_RXQ_V5_IN_TARGET_EVQ_LEN 4
11835 #define MC_CMD_INIT_RXQ_V5_IN_LABEL_LEN 4
11837 * local queue index. The calling client must be the currently-assigned user of
11841 #define MC_CMD_INIT_RXQ_V5_IN_INSTANCE_LEN 4
11844 #define MC_CMD_INIT_RXQ_V5_IN_FLAGS_LEN 4
11846 #define MC_CMD_INIT_RXQ_V5_IN_FLAG_BUFF_MODE_LBN 0
11856 #define MC_CMD_INIT_RXQ_V5_IN_CRC_MODE_WIDTH 4
11868 #define MC_CMD_INIT_RXQ_V5_IN_DMA_MODE_WIDTH 4
11870 #define MC_CMD_INIT_RXQ_V5_IN_SINGLE_PACKET 0x0
11872 #define MC_CMD_INIT_RXQ_V5_IN_PACKED_STREAM 0x1
11875 * multiple fixed-size packet buffers within each bucket. For a full
11876 * description see SF-119419-TC. This mode is only supported by "dpdk" datapath
11879 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_SUPER_BUFFER 0x2
11881 #define MC_CMD_INIT_RXQ_V5_IN_EQUAL_STRIDE_PACKED_STREAM 0x2
11888 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_1M 0x0 /* enum */
11889 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_512K 0x1 /* enum */
11890 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_256K 0x2 /* enum */
11891 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_128K 0x3 /* enum */
11892 #define MC_CMD_INIT_RXQ_V5_IN_PS_BUFF_64K 0x4 /* enum */
11907 #define MC_CMD_INIT_RXQ_V5_IN_OWNER_ID_LEN 4
11908 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
11910 #define MC_CMD_INIT_RXQ_V5_IN_PORT_ID_LEN 4
11911 /* 64-bit address of 4k of 4k-aligned host memory buffer */
11915 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_LO_LEN 4
11919 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_HI_LEN 4
11922 #define MC_CMD_INIT_RXQ_V5_IN_DMA_ADDR_MINNUM 0
11927 #define MC_CMD_INIT_RXQ_V5_IN_SNAPSHOT_LENGTH_LEN 4
11933 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_BUFFERS_PER_BUCKET_LEN 4
11940 #define MC_CMD_INIT_RXQ_V5_IN_ES_MAX_DMA_LEN_LEN 4
11946 #define MC_CMD_INIT_RXQ_V5_IN_ES_PACKET_STRIDE_LEN 4
11949 * are still no descriptors then the packet will be dropped. A timeout of 0
11954 #define MC_CMD_INIT_RXQ_V5_IN_ES_HEAD_OF_LINE_BLOCK_TIMEOUT_LEN 4
11957 #define MC_CMD_INIT_RXQ_V5_IN_V4_DATA_LEN 4
11959 * to zero if using this message on non-QDMA based platforms. Currently in
11961 * active queues. A 2KB and 4KB buffer is guaranteed to be available, but a
11967 #define MC_CMD_INIT_RXQ_V5_IN_BUFFER_SIZE_BYTES_LEN 4
11974 #define MC_CMD_INIT_RXQ_V5_IN_RX_PREFIX_ID_LEN 4
11977 #define MC_CMD_INIT_RXQ_OUT_LEN 0
11980 #define MC_CMD_INIT_RXQ_EXT_OUT_LEN 0
11983 #define MC_CMD_INIT_RXQ_V3_OUT_LEN 0
11986 #define MC_CMD_INIT_RXQ_V4_OUT_LEN 0
11989 #define MC_CMD_INIT_RXQ_V5_OUT_LEN 0
11995 #define MC_CMD_INIT_TXQ 0x82
12007 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_NUM(len) (((len)-28)/8)
12009 #define MC_CMD_INIT_TXQ_IN_SIZE_OFST 0
12010 #define MC_CMD_INIT_TXQ_IN_SIZE_LEN 4
12014 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_OFST 4
12015 #define MC_CMD_INIT_TXQ_IN_TARGET_EVQ_LEN 4
12018 #define MC_CMD_INIT_TXQ_IN_LABEL_LEN 4
12020 * local queue index. The calling client must be the currently-assigned user of
12024 #define MC_CMD_INIT_TXQ_IN_INSTANCE_LEN 4
12027 #define MC_CMD_INIT_TXQ_IN_FLAGS_LEN 4
12029 #define MC_CMD_INIT_TXQ_IN_FLAG_BUFF_MODE_LBN 0
12041 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_LBN 4
12042 #define MC_CMD_INIT_TXQ_IN_CRC_MODE_WIDTH 4
12057 #define MC_CMD_INIT_TXQ_IN_OWNER_ID_LEN 4
12058 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
12060 #define MC_CMD_INIT_TXQ_IN_PORT_ID_LEN 4
12061 /* 64-bit address of 4k of 4k-aligned host memory buffer */
12065 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_LO_LEN 4
12069 #define MC_CMD_INIT_TXQ_IN_DMA_ADDR_HI_LEN 4
12081 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_OFST 0
12082 #define MC_CMD_INIT_TXQ_EXT_IN_SIZE_LEN 4
12086 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_OFST 4
12087 #define MC_CMD_INIT_TXQ_EXT_IN_TARGET_EVQ_LEN 4
12090 #define MC_CMD_INIT_TXQ_EXT_IN_LABEL_LEN 4
12092 * local queue index. The calling client must be the currently-assigned user of
12096 #define MC_CMD_INIT_TXQ_EXT_IN_INSTANCE_LEN 4
12099 #define MC_CMD_INIT_TXQ_EXT_IN_FLAGS_LEN 4
12101 #define MC_CMD_INIT_TXQ_EXT_IN_FLAG_BUFF_MODE_LBN 0
12113 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_LBN 4
12114 #define MC_CMD_INIT_TXQ_EXT_IN_CRC_MODE_WIDTH 4
12147 #define MC_CMD_INIT_TXQ_EXT_IN_OWNER_ID_LEN 4
12148 /* The port ID associated with the v-adaptor which should contain this DMAQ. */
12150 #define MC_CMD_INIT_TXQ_EXT_IN_PORT_ID_LEN 4
12151 /* 64-bit address of 4k of 4k-aligned host memory buffer */
12155 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_LO_LEN 4
12159 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_HI_LEN 4
12162 #define MC_CMD_INIT_TXQ_EXT_IN_DMA_ADDR_MINNUM 0
12167 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_FLAGS_LEN 4
12169 #define MC_CMD_INIT_TXQ_EXT_IN_QBB_ENABLE_LBN 0
12176 #define MC_CMD_INIT_TXQ_OUT_LEN 0
12186 #define MC_CMD_FINI_EVQ 0x83
12192 #define MC_CMD_FINI_EVQ_IN_LEN 4
12196 #define MC_CMD_FINI_EVQ_IN_INSTANCE_OFST 0
12197 #define MC_CMD_FINI_EVQ_IN_INSTANCE_LEN 4
12200 #define MC_CMD_FINI_EVQ_OUT_LEN 0
12207 #define MC_CMD_FINI_RXQ 0x84
12213 #define MC_CMD_FINI_RXQ_IN_LEN 4
12215 #define MC_CMD_FINI_RXQ_IN_INSTANCE_OFST 0
12216 #define MC_CMD_FINI_RXQ_IN_INSTANCE_LEN 4
12219 #define MC_CMD_FINI_RXQ_OUT_LEN 0
12226 #define MC_CMD_FINI_TXQ 0x85
12232 #define MC_CMD_FINI_TXQ_IN_LEN 4
12234 #define MC_CMD_FINI_TXQ_IN_INSTANCE_OFST 0
12235 #define MC_CMD_FINI_TXQ_IN_INSTANCE_LEN 4
12238 #define MC_CMD_FINI_TXQ_OUT_LEN 0
12245 #define MC_CMD_DRIVER_EVENT 0x86
12253 #define MC_CMD_DRIVER_EVENT_IN_EVQ_OFST 0
12254 #define MC_CMD_DRIVER_EVENT_IN_EVQ_LEN 4
12255 /* Bits 0 - 63 of event */
12256 #define MC_CMD_DRIVER_EVENT_IN_DATA_OFST 4
12258 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_OFST 4
12259 #define MC_CMD_DRIVER_EVENT_IN_DATA_LO_LEN 4
12263 #define MC_CMD_DRIVER_EVENT_IN_DATA_HI_LEN 4
12268 #define MC_CMD_DRIVER_EVENT_OUT_LEN 0
12278 #define MC_CMD_PROXY_CMD 0x5b
12284 #define MC_CMD_PROXY_CMD_IN_LEN 4
12286 #define MC_CMD_PROXY_CMD_IN_TARGET_OFST 0
12287 #define MC_CMD_PROXY_CMD_IN_TARGET_LEN 4
12288 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_OFST 0
12289 #define MC_CMD_PROXY_CMD_IN_TARGET_PF_LBN 0
12291 #define MC_CMD_PROXY_CMD_IN_TARGET_VF_OFST 0
12294 #define MC_CMD_PROXY_CMD_IN_VF_NULL 0xffff /* enum */
12297 #define MC_CMD_PROXY_CMD_OUT_LEN 0
12304 #define MC_CMD_FILTER_OP 0x8a
12312 #define MC_CMD_FILTER_OP_IN_OP_OFST 0
12313 #define MC_CMD_FILTER_OP_IN_OP_LEN 4
12314 /* enum: single-recipient filter insert */
12315 #define MC_CMD_FILTER_OP_IN_OP_INSERT 0x0
12316 /* enum: single-recipient filter remove */
12317 #define MC_CMD_FILTER_OP_IN_OP_REMOVE 0x1
12318 /* enum: multi-recipient filter subscribe */
12319 #define MC_CMD_FILTER_OP_IN_OP_SUBSCRIBE 0x2
12320 /* enum: multi-recipient filter unsubscribe */
12321 #define MC_CMD_FILTER_OP_IN_OP_UNSUBSCRIBE 0x3
12322 /* enum: replace one recipient with another (warning - the filter handle may
12325 #define MC_CMD_FILTER_OP_IN_OP_REPLACE 0x4
12327 #define MC_CMD_FILTER_OP_IN_HANDLE_OFST 4
12329 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_OFST 4
12330 #define MC_CMD_FILTER_OP_IN_HANDLE_LO_LEN 4
12334 #define MC_CMD_FILTER_OP_IN_HANDLE_HI_LEN 4
12337 /* The port ID associated with the v-adaptor which should contain this filter.
12340 #define MC_CMD_FILTER_OP_IN_PORT_ID_LEN 4
12343 #define MC_CMD_FILTER_OP_IN_MATCH_FIELDS_LEN 4
12345 #define MC_CMD_FILTER_OP_IN_MATCH_SRC_IP_LBN 0
12357 #define MC_CMD_FILTER_OP_IN_MATCH_DST_MAC_LBN 4
12391 #define MC_CMD_FILTER_OP_IN_RX_DEST_LEN 4
12393 #define MC_CMD_FILTER_OP_IN_RX_DEST_DROP 0x0
12395 #define MC_CMD_FILTER_OP_IN_RX_DEST_HOST 0x1
12397 #define MC_CMD_FILTER_OP_IN_RX_DEST_MC 0x2
12398 /* enum: loop back to TXDP 0 */
12399 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX0 0x3
12401 #define MC_CMD_FILTER_OP_IN_RX_DEST_TX1 0x4
12404 #define MC_CMD_FILTER_OP_IN_RX_QUEUE_LEN 4
12407 #define MC_CMD_FILTER_OP_IN_RX_MODE_LEN 4
12409 #define MC_CMD_FILTER_OP_IN_RX_MODE_SIMPLE 0x0
12411 #define MC_CMD_FILTER_OP_IN_RX_MODE_RSS 0x1
12413 #define MC_CMD_FILTER_OP_IN_RX_MODE_DOT1P_MAPPING 0x2
12416 #define MC_CMD_FILTER_OP_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12422 #define MC_CMD_FILTER_OP_IN_RX_CONTEXT_LEN 4
12423 /* transmit domain (reserved; set to 0) */
12425 #define MC_CMD_FILTER_OP_IN_TX_DOMAIN_LEN 4
12431 #define MC_CMD_FILTER_OP_IN_TX_DEST_LEN 4
12433 #define MC_CMD_FILTER_OP_IN_TX_DEST_DEFAULT 0xffffffff
12435 #define MC_CMD_FILTER_OP_IN_TX_DEST_MAC_LBN 0
12461 /* IP protocol to match (in low byte; set high byte to 0) */
12464 /* Firmware defined register 0 to match (reserved; set to 0) */
12466 #define MC_CMD_FILTER_OP_IN_FWDEF0_LEN 4
12467 /* Firmware defined register 1 to match (reserved; set to 0) */
12469 #define MC_CMD_FILTER_OP_IN_FWDEF1_LEN 4
12471 * 0 for IPv4 address)
12476 * bytes to 0 for IPv4 address)
12487 #define MC_CMD_FILTER_OP_EXT_IN_OP_OFST 0
12488 #define MC_CMD_FILTER_OP_EXT_IN_OP_LEN 4
12492 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_OFST 4
12494 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_OFST 4
12495 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_LO_LEN 4
12499 #define MC_CMD_FILTER_OP_EXT_IN_HANDLE_HI_LEN 4
12502 /* The port ID associated with the v-adaptor which should contain this filter.
12505 #define MC_CMD_FILTER_OP_EXT_IN_PORT_ID_LEN 4
12508 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_FIELDS_LEN 4
12510 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_SRC_IP_LBN 0
12522 #define MC_CMD_FILTER_OP_EXT_IN_MATCH_DST_MAC_LBN 4
12598 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_LEN 4
12600 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_DROP 0x0
12602 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_HOST 0x1
12604 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_MC 0x2
12605 /* enum: loop back to TXDP 0 */
12606 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX0 0x3
12608 #define MC_CMD_FILTER_OP_EXT_IN_RX_DEST_TX1 0x4
12611 #define MC_CMD_FILTER_OP_EXT_IN_RX_QUEUE_LEN 4
12614 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_LEN 4
12616 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_SIMPLE 0x0
12618 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_RSS 0x1
12620 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_DOT1P_MAPPING 0x2
12623 #define MC_CMD_FILTER_OP_EXT_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12629 #define MC_CMD_FILTER_OP_EXT_IN_RX_CONTEXT_LEN 4
12630 /* transmit domain (reserved; set to 0) */
12632 #define MC_CMD_FILTER_OP_EXT_IN_TX_DOMAIN_LEN 4
12638 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_LEN 4
12640 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_DEFAULT 0xffffffff
12642 #define MC_CMD_FILTER_OP_EXT_IN_TX_DEST_MAC_LBN 0
12668 /* IP protocol to match (in low byte; set high byte to 0) */
12671 /* Firmware defined register 0 to match (reserved; set to 0) */
12673 #define MC_CMD_FILTER_OP_EXT_IN_FWDEF0_LEN 4
12675 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12679 #define MC_CMD_FILTER_OP_EXT_IN_VNI_OR_VSID_LEN 4
12681 #define MC_CMD_FILTER_OP_EXT_IN_VNI_VALUE_LBN 0
12687 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_VXLAN 0x0
12689 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_GENEVE 0x1
12691 #define MC_CMD_FILTER_OP_EXT_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12693 #define MC_CMD_FILTER_OP_EXT_IN_VSID_VALUE_LBN 0
12699 #define MC_CMD_FILTER_OP_EXT_IN_VSID_TYPE_NVGRE 0x0
12701 * 0 for IPv4 address)
12706 * bytes to 0 for IPv4 address)
12741 * 0)
12745 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
12746 * to 0)
12749 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF0_LEN 4
12751 * to 0)
12754 #define MC_CMD_FILTER_OP_EXT_IN_IFRM_FWDEF1_LEN 4
12756 * order; set last 12 bytes to 0 for IPv4 address)
12761 * order; set last 12 bytes to 0 for IPv4 address)
12775 #define MC_CMD_FILTER_OP_V3_IN_OP_OFST 0
12776 #define MC_CMD_FILTER_OP_V3_IN_OP_LEN 4
12780 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_OFST 4
12782 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_OFST 4
12783 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_LO_LEN 4
12787 #define MC_CMD_FILTER_OP_V3_IN_HANDLE_HI_LEN 4
12790 /* The port ID associated with the v-adaptor which should contain this filter.
12793 #define MC_CMD_FILTER_OP_V3_IN_PORT_ID_LEN 4
12796 #define MC_CMD_FILTER_OP_V3_IN_MATCH_FIELDS_LEN 4
12798 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SRC_IP_LBN 0
12810 #define MC_CMD_FILTER_OP_V3_IN_MATCH_DST_MAC_LBN 4
12886 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_LEN 4
12888 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_DROP 0x0
12890 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_HOST 0x1
12892 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_MC 0x2
12893 /* enum: loop back to TXDP 0 */
12894 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX0 0x3
12896 #define MC_CMD_FILTER_OP_V3_IN_RX_DEST_TX1 0x4
12899 #define MC_CMD_FILTER_OP_V3_IN_RX_QUEUE_LEN 4
12902 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_LEN 4
12904 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_SIMPLE 0x0
12906 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_RSS 0x1
12908 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_DOT1P_MAPPING 0x2
12911 #define MC_CMD_FILTER_OP_V3_IN_RX_MODE_TEST_NEVER_MATCH 0x80000000
12917 #define MC_CMD_FILTER_OP_V3_IN_RX_CONTEXT_LEN 4
12918 /* transmit domain (reserved; set to 0) */
12920 #define MC_CMD_FILTER_OP_V3_IN_TX_DOMAIN_LEN 4
12926 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_LEN 4
12928 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_DEFAULT 0xffffffff
12930 #define MC_CMD_FILTER_OP_V3_IN_TX_DEST_MAC_LBN 0
12956 /* IP protocol to match (in low byte; set high byte to 0) */
12959 /* Firmware defined register 0 to match (reserved; set to 0) */
12961 #define MC_CMD_FILTER_OP_V3_IN_FWDEF0_LEN 4
12963 * protocol is GRE) to match (as bytes in network order; set last byte to 0 for
12967 #define MC_CMD_FILTER_OP_V3_IN_VNI_OR_VSID_LEN 4
12969 #define MC_CMD_FILTER_OP_V3_IN_VNI_VALUE_LBN 0
12975 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_VXLAN 0x0
12977 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_GENEVE 0x1
12979 #define MC_CMD_FILTER_OP_V3_IN_VNI_TYPE_EXPERIMENTAL 0xfe
12981 #define MC_CMD_FILTER_OP_V3_IN_VSID_VALUE_LBN 0
12987 #define MC_CMD_FILTER_OP_V3_IN_VSID_TYPE_NVGRE 0x0
12989 * 0 for IPv4 address)
12994 * bytes to 0 for IPv4 address)
13029 * 0)
13033 /* VXLAN/NVGRE inner frame Firmware defined register 0 to match (reserved; set
13034 * to 0)
13037 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF0_LEN 4
13039 * to 0)
13042 #define MC_CMD_FILTER_OP_V3_IN_IFRM_FWDEF1_LEN 4
13044 * order; set last 12 bytes to 0 for IPv4 address)
13049 * order; set last 12 bytes to 0 for IPv4 address)
13056 * else user_flag = req.MATCH_SET_FLAG; if (req.MATCH_SET_MARK == 0) user_mark
13057 * = 0; else if (req.MATCH_BITOR_MARK == 1) user_mark = req.MATCH_SET_MARK
13064 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAGS_LEN 4
13066 #define MC_CMD_FILTER_OP_V3_IN_MATCH_SET_FLAG_LBN 0
13078 #define MC_CMD_FILTER_OP_V3_IN_MATCH_STRIP_VLAN_LBN 4
13081 * functionality of this field in an ABI-backwards-compatible manner, and
13086 * Firmware Driver Interface (SF-119419-TC). Requesting anything other than
13091 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_LEN 4
13093 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_NONE 0x0
13098 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_FLAG 0x1
13103 #define MC_CMD_FILTER_OP_V3_IN_MATCH_ACTION_MARK 0x2
13109 #define MC_CMD_FILTER_OP_V3_IN_MATCH_MARK_VALUE_LEN 4
13114 #define MC_CMD_FILTER_OP_OUT_OP_OFST 0
13115 #define MC_CMD_FILTER_OP_OUT_OP_LEN 4
13120 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
13122 #define MC_CMD_FILTER_OP_OUT_HANDLE_OFST 4
13124 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_OFST 4
13125 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_LEN 4
13129 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_LEN 4
13133 #define MC_CMD_FILTER_OP_OUT_HANDLE_LO_INVALID 0xffffffff
13135 #define MC_CMD_FILTER_OP_OUT_HANDLE_HI_INVALID 0xffffffff
13140 #define MC_CMD_FILTER_OP_EXT_OUT_OP_OFST 0
13141 #define MC_CMD_FILTER_OP_EXT_OUT_OP_LEN 4
13146 * 0xFFFFFFFF_FFFFFFFF is guaranteed never to be a valid handle.
13148 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_OFST 4
13150 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_OFST 4
13151 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_LO_LEN 4
13155 #define MC_CMD_FILTER_OP_EXT_OUT_HANDLE_HI_LEN 4
13164 * Get information related to the parser-dispatcher subsystem
13166 #define MC_CMD_GET_PARSER_DISP_INFO 0xe4
13172 #define MC_CMD_GET_PARSER_DISP_INFO_IN_LEN 4
13174 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_OFST 0
13175 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_LEN 4
13177 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_RX_MATCHES 0x1
13181 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_RESTRICTIONS 0x2
13182 /* enum: read properties relating to security rules (Medford-only; for use by
13183 * SolarSecure apps, not directly by drivers. See SF-114946-SW.)
13185 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SECURITY_RULE_INFO 0x3
13190 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_ENCAP_RX_MATCHES 0x4
13194 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_MATCHES 0x5
13196 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_VNIC_ENCAP_TYPES 0x6
13197 /* enum: read the supported RX filter matches for low-latency queues (as
13200 #define MC_CMD_GET_PARSER_DISP_INFO_IN_OP_GET_SUPPORTED_LL_RX_MATCHES 0x7
13206 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_LEN(num) (8+4*(num))
13207 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
13209 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_OFST 0
13210 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_OP_LEN 4
13214 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_OFST 4
13215 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_NUM_SUPPORTED_MATCHES_LEN 4
13220 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_LEN 4
13221 #define MC_CMD_GET_PARSER_DISP_INFO_OUT_SUPPORTED_MATCHES_MINNUM 0
13228 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_OFST 0
13229 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_OP_LEN 4
13233 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_OFST 4
13234 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_RESTRICTION_FLAGS_LEN 4
13235 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_OFST 4
13236 #define MC_CMD_GET_PARSER_DISP_RESTRICTIONS_OUT_DST_IP_MCAST_ONLY_LBN 0
13241 * (Medford-only; for use by SolarSecure apps, not directly by drivers. See
13242 * SF-114946-SW.) NOTE - this message definition is provisional. It has not yet
13248 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_OFST 0
13249 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_OP_LEN 4
13255 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_OFST 4
13256 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_LEN 4
13257 /* enum: implements lookup sequences described in SF-114946-SW draft C */
13258 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_RULES_VERSION_SF_114946_SW_C 0x0
13261 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_NODES_LEN 4
13264 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_MAP_NUM_ENTRIES_PER_NODE_LEN 4
13267 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MIN_LEN 4
13270 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_SUBNET_ID_MAX_LEN 4
13273 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_TREE_NUM_ENTRIES_LEN 4
13276 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MIN_LEN 4
13279 #define MC_CMD_GET_PARSER_DISP_SECURITY_RULE_INFO_OUT_PORTRANGE_ID_MAX_LEN 4
13290 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_LEN(num) (8+4*(num))
13291 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_NUM(len) (((len)-8)/4)
13293 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_OFST 0
13294 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_OP_LEN 4
13298 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_OFST 4
13299 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_NUM_SUPPORTED_MATCHES_LEN 4
13304 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_LEN 4
13305 #define MC_CMD_GET_PARSER_DISP_VNIC_ENCAP_MATCHES_OUT_SUPPORTED_MATCHES_MINNUM 0
13314 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_OFST 0
13315 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_OP_LEN 4
13318 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
13319 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
13320 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_OFST 4
13321 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_VXLAN_LBN 0
13323 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_NVGRE_OFST 4
13326 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_GENEVE_OFST 4
13329 #define MC_CMD_GET_PARSER_DISP_SUPPORTED_VNIC_ENCAP_TYPES_OUT_ENCAP_TYPE_L2GRE_OFST 4
13338 #define MC_CMD_GET_PORT_ASSIGNMENT 0xb8
13344 #define MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN 0
13347 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN 4
13351 * sense - e.g. virtio-blk), in which case the return value is NULL_PORT.
13353 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_OFST 0
13354 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_PORT_LEN 4
13356 #define MC_CMD_GET_PORT_ASSIGNMENT_OUT_NULL_PORT 0xffffffff
13363 #define MC_CMD_ALLOC_VIS 0x8b
13371 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_OFST 0
13372 #define MC_CMD_ALLOC_VIS_IN_MIN_VI_COUNT_LEN 4
13374 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_OFST 4
13375 #define MC_CMD_ALLOC_VIS_IN_MAX_VI_COUNT_LEN 4
13377 /* MC_CMD_ALLOC_VIS_OUT msgresponse: Huntington-compatible VI_ALLOC request.
13382 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_OFST 0
13383 #define MC_CMD_ALLOC_VIS_OUT_VI_COUNT_LEN 4
13387 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_OFST 4
13388 #define MC_CMD_ALLOC_VIS_OUT_VI_BASE_LEN 4
13393 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_OFST 0
13394 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_COUNT_LEN 4
13398 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_OFST 4
13399 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_BASE_LEN 4
13400 /* Function's port vi_shift value (always 0 on Huntington) */
13402 #define MC_CMD_ALLOC_VIS_EXT_OUT_VI_SHIFT_LEN 4
13410 #define MC_CMD_FREE_VIS 0x8c
13416 #define MC_CMD_FREE_VIS_IN_LEN 0
13419 #define MC_CMD_FREE_VIS_OUT_LEN 0
13426 #define MC_CMD_GET_SRIOV_CFG 0xba
13432 #define MC_CMD_GET_SRIOV_CFG_IN_LEN 0
13437 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_OFST 0
13438 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_CURRENT_LEN 4
13440 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_OFST 4
13441 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_MAX_LEN 4
13443 #define MC_CMD_GET_SRIOV_CFG_OUT_FLAGS_LEN 4
13445 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_ENABLED_LBN 0
13449 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_OFFSET_LEN 4
13452 #define MC_CMD_GET_SRIOV_CFG_OUT_VF_STRIDE_LEN 4
13459 #define MC_CMD_ALLOC_PIOBUF 0x8f
13465 #define MC_CMD_ALLOC_PIOBUF_IN_LEN 0
13468 #define MC_CMD_ALLOC_PIOBUF_OUT_LEN 4
13470 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_OFST 0
13471 #define MC_CMD_ALLOC_PIOBUF_OUT_PIOBUF_HANDLE_LEN 4
13478 #define MC_CMD_FREE_PIOBUF 0x90
13484 #define MC_CMD_FREE_PIOBUF_IN_LEN 4
13486 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
13487 #define MC_CMD_FREE_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
13490 #define MC_CMD_FREE_PIOBUF_OUT_LEN 0
13496 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13499 #define MC_CMD_GET_VI_TLP_PROCESSING 0xb0
13505 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_LEN 4
13507 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_OFST 0
13508 #define MC_CMD_GET_VI_TLP_PROCESSING_IN_INSTANCE_LEN 4
13514 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_LEN 4
13515 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_OFST 0
13516 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_DATA_LEN 4
13517 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_OFST 0
13518 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG1_RX_LBN 0
13520 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_TAG2_EV_OFST 0
13523 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_OFST 0
13526 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_PACKET_DATA_OFST 0
13529 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_ID_BASED_ORDERING_OFST 0
13532 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_NO_SNOOP_OFST 0
13535 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_TPH_ON_OFST 0
13538 #define MC_CMD_GET_VI_TLP_PROCESSING_V2_OUT_RELAXED_ORDERING_SYNC_DATA_OFST 0
13546 * GRP_FUNC_DMA privilege and must be the currently-assigned user of this VI or
13553 #define MC_CMD_SET_VI_TLP_PROCESSING 0xb1
13564 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_OFST 0
13565 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_INSTANCE_LEN 4
13566 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_OFST 4
13567 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_DATA_LEN 4
13568 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_OFST 4
13569 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG1_RX_LBN 0
13571 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_TAG2_EV_OFST 4
13574 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_OFST 4
13577 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_PACKET_DATA_OFST 4
13580 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_ID_BASED_ORDERING_OFST 4
13583 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_NO_SNOOP_OFST 4
13586 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_TPH_ON_OFST 4
13589 #define MC_CMD_SET_VI_TLP_PROCESSING_V2_IN_RELAXED_ORDERING_SYNC_DATA_OFST 4
13594 #define MC_CMD_SET_VI_TLP_PROCESSING_OUT_LEN 0
13603 #define MC_CMD_GET_CAPABILITIES 0xbe
13609 #define MC_CMD_GET_CAPABILITIES_IN_LEN 0
13614 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_OFST 0
13615 #define MC_CMD_GET_CAPABILITIES_OUT_FLAGS1_LEN 4
13616 #define MC_CMD_GET_CAPABILITIES_OUT_VPORT_RECONFIGURE_OFST 0
13619 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_OFST 0
13620 #define MC_CMD_GET_CAPABILITIES_OUT_TX_STRIPING_LBN 4
13622 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_QUERY_OFST 0
13625 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13628 #define MC_CMD_GET_CAPABILITIES_OUT_DRV_ATTACH_PREBOOT_OFST 0
13631 #define MC_CMD_GET_CAPABILITIES_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13634 #define MC_CMD_GET_CAPABILITIES_OUT_SET_MAC_ENHANCED_OFST 0
13637 #define MC_CMD_GET_CAPABILITIES_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13640 #define MC_CMD_GET_CAPABILITIES_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13643 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13646 #define MC_CMD_GET_CAPABILITIES_OUT_ADDITIONAL_RSS_MODES_OFST 0
13649 #define MC_CMD_GET_CAPABILITIES_OUT_QBB_OFST 0
13652 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13655 #define MC_CMD_GET_CAPABILITIES_OUT_RX_RSS_LIMITED_OFST 0
13658 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PACKED_STREAM_OFST 0
13661 #define MC_CMD_GET_CAPABILITIES_OUT_RX_INCLUDE_FCS_OFST 0
13664 #define MC_CMD_GET_CAPABILITIES_OUT_TX_VLAN_INSERTION_OFST 0
13667 #define MC_CMD_GET_CAPABILITIES_OUT_RX_VLAN_STRIPPING_OFST 0
13670 #define MC_CMD_GET_CAPABILITIES_OUT_TX_TSO_OFST 0
13673 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_0_OFST 0
13676 #define MC_CMD_GET_CAPABILITIES_OUT_RX_PREFIX_LEN_14_OFST 0
13679 #define MC_CMD_GET_CAPABILITIES_OUT_RX_TIMESTAMP_OFST 0
13682 #define MC_CMD_GET_CAPABILITIES_OUT_RX_BATCHING_OFST 0
13685 #define MC_CMD_GET_CAPABILITIES_OUT_MCAST_FILTER_CHAINING_OFST 0
13688 #define MC_CMD_GET_CAPABILITIES_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13691 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DISABLE_SCATTER_OFST 0
13694 #define MC_CMD_GET_CAPABILITIES_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13697 #define MC_CMD_GET_CAPABILITIES_OUT_EVB_OFST 0
13700 #define MC_CMD_GET_CAPABILITIES_OUT_VXLAN_NVGRE_OFST 0
13704 #define MC_CMD_GET_CAPABILITIES_OUT_RX_DPCPU_FW_ID_OFST 4
13707 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP 0x0
13709 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_LOW_LATENCY 0x1
13711 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_PACKED_STREAM 0x2
13713 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_RULES_ENGINE 0x5
13715 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_DPDK 0x6
13717 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_BIST 0x10a
13719 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13721 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13723 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13724 /* enum: RXDP Test firmware image 4 */
13725 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13727 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_BACKPRESSURE 0x105
13729 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13731 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13733 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13735 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13737 #define MC_CMD_GET_CAPABILITIES_OUT_RXDP_TEST_FW_SLOW 0x10c
13742 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP 0x0
13744 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_LOW_LATENCY 0x1
13746 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_HIGH_PACKET_RATE 0x3
13748 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_RULES_ENGINE 0x5
13750 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_DPDK 0x6
13752 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_BIST 0x12d
13754 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
13756 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
13758 #define MC_CMD_GET_CAPABILITIES_OUT_TXDP_TEST_FW_CSR 0x103
13762 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_REV_LBN 0
13766 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
13767 /* enum: reserved value - do not use (may indicate alternative interpretation
13770 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RESERVED 0x0
13774 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
13777 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13778 /* enum: RX PD firmware with approximately Siena-compatible behaviour
13781 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
13783 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
13785 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_VSWITCH 0x3
13789 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13791 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
13793 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
13797 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
13799 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
13800 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13801 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_L3XUDP 0x9
13803 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_DPDK 0xa
13805 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13809 #define MC_CMD_GET_CAPABILITIES_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
13813 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_REV_LBN 0
13817 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
13818 /* enum: reserved value - do not use (may indicate alternative interpretation
13821 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RESERVED 0x0
13825 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
13828 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
13829 /* enum: TX PD firmware with approximately Siena-compatible behaviour
13832 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
13834 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
13836 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_VSWITCH 0x3
13840 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
13841 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
13845 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
13847 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
13848 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
13849 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_L3XUDP 0x9
13851 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_DPDK 0xa
13853 #define MC_CMD_GET_CAPABILITIES_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
13856 #define MC_CMD_GET_CAPABILITIES_OUT_HW_CAPABILITIES_LEN 4
13859 #define MC_CMD_GET_CAPABILITIES_OUT_LICENSE_CAPABILITIES_LEN 4
13862 #define MC_CMD_GET_CAPABILITIES_V2_IN_LEN 0
13867 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_OFST 0
13868 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS1_LEN 4
13869 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VPORT_RECONFIGURE_OFST 0
13872 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_OFST 0
13873 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_STRIPING_LBN 4
13875 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_QUERY_OFST 0
13878 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
13881 #define MC_CMD_GET_CAPABILITIES_V2_OUT_DRV_ATTACH_PREBOOT_OFST 0
13884 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_FORCE_EVENT_MERGING_OFST 0
13887 #define MC_CMD_GET_CAPABILITIES_V2_OUT_SET_MAC_ENHANCED_OFST 0
13890 #define MC_CMD_GET_CAPABILITIES_V2_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
13893 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
13896 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
13899 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ADDITIONAL_RSS_MODES_OFST 0
13902 #define MC_CMD_GET_CAPABILITIES_V2_OUT_QBB_OFST 0
13905 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
13908 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_RSS_LIMITED_OFST 0
13911 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PACKED_STREAM_OFST 0
13914 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_INCLUDE_FCS_OFST 0
13917 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_VLAN_INSERTION_OFST 0
13920 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_VLAN_STRIPPING_OFST 0
13923 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_OFST 0
13926 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_0_OFST 0
13929 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_PREFIX_LEN_14_OFST 0
13932 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_TIMESTAMP_OFST 0
13935 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_BATCHING_OFST 0
13938 #define MC_CMD_GET_CAPABILITIES_V2_OUT_MCAST_FILTER_CHAINING_OFST 0
13941 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PM_AND_RXDP_COUNTERS_OFST 0
13944 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DISABLE_SCATTER_OFST 0
13947 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
13950 #define MC_CMD_GET_CAPABILITIES_V2_OUT_EVB_OFST 0
13953 #define MC_CMD_GET_CAPABILITIES_V2_OUT_VXLAN_NVGRE_OFST 0
13957 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_DPCPU_FW_ID_OFST 4
13960 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP 0x0
13962 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_LOW_LATENCY 0x1
13964 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_PACKED_STREAM 0x2
13966 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_RULES_ENGINE 0x5
13968 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_DPDK 0x6
13970 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_BIST 0x10a
13972 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
13974 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
13976 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
13977 /* enum: RXDP Test firmware image 4 */
13978 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
13980 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_BACKPRESSURE 0x105
13982 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
13984 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
13986 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
13988 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
13990 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXDP_TEST_FW_SLOW 0x10c
13995 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP 0x0
13997 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_LOW_LATENCY 0x1
13999 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_HIGH_PACKET_RATE 0x3
14001 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_RULES_ENGINE 0x5
14003 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_DPDK 0x6
14005 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_BIST 0x12d
14007 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14009 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14011 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXDP_TEST_FW_CSR 0x103
14015 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_REV_LBN 0
14019 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14020 /* enum: reserved value - do not use (may indicate alternative interpretation
14023 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RESERVED 0x0
14027 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14030 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14031 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14034 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14036 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14038 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14042 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14044 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14046 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14050 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14052 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14053 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14054 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14056 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_DPDK 0xa
14058 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14062 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14066 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_REV_LBN 0
14070 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14071 /* enum: reserved value - do not use (may indicate alternative interpretation
14074 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RESERVED 0x0
14078 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14081 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14082 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14085 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14087 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14089 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14093 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14094 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14098 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14100 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14101 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14102 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14104 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_DPDK 0xa
14106 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14109 #define MC_CMD_GET_CAPABILITIES_V2_OUT_HW_CAPABILITIES_LEN 4
14112 #define MC_CMD_GET_CAPABILITIES_V2_OUT_LICENSE_CAPABILITIES_LEN 4
14115 #define MC_CMD_GET_CAPABILITIES_V2_OUT_FLAGS2_LEN 4
14117 #define MC_CMD_GET_CAPABILITIES_V2_OUT_TX_TSO_V2_LBN 0
14129 #define MC_CMD_GET_CAPABILITIES_V2_OUT_RX_CUT_THROUGH_LBN 4
14231 #define MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff
14233 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe
14235 #define MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_ASSIGNED 0xfd
14242 #define MC_CMD_GET_CAPABILITIES_V2_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14250 /* MC_CMD_GET_CAPABILITIES_V2_OUT_ACCESS_NOT_PERMITTED 0xff */
14252 /* MC_CMD_GET_CAPABILITIES_V2_OUT_PF_NOT_PRESENT 0xfe */
14253 /* Number of VIs available for external ports 0-3. For devices with more than
14259 #define MC_CMD_GET_CAPABILITIES_V2_OUT_NUM_VIS_PER_PORT_NUM 4
14280 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_OFST 0
14281 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS1_LEN 4
14282 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VPORT_RECONFIGURE_OFST 0
14285 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_OFST 0
14286 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_STRIPING_LBN 4
14288 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_QUERY_OFST 0
14291 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14294 #define MC_CMD_GET_CAPABILITIES_V3_OUT_DRV_ATTACH_PREBOOT_OFST 0
14297 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14300 #define MC_CMD_GET_CAPABILITIES_V3_OUT_SET_MAC_ENHANCED_OFST 0
14303 #define MC_CMD_GET_CAPABILITIES_V3_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14306 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14309 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14312 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ADDITIONAL_RSS_MODES_OFST 0
14315 #define MC_CMD_GET_CAPABILITIES_V3_OUT_QBB_OFST 0
14318 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14321 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_RSS_LIMITED_OFST 0
14324 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PACKED_STREAM_OFST 0
14327 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_INCLUDE_FCS_OFST 0
14330 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_VLAN_INSERTION_OFST 0
14333 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_VLAN_STRIPPING_OFST 0
14336 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_OFST 0
14339 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_0_OFST 0
14342 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_PREFIX_LEN_14_OFST 0
14345 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_TIMESTAMP_OFST 0
14348 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_BATCHING_OFST 0
14351 #define MC_CMD_GET_CAPABILITIES_V3_OUT_MCAST_FILTER_CHAINING_OFST 0
14354 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14357 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DISABLE_SCATTER_OFST 0
14360 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14363 #define MC_CMD_GET_CAPABILITIES_V3_OUT_EVB_OFST 0
14366 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VXLAN_NVGRE_OFST 0
14370 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_DPCPU_FW_ID_OFST 4
14373 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP 0x0
14375 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_LOW_LATENCY 0x1
14377 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_PACKED_STREAM 0x2
14379 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_RULES_ENGINE 0x5
14381 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_DPDK 0x6
14383 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_BIST 0x10a
14385 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14387 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14389 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14390 /* enum: RXDP Test firmware image 4 */
14391 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14393 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_BACKPRESSURE 0x105
14395 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14397 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14399 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14401 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14403 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXDP_TEST_FW_SLOW 0x10c
14408 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP 0x0
14410 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_LOW_LATENCY 0x1
14412 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_HIGH_PACKET_RATE 0x3
14414 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_RULES_ENGINE 0x5
14416 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_DPDK 0x6
14418 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_BIST 0x12d
14420 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14422 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14424 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXDP_TEST_FW_CSR 0x103
14428 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_REV_LBN 0
14432 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14433 /* enum: reserved value - do not use (may indicate alternative interpretation
14436 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RESERVED 0x0
14440 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14443 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14444 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14447 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14449 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14451 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14455 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14457 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14459 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14463 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14465 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14466 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14467 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14469 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_DPDK 0xa
14471 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14475 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14479 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_REV_LBN 0
14483 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14484 /* enum: reserved value - do not use (may indicate alternative interpretation
14487 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RESERVED 0x0
14491 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14494 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14495 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14498 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14500 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14502 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14506 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14507 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14511 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14513 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14514 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14515 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14517 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_DPDK 0xa
14519 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14522 #define MC_CMD_GET_CAPABILITIES_V3_OUT_HW_CAPABILITIES_LEN 4
14525 #define MC_CMD_GET_CAPABILITIES_V3_OUT_LICENSE_CAPABILITIES_LEN 4
14528 #define MC_CMD_GET_CAPABILITIES_V3_OUT_FLAGS2_LEN 4
14530 #define MC_CMD_GET_CAPABILITIES_V3_OUT_TX_TSO_V2_LBN 0
14542 #define MC_CMD_GET_CAPABILITIES_V3_OUT_RX_CUT_THROUGH_LBN 4
14644 #define MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff
14646 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe
14648 #define MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_ASSIGNED 0xfd
14655 #define MC_CMD_GET_CAPABILITIES_V3_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
14663 /* MC_CMD_GET_CAPABILITIES_V3_OUT_ACCESS_NOT_PERMITTED 0xff */
14665 /* MC_CMD_GET_CAPABILITIES_V3_OUT_PF_NOT_PRESENT 0xfe */
14666 /* Number of VIs available for external ports 0-3. For devices with more than
14672 #define MC_CMD_GET_CAPABILITIES_V3_OUT_NUM_VIS_PER_PORT_NUM 4
14691 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
14696 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
14699 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_8K 0x0
14700 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
14701 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_16K 0x1
14702 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
14703 #define MC_CMD_GET_CAPABILITIES_V3_OUT_VI_WINDOW_MODE_64K 0x2
14705 * (SF-115995-SW) in the present configuration of firmware and port mode.
14710 * (SF-115995-SW) in the present configuration of firmware and port mode.
14718 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_OFST 0
14719 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS1_LEN 4
14720 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VPORT_RECONFIGURE_OFST 0
14723 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_OFST 0
14724 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_STRIPING_LBN 4
14726 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_QUERY_OFST 0
14729 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
14732 #define MC_CMD_GET_CAPABILITIES_V4_OUT_DRV_ATTACH_PREBOOT_OFST 0
14735 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_FORCE_EVENT_MERGING_OFST 0
14738 #define MC_CMD_GET_CAPABILITIES_V4_OUT_SET_MAC_ENHANCED_OFST 0
14741 #define MC_CMD_GET_CAPABILITIES_V4_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
14744 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
14747 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
14750 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ADDITIONAL_RSS_MODES_OFST 0
14753 #define MC_CMD_GET_CAPABILITIES_V4_OUT_QBB_OFST 0
14756 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
14759 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_RSS_LIMITED_OFST 0
14762 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PACKED_STREAM_OFST 0
14765 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_INCLUDE_FCS_OFST 0
14768 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_VLAN_INSERTION_OFST 0
14771 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_VLAN_STRIPPING_OFST 0
14774 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_OFST 0
14777 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_0_OFST 0
14780 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_PREFIX_LEN_14_OFST 0
14783 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_TIMESTAMP_OFST 0
14786 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_BATCHING_OFST 0
14789 #define MC_CMD_GET_CAPABILITIES_V4_OUT_MCAST_FILTER_CHAINING_OFST 0
14792 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PM_AND_RXDP_COUNTERS_OFST 0
14795 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DISABLE_SCATTER_OFST 0
14798 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
14801 #define MC_CMD_GET_CAPABILITIES_V4_OUT_EVB_OFST 0
14804 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VXLAN_NVGRE_OFST 0
14808 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_DPCPU_FW_ID_OFST 4
14811 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP 0x0
14813 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_LOW_LATENCY 0x1
14815 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_PACKED_STREAM 0x2
14817 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_RULES_ENGINE 0x5
14819 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_DPDK 0x6
14821 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_BIST 0x10a
14823 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
14825 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
14827 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
14828 /* enum: RXDP Test firmware image 4 */
14829 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
14831 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_BACKPRESSURE 0x105
14833 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
14835 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
14837 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
14839 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
14841 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXDP_TEST_FW_SLOW 0x10c
14846 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP 0x0
14848 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_LOW_LATENCY 0x1
14850 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_HIGH_PACKET_RATE 0x3
14852 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_RULES_ENGINE 0x5
14854 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_DPDK 0x6
14856 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_BIST 0x12d
14858 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
14860 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
14862 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXDP_TEST_FW_CSR 0x103
14866 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_REV_LBN 0
14870 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
14871 /* enum: reserved value - do not use (may indicate alternative interpretation
14874 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RESERVED 0x0
14878 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
14881 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14882 /* enum: RX PD firmware with approximately Siena-compatible behaviour
14885 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
14887 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
14889 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_VSWITCH 0x3
14893 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14895 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
14897 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
14901 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
14903 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
14904 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14905 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_L3XUDP 0x9
14907 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_DPDK 0xa
14909 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14913 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
14917 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_REV_LBN 0
14921 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
14922 /* enum: reserved value - do not use (may indicate alternative interpretation
14925 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RESERVED 0x0
14929 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
14932 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
14933 /* enum: TX PD firmware with approximately Siena-compatible behaviour
14936 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
14938 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
14940 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_VSWITCH 0x3
14944 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
14945 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
14949 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
14951 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
14952 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
14953 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_L3XUDP 0x9
14955 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_DPDK 0xa
14957 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
14960 #define MC_CMD_GET_CAPABILITIES_V4_OUT_HW_CAPABILITIES_LEN 4
14963 #define MC_CMD_GET_CAPABILITIES_V4_OUT_LICENSE_CAPABILITIES_LEN 4
14966 #define MC_CMD_GET_CAPABILITIES_V4_OUT_FLAGS2_LEN 4
14968 #define MC_CMD_GET_CAPABILITIES_V4_OUT_TX_TSO_V2_LBN 0
14980 #define MC_CMD_GET_CAPABILITIES_V4_OUT_RX_CUT_THROUGH_LBN 4
15082 #define MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff
15084 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe
15086 #define MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_ASSIGNED 0xfd
15093 #define MC_CMD_GET_CAPABILITIES_V4_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15101 /* MC_CMD_GET_CAPABILITIES_V4_OUT_ACCESS_NOT_PERMITTED 0xff */
15103 /* MC_CMD_GET_CAPABILITIES_V4_OUT_PF_NOT_PRESENT 0xfe */
15104 /* Number of VIs available for external ports 0-3. For devices with more than
15110 #define MC_CMD_GET_CAPABILITIES_V4_OUT_NUM_VIS_PER_PORT_NUM 4
15129 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15134 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15137 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_8K 0x0
15138 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15139 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_16K 0x1
15140 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15141 #define MC_CMD_GET_CAPABILITIES_V4_OUT_VI_WINDOW_MODE_64K 0x2
15143 * (SF-115995-SW) in the present configuration of firmware and port mode.
15148 * (SF-115995-SW) in the present configuration of firmware and port mode.
15154 * hold at least this many 64-bit stats values, if they wish to receive all
15164 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_OFST 0
15165 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS1_LEN 4
15166 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VPORT_RECONFIGURE_OFST 0
15169 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_OFST 0
15170 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_STRIPING_LBN 4
15172 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_QUERY_OFST 0
15175 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15178 #define MC_CMD_GET_CAPABILITIES_V5_OUT_DRV_ATTACH_PREBOOT_OFST 0
15181 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15184 #define MC_CMD_GET_CAPABILITIES_V5_OUT_SET_MAC_ENHANCED_OFST 0
15187 #define MC_CMD_GET_CAPABILITIES_V5_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15190 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15193 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15196 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ADDITIONAL_RSS_MODES_OFST 0
15199 #define MC_CMD_GET_CAPABILITIES_V5_OUT_QBB_OFST 0
15202 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15205 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_RSS_LIMITED_OFST 0
15208 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PACKED_STREAM_OFST 0
15211 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_INCLUDE_FCS_OFST 0
15214 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_VLAN_INSERTION_OFST 0
15217 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_VLAN_STRIPPING_OFST 0
15220 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_OFST 0
15223 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_0_OFST 0
15226 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_PREFIX_LEN_14_OFST 0
15229 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_TIMESTAMP_OFST 0
15232 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_BATCHING_OFST 0
15235 #define MC_CMD_GET_CAPABILITIES_V5_OUT_MCAST_FILTER_CHAINING_OFST 0
15238 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15241 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DISABLE_SCATTER_OFST 0
15244 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15247 #define MC_CMD_GET_CAPABILITIES_V5_OUT_EVB_OFST 0
15250 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VXLAN_NVGRE_OFST 0
15254 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_DPCPU_FW_ID_OFST 4
15257 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP 0x0
15259 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_LOW_LATENCY 0x1
15261 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_PACKED_STREAM 0x2
15263 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_RULES_ENGINE 0x5
15265 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_DPDK 0x6
15267 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_BIST 0x10a
15269 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15271 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15273 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15274 /* enum: RXDP Test firmware image 4 */
15275 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15277 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_BACKPRESSURE 0x105
15279 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15281 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15283 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15285 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15287 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXDP_TEST_FW_SLOW 0x10c
15292 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP 0x0
15294 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_LOW_LATENCY 0x1
15296 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_HIGH_PACKET_RATE 0x3
15298 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_RULES_ENGINE 0x5
15300 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_DPDK 0x6
15302 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_BIST 0x12d
15304 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15306 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15308 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXDP_TEST_FW_CSR 0x103
15312 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_REV_LBN 0
15316 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15317 /* enum: reserved value - do not use (may indicate alternative interpretation
15320 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RESERVED 0x0
15324 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15327 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15328 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15331 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15333 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15335 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15339 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15341 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15343 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15347 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15349 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15350 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15351 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15353 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_DPDK 0xa
15355 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15359 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15363 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_REV_LBN 0
15367 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15368 /* enum: reserved value - do not use (may indicate alternative interpretation
15371 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RESERVED 0x0
15375 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15378 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15379 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15382 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15384 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15386 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15390 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15391 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15395 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15397 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15398 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15399 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15401 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_DPDK 0xa
15403 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15406 #define MC_CMD_GET_CAPABILITIES_V5_OUT_HW_CAPABILITIES_LEN 4
15409 #define MC_CMD_GET_CAPABILITIES_V5_OUT_LICENSE_CAPABILITIES_LEN 4
15412 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FLAGS2_LEN 4
15414 #define MC_CMD_GET_CAPABILITIES_V5_OUT_TX_TSO_V2_LBN 0
15426 #define MC_CMD_GET_CAPABILITIES_V5_OUT_RX_CUT_THROUGH_LBN 4
15528 #define MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff
15530 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe
15532 #define MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_ASSIGNED 0xfd
15539 #define MC_CMD_GET_CAPABILITIES_V5_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15547 /* MC_CMD_GET_CAPABILITIES_V5_OUT_ACCESS_NOT_PERMITTED 0xff */
15549 /* MC_CMD_GET_CAPABILITIES_V5_OUT_PF_NOT_PRESENT 0xfe */
15550 /* Number of VIs available for external ports 0-3. For devices with more than
15556 #define MC_CMD_GET_CAPABILITIES_V5_OUT_NUM_VIS_PER_PORT_NUM 4
15575 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
15580 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
15583 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_8K 0x0
15584 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
15585 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_16K 0x1
15586 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
15587 #define MC_CMD_GET_CAPABILITIES_V5_OUT_VI_WINDOW_MODE_64K 0x2
15589 * (SF-115995-SW) in the present configuration of firmware and port mode.
15594 * (SF-115995-SW) in the present configuration of firmware and port mode.
15600 * hold at least this many 64-bit stats values, if they wish to receive all
15607 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
15610 #define MC_CMD_GET_CAPABILITIES_V5_OUT_FILTER_ACTION_MARK_MAX_LEN 4
15615 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_OFST 0
15616 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS1_LEN 4
15617 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VPORT_RECONFIGURE_OFST 0
15620 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_OFST 0
15621 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_STRIPING_LBN 4
15623 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_QUERY_OFST 0
15626 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
15629 #define MC_CMD_GET_CAPABILITIES_V6_OUT_DRV_ATTACH_PREBOOT_OFST 0
15632 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_FORCE_EVENT_MERGING_OFST 0
15635 #define MC_CMD_GET_CAPABILITIES_V6_OUT_SET_MAC_ENHANCED_OFST 0
15638 #define MC_CMD_GET_CAPABILITIES_V6_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
15641 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
15644 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
15647 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ADDITIONAL_RSS_MODES_OFST 0
15650 #define MC_CMD_GET_CAPABILITIES_V6_OUT_QBB_OFST 0
15653 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
15656 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_RSS_LIMITED_OFST 0
15659 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PACKED_STREAM_OFST 0
15662 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_INCLUDE_FCS_OFST 0
15665 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_VLAN_INSERTION_OFST 0
15668 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_VLAN_STRIPPING_OFST 0
15671 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_OFST 0
15674 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_0_OFST 0
15677 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_PREFIX_LEN_14_OFST 0
15680 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_TIMESTAMP_OFST 0
15683 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_BATCHING_OFST 0
15686 #define MC_CMD_GET_CAPABILITIES_V6_OUT_MCAST_FILTER_CHAINING_OFST 0
15689 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PM_AND_RXDP_COUNTERS_OFST 0
15692 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DISABLE_SCATTER_OFST 0
15695 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
15698 #define MC_CMD_GET_CAPABILITIES_V6_OUT_EVB_OFST 0
15701 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VXLAN_NVGRE_OFST 0
15705 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_DPCPU_FW_ID_OFST 4
15708 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP 0x0
15710 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_LOW_LATENCY 0x1
15712 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_PACKED_STREAM 0x2
15714 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_RULES_ENGINE 0x5
15716 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_DPDK 0x6
15718 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_BIST 0x10a
15720 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
15722 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
15724 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
15725 /* enum: RXDP Test firmware image 4 */
15726 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
15728 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_BACKPRESSURE 0x105
15730 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
15732 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
15734 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
15736 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
15738 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXDP_TEST_FW_SLOW 0x10c
15743 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP 0x0
15745 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_LOW_LATENCY 0x1
15747 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_HIGH_PACKET_RATE 0x3
15749 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_RULES_ENGINE 0x5
15751 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_DPDK 0x6
15753 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_BIST 0x12d
15755 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
15757 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
15759 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXDP_TEST_FW_CSR 0x103
15763 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_REV_LBN 0
15767 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
15768 /* enum: reserved value - do not use (may indicate alternative interpretation
15771 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RESERVED 0x0
15775 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
15778 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15779 /* enum: RX PD firmware with approximately Siena-compatible behaviour
15782 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
15784 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
15786 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_VSWITCH 0x3
15790 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15792 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
15794 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
15798 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
15800 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
15801 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15802 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_L3XUDP 0x9
15804 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_DPDK 0xa
15806 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15810 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
15814 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_REV_LBN 0
15818 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
15819 /* enum: reserved value - do not use (may indicate alternative interpretation
15822 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RESERVED 0x0
15826 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
15829 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
15830 /* enum: TX PD firmware with approximately Siena-compatible behaviour
15833 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
15835 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
15837 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_VSWITCH 0x3
15841 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
15842 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
15846 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
15848 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
15849 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
15850 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_L3XUDP 0x9
15852 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_DPDK 0xa
15854 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
15857 #define MC_CMD_GET_CAPABILITIES_V6_OUT_HW_CAPABILITIES_LEN 4
15860 #define MC_CMD_GET_CAPABILITIES_V6_OUT_LICENSE_CAPABILITIES_LEN 4
15863 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FLAGS2_LEN 4
15865 #define MC_CMD_GET_CAPABILITIES_V6_OUT_TX_TSO_V2_LBN 0
15877 #define MC_CMD_GET_CAPABILITIES_V6_OUT_RX_CUT_THROUGH_LBN 4
15979 #define MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff
15981 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe
15983 #define MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_ASSIGNED 0xfd
15990 #define MC_CMD_GET_CAPABILITIES_V6_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
15998 /* MC_CMD_GET_CAPABILITIES_V6_OUT_ACCESS_NOT_PERMITTED 0xff */
16000 /* MC_CMD_GET_CAPABILITIES_V6_OUT_PF_NOT_PRESENT 0xfe */
16001 /* Number of VIs available for external ports 0-3. For devices with more than
16007 #define MC_CMD_GET_CAPABILITIES_V6_OUT_NUM_VIS_PER_PORT_NUM 4
16026 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16031 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16034 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_8K 0x0
16035 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16036 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_16K 0x1
16037 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16038 #define MC_CMD_GET_CAPABILITIES_V6_OUT_VI_WINDOW_MODE_64K 0x2
16040 * (SF-115995-SW) in the present configuration of firmware and port mode.
16045 * (SF-115995-SW) in the present configuration of firmware and port mode.
16051 * hold at least this many 64-bit stats values, if they wish to receive all
16058 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16061 #define MC_CMD_GET_CAPABILITIES_V6_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16071 #define MC_CMD_GET_CAPABILITIES_V6_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16077 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_OFST 0
16078 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS1_LEN 4
16079 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VPORT_RECONFIGURE_OFST 0
16082 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_OFST 0
16083 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_STRIPING_LBN 4
16085 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_QUERY_OFST 0
16088 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16091 #define MC_CMD_GET_CAPABILITIES_V7_OUT_DRV_ATTACH_PREBOOT_OFST 0
16094 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16097 #define MC_CMD_GET_CAPABILITIES_V7_OUT_SET_MAC_ENHANCED_OFST 0
16100 #define MC_CMD_GET_CAPABILITIES_V7_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16103 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16106 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16109 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ADDITIONAL_RSS_MODES_OFST 0
16112 #define MC_CMD_GET_CAPABILITIES_V7_OUT_QBB_OFST 0
16115 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16118 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_RSS_LIMITED_OFST 0
16121 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PACKED_STREAM_OFST 0
16124 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_INCLUDE_FCS_OFST 0
16127 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_VLAN_INSERTION_OFST 0
16130 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_VLAN_STRIPPING_OFST 0
16133 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_OFST 0
16136 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_0_OFST 0
16139 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_PREFIX_LEN_14_OFST 0
16142 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_TIMESTAMP_OFST 0
16145 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_BATCHING_OFST 0
16148 #define MC_CMD_GET_CAPABILITIES_V7_OUT_MCAST_FILTER_CHAINING_OFST 0
16151 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16154 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DISABLE_SCATTER_OFST 0
16157 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16160 #define MC_CMD_GET_CAPABILITIES_V7_OUT_EVB_OFST 0
16163 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VXLAN_NVGRE_OFST 0
16167 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_DPCPU_FW_ID_OFST 4
16170 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP 0x0
16172 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_LOW_LATENCY 0x1
16174 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_PACKED_STREAM 0x2
16176 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_RULES_ENGINE 0x5
16178 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_DPDK 0x6
16180 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_BIST 0x10a
16182 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16184 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16186 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16187 /* enum: RXDP Test firmware image 4 */
16188 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16190 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_BACKPRESSURE 0x105
16192 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16194 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16196 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16198 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16200 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXDP_TEST_FW_SLOW 0x10c
16205 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP 0x0
16207 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_LOW_LATENCY 0x1
16209 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_HIGH_PACKET_RATE 0x3
16211 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_RULES_ENGINE 0x5
16213 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_DPDK 0x6
16215 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_BIST 0x12d
16217 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16219 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16221 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXDP_TEST_FW_CSR 0x103
16225 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_REV_LBN 0
16229 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16230 /* enum: reserved value - do not use (may indicate alternative interpretation
16233 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RESERVED 0x0
16237 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16240 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16241 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16244 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16246 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16248 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16252 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16254 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16256 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16260 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16262 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16263 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16264 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16266 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_DPDK 0xa
16268 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16272 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16276 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_REV_LBN 0
16280 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16281 /* enum: reserved value - do not use (may indicate alternative interpretation
16284 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RESERVED 0x0
16288 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16291 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16292 /* enum: TX PD firmware with approximately Siena-compatible behaviour
16295 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16297 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16299 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16303 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16304 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16308 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16310 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16311 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16312 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16314 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_DPDK 0xa
16316 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16319 #define MC_CMD_GET_CAPABILITIES_V7_OUT_HW_CAPABILITIES_LEN 4
16322 #define MC_CMD_GET_CAPABILITIES_V7_OUT_LICENSE_CAPABILITIES_LEN 4
16325 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS2_LEN 4
16327 #define MC_CMD_GET_CAPABILITIES_V7_OUT_TX_TSO_V2_LBN 0
16339 #define MC_CMD_GET_CAPABILITIES_V7_OUT_RX_CUT_THROUGH_LBN 4
16441 #define MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff
16443 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe
16445 #define MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_ASSIGNED 0xfd
16452 #define MC_CMD_GET_CAPABILITIES_V7_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16460 /* MC_CMD_GET_CAPABILITIES_V7_OUT_ACCESS_NOT_PERMITTED 0xff */
16462 /* MC_CMD_GET_CAPABILITIES_V7_OUT_PF_NOT_PRESENT 0xfe */
16463 /* Number of VIs available for external ports 0-3. For devices with more than
16469 #define MC_CMD_GET_CAPABILITIES_V7_OUT_NUM_VIS_PER_PORT_NUM 4
16488 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
16493 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
16496 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_8K 0x0
16497 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
16498 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_16K 0x1
16499 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
16500 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VI_WINDOW_MODE_64K 0x2
16502 * (SF-115995-SW) in the present configuration of firmware and port mode.
16507 * (SF-115995-SW) in the present configuration of firmware and port mode.
16513 * hold at least this many 64-bit stats values, if they wish to receive all
16520 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
16523 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FILTER_ACTION_MARK_MAX_LEN 4
16533 #define MC_CMD_GET_CAPABILITIES_V7_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
16537 #define MC_CMD_GET_CAPABILITIES_V7_OUT_FLAGS3_LEN 4
16539 #define MC_CMD_GET_CAPABILITIES_V7_OUT_WOL_ETHERWAKE_LBN 0
16551 #define MC_CMD_GET_CAPABILITIES_V7_OUT_VDPA_SUPPORTED_LBN 4
16596 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_OFST 0
16597 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS1_LEN 4
16598 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VPORT_RECONFIGURE_OFST 0
16601 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_OFST 0
16602 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_STRIPING_LBN 4
16604 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_QUERY_OFST 0
16607 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
16610 #define MC_CMD_GET_CAPABILITIES_V8_OUT_DRV_ATTACH_PREBOOT_OFST 0
16613 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_FORCE_EVENT_MERGING_OFST 0
16616 #define MC_CMD_GET_CAPABILITIES_V8_OUT_SET_MAC_ENHANCED_OFST 0
16619 #define MC_CMD_GET_CAPABILITIES_V8_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
16622 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
16625 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
16628 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ADDITIONAL_RSS_MODES_OFST 0
16631 #define MC_CMD_GET_CAPABILITIES_V8_OUT_QBB_OFST 0
16634 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
16637 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_RSS_LIMITED_OFST 0
16640 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PACKED_STREAM_OFST 0
16643 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_INCLUDE_FCS_OFST 0
16646 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_VLAN_INSERTION_OFST 0
16649 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_VLAN_STRIPPING_OFST 0
16652 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_OFST 0
16655 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_0_OFST 0
16658 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_PREFIX_LEN_14_OFST 0
16661 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_TIMESTAMP_OFST 0
16664 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_BATCHING_OFST 0
16667 #define MC_CMD_GET_CAPABILITIES_V8_OUT_MCAST_FILTER_CHAINING_OFST 0
16670 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PM_AND_RXDP_COUNTERS_OFST 0
16673 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DISABLE_SCATTER_OFST 0
16676 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
16679 #define MC_CMD_GET_CAPABILITIES_V8_OUT_EVB_OFST 0
16682 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VXLAN_NVGRE_OFST 0
16686 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_DPCPU_FW_ID_OFST 4
16689 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP 0x0
16691 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_LOW_LATENCY 0x1
16693 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_PACKED_STREAM 0x2
16695 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_RULES_ENGINE 0x5
16697 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_DPDK 0x6
16699 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_BIST 0x10a
16701 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
16703 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
16705 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
16706 /* enum: RXDP Test firmware image 4 */
16707 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
16709 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_BACKPRESSURE 0x105
16711 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
16713 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
16715 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
16717 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
16719 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXDP_TEST_FW_SLOW 0x10c
16724 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP 0x0
16726 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_LOW_LATENCY 0x1
16728 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_HIGH_PACKET_RATE 0x3
16730 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_RULES_ENGINE 0x5
16732 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_DPDK 0x6
16734 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_BIST 0x12d
16736 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
16738 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
16740 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXDP_TEST_FW_CSR 0x103
16744 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_REV_LBN 0
16748 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
16749 /* enum: reserved value - do not use (may indicate alternative interpretation
16752 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RESERVED 0x0
16756 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
16759 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16760 /* enum: RX PD firmware with approximately Siena-compatible behaviour
16763 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
16765 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
16767 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_VSWITCH 0x3
16771 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16773 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
16775 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
16779 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
16781 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
16782 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16783 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_L3XUDP 0x9
16785 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_DPDK 0xa
16787 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16791 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
16795 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_REV_LBN 0
16799 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
16800 /* enum: reserved value - do not use (may indicate alternative interpretation
16803 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RESERVED 0x0
16807 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
16810 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
16811 /* enum: TX PD firmware with approximately Siena-compatible behaviour
16814 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
16816 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
16818 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_VSWITCH 0x3
16822 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
16823 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
16827 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
16829 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
16830 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
16831 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_L3XUDP 0x9
16833 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_DPDK 0xa
16835 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
16838 #define MC_CMD_GET_CAPABILITIES_V8_OUT_HW_CAPABILITIES_LEN 4
16841 #define MC_CMD_GET_CAPABILITIES_V8_OUT_LICENSE_CAPABILITIES_LEN 4
16844 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS2_LEN 4
16846 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TX_TSO_V2_LBN 0
16858 #define MC_CMD_GET_CAPABILITIES_V8_OUT_RX_CUT_THROUGH_LBN 4
16960 #define MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff
16962 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe
16964 #define MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_ASSIGNED 0xfd
16971 #define MC_CMD_GET_CAPABILITIES_V8_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
16979 /* MC_CMD_GET_CAPABILITIES_V8_OUT_ACCESS_NOT_PERMITTED 0xff */
16981 /* MC_CMD_GET_CAPABILITIES_V8_OUT_PF_NOT_PRESENT 0xfe */
16982 /* Number of VIs available for external ports 0-3. For devices with more than
16988 #define MC_CMD_GET_CAPABILITIES_V8_OUT_NUM_VIS_PER_PORT_NUM 4
17007 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17012 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17015 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_8K 0x0
17016 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17017 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_16K 0x1
17018 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17019 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VI_WINDOW_MODE_64K 0x2
17021 * (SF-115995-SW) in the present configuration of firmware and port mode.
17026 * (SF-115995-SW) in the present configuration of firmware and port mode.
17032 * hold at least this many 64-bit stats values, if they wish to receive all
17039 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17042 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17052 #define MC_CMD_GET_CAPABILITIES_V8_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17056 #define MC_CMD_GET_CAPABILITIES_V8_OUT_FLAGS3_LEN 4
17058 #define MC_CMD_GET_CAPABILITIES_V8_OUT_WOL_ETHERWAKE_LBN 0
17070 #define MC_CMD_GET_CAPABILITIES_V8_OUT_VDPA_SUPPORTED_LBN 4
17111 /* These bits are reserved for communicating test-specific capabilities to
17112 * host-side test software. All production drivers should treat this field as
17118 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_LO_LEN 4
17122 #define MC_CMD_GET_CAPABILITIES_V8_OUT_TEST_RESERVED_HI_LEN 4
17129 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_OFST 0
17130 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS1_LEN 4
17131 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VPORT_RECONFIGURE_OFST 0
17134 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_OFST 0
17135 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_STRIPING_LBN 4
17137 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_QUERY_OFST 0
17140 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17143 #define MC_CMD_GET_CAPABILITIES_V9_OUT_DRV_ATTACH_PREBOOT_OFST 0
17146 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17149 #define MC_CMD_GET_CAPABILITIES_V9_OUT_SET_MAC_ENHANCED_OFST 0
17152 #define MC_CMD_GET_CAPABILITIES_V9_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17155 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17158 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17161 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ADDITIONAL_RSS_MODES_OFST 0
17164 #define MC_CMD_GET_CAPABILITIES_V9_OUT_QBB_OFST 0
17167 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17170 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_RSS_LIMITED_OFST 0
17173 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PACKED_STREAM_OFST 0
17176 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_INCLUDE_FCS_OFST 0
17179 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_VLAN_INSERTION_OFST 0
17182 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_VLAN_STRIPPING_OFST 0
17185 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_OFST 0
17188 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_0_OFST 0
17191 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_PREFIX_LEN_14_OFST 0
17194 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_TIMESTAMP_OFST 0
17197 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_BATCHING_OFST 0
17200 #define MC_CMD_GET_CAPABILITIES_V9_OUT_MCAST_FILTER_CHAINING_OFST 0
17203 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17206 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DISABLE_SCATTER_OFST 0
17209 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17212 #define MC_CMD_GET_CAPABILITIES_V9_OUT_EVB_OFST 0
17215 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VXLAN_NVGRE_OFST 0
17219 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_DPCPU_FW_ID_OFST 4
17222 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP 0x0
17224 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_LOW_LATENCY 0x1
17226 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_PACKED_STREAM 0x2
17228 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_RULES_ENGINE 0x5
17230 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_DPDK 0x6
17232 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_BIST 0x10a
17234 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17236 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17238 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17239 /* enum: RXDP Test firmware image 4 */
17240 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17242 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_BACKPRESSURE 0x105
17244 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17246 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17248 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17250 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17252 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXDP_TEST_FW_SLOW 0x10c
17257 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP 0x0
17259 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_LOW_LATENCY 0x1
17261 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_HIGH_PACKET_RATE 0x3
17263 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_RULES_ENGINE 0x5
17265 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_DPDK 0x6
17267 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_BIST 0x12d
17269 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17271 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17273 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXDP_TEST_FW_CSR 0x103
17277 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_REV_LBN 0
17281 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17282 /* enum: reserved value - do not use (may indicate alternative interpretation
17285 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RESERVED 0x0
17289 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17292 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17293 /* enum: RX PD firmware with approximately Siena-compatible behaviour
17296 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17298 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17300 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17304 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17306 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17308 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17312 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17314 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17315 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17316 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17318 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_DPDK 0xa
17320 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17324 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17328 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_REV_LBN 0
17332 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17333 /* enum: reserved value - do not use (may indicate alternative interpretation
17336 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RESERVED 0x0
17340 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17343 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17344 /* enum: TX PD firmware with approximately Siena-compatible behaviour
17347 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17349 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17351 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17355 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17356 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17360 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17362 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17363 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17364 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17366 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_DPDK 0xa
17368 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17371 #define MC_CMD_GET_CAPABILITIES_V9_OUT_HW_CAPABILITIES_LEN 4
17374 #define MC_CMD_GET_CAPABILITIES_V9_OUT_LICENSE_CAPABILITIES_LEN 4
17377 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS2_LEN 4
17379 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TX_TSO_V2_LBN 0
17391 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RX_CUT_THROUGH_LBN 4
17493 #define MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff
17495 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe
17497 #define MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_ASSIGNED 0xfd
17504 #define MC_CMD_GET_CAPABILITIES_V9_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
17512 /* MC_CMD_GET_CAPABILITIES_V9_OUT_ACCESS_NOT_PERMITTED 0xff */
17514 /* MC_CMD_GET_CAPABILITIES_V9_OUT_PF_NOT_PRESENT 0xfe */
17515 /* Number of VIs available for external ports 0-3. For devices with more than
17521 #define MC_CMD_GET_CAPABILITIES_V9_OUT_NUM_VIS_PER_PORT_NUM 4
17540 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
17545 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
17548 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_8K 0x0
17549 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
17550 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_16K 0x1
17551 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
17552 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VI_WINDOW_MODE_64K 0x2
17554 * (SF-115995-SW) in the present configuration of firmware and port mode.
17559 * (SF-115995-SW) in the present configuration of firmware and port mode.
17565 * hold at least this many 64-bit stats values, if they wish to receive all
17572 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
17575 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FILTER_ACTION_MARK_MAX_LEN 4
17585 #define MC_CMD_GET_CAPABILITIES_V9_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
17589 #define MC_CMD_GET_CAPABILITIES_V9_OUT_FLAGS3_LEN 4
17591 #define MC_CMD_GET_CAPABILITIES_V9_OUT_WOL_ETHERWAKE_LBN 0
17603 #define MC_CMD_GET_CAPABILITIES_V9_OUT_VDPA_SUPPORTED_LBN 4
17644 /* These bits are reserved for communicating test-specific capabilities to
17645 * host-side test software. All production drivers should treat this field as
17651 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_LO_LEN 4
17655 #define MC_CMD_GET_CAPABILITIES_V9_OUT_TEST_RESERVED_HI_LEN 4
17663 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
17669 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
17675 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
17676 /* The maximum number of queues that can be used by an RSS context in even-
17677 * spreading mode. In even-spreading mode the context has no indirection table
17681 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
17687 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_NUM_CONTEXTS_LEN 4
17692 #define MC_CMD_GET_CAPABILITIES_V9_OUT_RSS_TABLE_POOL_SIZE_LEN 4
17697 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_OFST 0
17698 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS1_LEN 4
17699 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VPORT_RECONFIGURE_OFST 0
17702 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_OFST 0
17703 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_STRIPING_LBN 4
17705 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_QUERY_OFST 0
17708 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
17711 #define MC_CMD_GET_CAPABILITIES_V10_OUT_DRV_ATTACH_PREBOOT_OFST 0
17714 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_FORCE_EVENT_MERGING_OFST 0
17717 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SET_MAC_ENHANCED_OFST 0
17720 …efine MC_CMD_GET_CAPABILITIES_V10_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
17723 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
17726 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
17729 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ADDITIONAL_RSS_MODES_OFST 0
17732 #define MC_CMD_GET_CAPABILITIES_V10_OUT_QBB_OFST 0
17735 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
17738 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_RSS_LIMITED_OFST 0
17741 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PACKED_STREAM_OFST 0
17744 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_INCLUDE_FCS_OFST 0
17747 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_VLAN_INSERTION_OFST 0
17750 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_VLAN_STRIPPING_OFST 0
17753 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_OFST 0
17756 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_0_OFST 0
17759 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_PREFIX_LEN_14_OFST 0
17762 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_TIMESTAMP_OFST 0
17765 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_BATCHING_OFST 0
17768 #define MC_CMD_GET_CAPABILITIES_V10_OUT_MCAST_FILTER_CHAINING_OFST 0
17771 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PM_AND_RXDP_COUNTERS_OFST 0
17774 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DISABLE_SCATTER_OFST 0
17777 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
17780 #define MC_CMD_GET_CAPABILITIES_V10_OUT_EVB_OFST 0
17783 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VXLAN_NVGRE_OFST 0
17787 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_DPCPU_FW_ID_OFST 4
17790 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP 0x0
17792 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_LOW_LATENCY 0x1
17794 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_PACKED_STREAM 0x2
17796 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_RULES_ENGINE 0x5
17798 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_DPDK 0x6
17800 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_BIST 0x10a
17802 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
17804 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
17806 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
17807 /* enum: RXDP Test firmware image 4 */
17808 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
17810 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_BACKPRESSURE 0x105
17812 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
17814 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
17816 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
17818 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
17820 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXDP_TEST_FW_SLOW 0x10c
17825 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP 0x0
17827 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_LOW_LATENCY 0x1
17829 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_HIGH_PACKET_RATE 0x3
17831 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_RULES_ENGINE 0x5
17833 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_DPDK 0x6
17835 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_BIST 0x12d
17837 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
17839 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
17841 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXDP_TEST_FW_CSR 0x103
17845 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_REV_LBN 0
17849 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
17850 /* enum: reserved value - do not use (may indicate alternative interpretation
17853 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RESERVED 0x0
17857 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
17860 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17861 /* enum: RX PD firmware with approximately Siena-compatible behaviour
17864 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
17866 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
17868 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_VSWITCH 0x3
17872 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17874 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
17876 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
17880 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
17882 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
17883 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17884 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_L3XUDP 0x9
17886 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_DPDK 0xa
17888 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17892 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
17896 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_REV_LBN 0
17900 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
17901 /* enum: reserved value - do not use (may indicate alternative interpretation
17904 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RESERVED 0x0
17908 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
17911 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
17912 /* enum: TX PD firmware with approximately Siena-compatible behaviour
17915 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
17917 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
17919 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_VSWITCH 0x3
17923 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
17924 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
17928 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
17930 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
17931 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
17932 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_L3XUDP 0x9
17934 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_DPDK 0xa
17936 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
17939 #define MC_CMD_GET_CAPABILITIES_V10_OUT_HW_CAPABILITIES_LEN 4
17942 #define MC_CMD_GET_CAPABILITIES_V10_OUT_LICENSE_CAPABILITIES_LEN 4
17945 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS2_LEN 4
17947 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TX_TSO_V2_LBN 0
17959 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RX_CUT_THROUGH_LBN 4
18061 #define MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff
18063 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe
18065 #define MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_ASSIGNED 0xfd
18072 #define MC_CMD_GET_CAPABILITIES_V10_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18080 /* MC_CMD_GET_CAPABILITIES_V10_OUT_ACCESS_NOT_PERMITTED 0xff */
18082 /* MC_CMD_GET_CAPABILITIES_V10_OUT_PF_NOT_PRESENT 0xfe */
18083 /* Number of VIs available for external ports 0-3. For devices with more than
18089 #define MC_CMD_GET_CAPABILITIES_V10_OUT_NUM_VIS_PER_PORT_NUM 4
18108 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18113 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18116 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_8K 0x0
18117 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18118 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_16K 0x1
18119 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18120 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VI_WINDOW_MODE_64K 0x2
18122 * (SF-115995-SW) in the present configuration of firmware and port mode.
18127 * (SF-115995-SW) in the present configuration of firmware and port mode.
18133 * hold at least this many 64-bit stats values, if they wish to receive all
18140 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18143 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18153 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18157 #define MC_CMD_GET_CAPABILITIES_V10_OUT_FLAGS3_LEN 4
18159 #define MC_CMD_GET_CAPABILITIES_V10_OUT_WOL_ETHERWAKE_LBN 0
18171 #define MC_CMD_GET_CAPABILITIES_V10_OUT_VDPA_SUPPORTED_LBN 4
18212 /* These bits are reserved for communicating test-specific capabilities to
18213 * host-side test software. All production drivers should treat this field as
18219 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_LO_LEN 4
18223 #define MC_CMD_GET_CAPABILITIES_V10_OUT_TEST_RESERVED_HI_LEN 4
18231 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18237 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18243 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18244 /* The maximum number of queues that can be used by an RSS context in even-
18245 * spreading mode. In even-spreading mode the context has no indirection table
18249 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18255 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_NUM_CONTEXTS_LEN 4
18260 #define MC_CMD_GET_CAPABILITIES_V10_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18268 #define MC_CMD_GET_CAPABILITIES_V10_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18274 #define MC_CMD_GET_CAPABILITIES_V10_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18279 #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_OFST 0
18280 #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS1_LEN 4
18281 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VPORT_RECONFIGURE_OFST 0
18284 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_OFST 0
18285 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_STRIPING_LBN 4
18287 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_QUERY_OFST 0
18290 #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
18293 #define MC_CMD_GET_CAPABILITIES_V11_OUT_DRV_ATTACH_PREBOOT_OFST 0
18296 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_FORCE_EVENT_MERGING_OFST 0
18299 #define MC_CMD_GET_CAPABILITIES_V11_OUT_SET_MAC_ENHANCED_OFST 0
18302 …efine MC_CMD_GET_CAPABILITIES_V11_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
18305 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
18308 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
18311 #define MC_CMD_GET_CAPABILITIES_V11_OUT_ADDITIONAL_RSS_MODES_OFST 0
18314 #define MC_CMD_GET_CAPABILITIES_V11_OUT_QBB_OFST 0
18317 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
18320 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_RSS_LIMITED_OFST 0
18323 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PACKED_STREAM_OFST 0
18326 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_INCLUDE_FCS_OFST 0
18329 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_VLAN_INSERTION_OFST 0
18332 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_VLAN_STRIPPING_OFST 0
18335 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_OFST 0
18338 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_0_OFST 0
18341 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_PREFIX_LEN_14_OFST 0
18344 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_TIMESTAMP_OFST 0
18347 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_BATCHING_OFST 0
18350 #define MC_CMD_GET_CAPABILITIES_V11_OUT_MCAST_FILTER_CHAINING_OFST 0
18353 #define MC_CMD_GET_CAPABILITIES_V11_OUT_PM_AND_RXDP_COUNTERS_OFST 0
18356 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DISABLE_SCATTER_OFST 0
18359 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
18362 #define MC_CMD_GET_CAPABILITIES_V11_OUT_EVB_OFST 0
18365 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VXLAN_NVGRE_OFST 0
18369 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_DPCPU_FW_ID_OFST 4
18372 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP 0x0
18374 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_LOW_LATENCY 0x1
18376 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_PACKED_STREAM 0x2
18378 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_RULES_ENGINE 0x5
18380 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_DPDK 0x6
18382 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_BIST 0x10a
18384 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
18386 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
18388 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
18389 /* enum: RXDP Test firmware image 4 */
18390 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
18392 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_BACKPRESSURE 0x105
18394 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
18396 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
18398 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
18400 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
18402 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXDP_TEST_FW_SLOW 0x10c
18407 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP 0x0
18409 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_LOW_LATENCY 0x1
18411 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_HIGH_PACKET_RATE 0x3
18413 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_RULES_ENGINE 0x5
18415 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_DPDK 0x6
18417 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_BIST 0x12d
18419 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
18421 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
18423 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXDP_TEST_FW_CSR 0x103
18427 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_REV_LBN 0
18431 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
18432 /* enum: reserved value - do not use (may indicate alternative interpretation
18435 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RESERVED 0x0
18439 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
18442 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18443 /* enum: RX PD firmware with approximately Siena-compatible behaviour
18446 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
18448 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
18450 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_VSWITCH 0x3
18454 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18456 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
18458 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
18462 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
18464 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
18465 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18466 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_L3XUDP 0x9
18468 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_DPDK 0xa
18470 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18474 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
18478 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_REV_LBN 0
18482 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
18483 /* enum: reserved value - do not use (may indicate alternative interpretation
18486 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RESERVED 0x0
18490 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
18493 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
18494 /* enum: TX PD firmware with approximately Siena-compatible behaviour
18497 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
18499 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
18501 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_VSWITCH 0x3
18505 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
18506 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
18510 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
18512 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
18513 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
18514 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_L3XUDP 0x9
18516 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_DPDK 0xa
18518 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
18521 #define MC_CMD_GET_CAPABILITIES_V11_OUT_HW_CAPABILITIES_LEN 4
18524 #define MC_CMD_GET_CAPABILITIES_V11_OUT_LICENSE_CAPABILITIES_LEN 4
18527 #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS2_LEN 4
18529 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TX_TSO_V2_LBN 0
18541 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RX_CUT_THROUGH_LBN 4
18643 #define MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff
18645 #define MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe
18647 #define MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_ASSIGNED 0xfd
18654 #define MC_CMD_GET_CAPABILITIES_V11_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
18662 /* MC_CMD_GET_CAPABILITIES_V11_OUT_ACCESS_NOT_PERMITTED 0xff */
18664 /* MC_CMD_GET_CAPABILITIES_V11_OUT_PF_NOT_PRESENT 0xfe */
18665 /* Number of VIs available for external ports 0-3. For devices with more than
18671 #define MC_CMD_GET_CAPABILITIES_V11_OUT_NUM_VIS_PER_PORT_NUM 4
18690 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
18695 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
18698 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_8K 0x0
18699 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
18700 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_16K 0x1
18701 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
18702 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VI_WINDOW_MODE_64K 0x2
18704 * (SF-115995-SW) in the present configuration of firmware and port mode.
18709 * (SF-115995-SW) in the present configuration of firmware and port mode.
18715 * hold at least this many 64-bit stats values, if they wish to receive all
18722 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
18725 #define MC_CMD_GET_CAPABILITIES_V11_OUT_FILTER_ACTION_MARK_MAX_LEN 4
18735 #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
18739 #define MC_CMD_GET_CAPABILITIES_V11_OUT_FLAGS3_LEN 4
18741 #define MC_CMD_GET_CAPABILITIES_V11_OUT_WOL_ETHERWAKE_LBN 0
18753 #define MC_CMD_GET_CAPABILITIES_V11_OUT_VDPA_SUPPORTED_LBN 4
18794 /* These bits are reserved for communicating test-specific capabilities to
18795 * host-side test software. All production drivers should treat this field as
18801 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_LO_LEN 4
18805 #define MC_CMD_GET_CAPABILITIES_V11_OUT_TEST_RESERVED_HI_LEN 4
18813 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
18819 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
18825 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
18826 /* The maximum number of queues that can be used by an RSS context in even-
18827 * spreading mode. In even-spreading mode the context has no indirection table
18831 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
18837 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_NUM_CONTEXTS_LEN 4
18842 #define MC_CMD_GET_CAPABILITIES_V11_OUT_RSS_TABLE_POOL_SIZE_LEN 4
18850 #define MC_CMD_GET_CAPABILITIES_V11_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
18856 #define MC_CMD_GET_CAPABILITIES_V11_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
18859 #define MC_CMD_GET_CAPABILITIES_V11_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
18864 #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_OFST 0
18865 #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS1_LEN 4
18866 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VPORT_RECONFIGURE_OFST 0
18869 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_OFST 0
18870 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_STRIPING_LBN 4
18872 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_QUERY_OFST 0
18875 #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_PORT_VLAN_RESTRICT_OFST 0
18878 #define MC_CMD_GET_CAPABILITIES_V12_OUT_DRV_ATTACH_PREBOOT_OFST 0
18881 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_FORCE_EVENT_MERGING_OFST 0
18884 #define MC_CMD_GET_CAPABILITIES_V12_OUT_SET_MAC_ENHANCED_OFST 0
18887 …efine MC_CMD_GET_CAPABILITIES_V12_OUT_UNKNOWN_UCAST_DST_FILTER_ALWAYS_MULTI_RECIPIENT_OFST 0
18890 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED_OFST 0
18893 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MAC_SECURITY_FILTERING_OFST 0
18896 #define MC_CMD_GET_CAPABILITIES_V12_OUT_ADDITIONAL_RSS_MODES_OFST 0
18899 #define MC_CMD_GET_CAPABILITIES_V12_OUT_QBB_OFST 0
18902 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_VAR_BUFFERS_OFST 0
18905 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_RSS_LIMITED_OFST 0
18908 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PACKED_STREAM_OFST 0
18911 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_INCLUDE_FCS_OFST 0
18914 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_VLAN_INSERTION_OFST 0
18917 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_VLAN_STRIPPING_OFST 0
18920 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_OFST 0
18923 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_0_OFST 0
18926 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_PREFIX_LEN_14_OFST 0
18929 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_TIMESTAMP_OFST 0
18932 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_BATCHING_OFST 0
18935 #define MC_CMD_GET_CAPABILITIES_V12_OUT_MCAST_FILTER_CHAINING_OFST 0
18938 #define MC_CMD_GET_CAPABILITIES_V12_OUT_PM_AND_RXDP_COUNTERS_OFST 0
18941 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DISABLE_SCATTER_OFST 0
18944 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_MCAST_UDP_LOOPBACK_OFST 0
18947 #define MC_CMD_GET_CAPABILITIES_V12_OUT_EVB_OFST 0
18950 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VXLAN_NVGRE_OFST 0
18954 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_DPCPU_FW_ID_OFST 4
18957 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP 0x0
18959 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_LOW_LATENCY 0x1
18961 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_PACKED_STREAM 0x2
18963 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_RULES_ENGINE 0x5
18965 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_DPDK 0x6
18967 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_BIST 0x10a
18969 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_CUT_THROUGH 0x101
18971 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD 0x102
18973 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_TO_MC_STORE_FORWARD_FIRST 0x103
18974 /* enum: RXDP Test firmware image 4 */
18975 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_EVERY_EVENT_BATCHABLE 0x104
18977 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_BACKPRESSURE 0x105
18979 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_PACKET_EDITS 0x106
18981 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_RX_HDR_SPLIT 0x107
18983 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DISABLE_DL 0x108
18985 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_DOORBELL_DELAY 0x10b
18987 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXDP_TEST_FW_SLOW 0x10c
18992 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP 0x0
18994 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_LOW_LATENCY 0x1
18996 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_HIGH_PACKET_RATE 0x3
18998 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_RULES_ENGINE 0x5
19000 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_DPDK 0x6
19002 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_BIST 0x12d
19004 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_TSO_EDIT 0x101
19006 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_PACKET_EDITS 0x102
19008 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXDP_TEST_FW_CSR 0x103
19012 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_REV_LBN 0
19016 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_VERSION_TYPE_WIDTH 4
19017 /* enum: reserved value - do not use (may indicate alternative interpretation
19020 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RESERVED 0x0
19024 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FIRST_PKT 0x1
19027 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
19028 /* enum: RX PD firmware with approximately Siena-compatible behaviour
19031 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT 0x2
19033 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_FULL_FEATURED 0x3
19035 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_VSWITCH 0x3
19039 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
19041 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LOW_LATENCY 0x5
19043 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_PACKED_STREAM 0x6
19047 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_LAYER2_PERF 0x7
19049 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_RULES_ENGINE 0x8
19050 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
19051 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_L3XUDP 0x9
19053 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_DPDK 0xa
19055 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
19059 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RXPD_FW_TYPE_TESTFW_ENCAP_PARSING_ONLY 0xf
19063 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_REV_LBN 0
19067 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_VERSION_TYPE_WIDTH 4
19068 /* enum: reserved value - do not use (may indicate alternative interpretation
19071 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RESERVED 0x0
19075 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FIRST_PKT 0x1
19078 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_TELEMETRY 0x1
19079 /* enum: TX PD firmware with approximately Siena-compatible behaviour
19082 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT 0x2
19084 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_FULL_FEATURED 0x3
19086 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_VSWITCH 0x3
19090 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_SIENA_COMPAT_PM 0x4
19091 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LOW_LATENCY 0x5 /* enum */
19095 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_LAYER2_PERF 0x7
19097 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_RULES_ENGINE 0x8
19098 /* enum: Custom firmware variant (see SF-119495-PD and bug69716) */
19099 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_L3XUDP 0x9
19101 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_DPDK 0xa
19103 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TXPD_FW_TYPE_TESTFW_GUE_PROTOTYPE 0xe
19106 #define MC_CMD_GET_CAPABILITIES_V12_OUT_HW_CAPABILITIES_LEN 4
19109 #define MC_CMD_GET_CAPABILITIES_V12_OUT_LICENSE_CAPABILITIES_LEN 4
19112 #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS2_LEN 4
19114 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TX_TSO_V2_LBN 0
19126 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RX_CUT_THROUGH_LBN 4
19228 #define MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff
19230 #define MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe
19232 #define MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_ASSIGNED 0xfd
19239 #define MC_CMD_GET_CAPABILITIES_V12_OUT_INCOMPATIBLE_ASSIGNMENT 0xfc
19247 /* MC_CMD_GET_CAPABILITIES_V12_OUT_ACCESS_NOT_PERMITTED 0xff */
19249 /* MC_CMD_GET_CAPABILITIES_V12_OUT_PF_NOT_PRESENT 0xfe */
19250 /* Number of VIs available for external ports 0-3. For devices with more than
19256 #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT_NUM 4
19275 * discover the VI to address mapping. Cut-through PIO (CTPIO) is not available
19280 /* enum: Each VI occupies 8k as on Huntington and Medford. PIO is at offset 4k.
19283 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_8K 0x0
19284 /* enum: Each VI occupies 16k. PIO is at offset 4k. CTPIO is at offset 12k. */
19285 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_16K 0x1
19286 /* enum: Each VI occupies 64k. PIO is at offset 4k. CTPIO is at offset 12k. */
19287 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VI_WINDOW_MODE_64K 0x2
19289 * (SF-115995-SW) in the present configuration of firmware and port mode.
19294 * (SF-115995-SW) in the present configuration of firmware and port mode.
19300 * hold at least this many 64-bit stats values, if they wish to receive all
19307 * will only be non-zero if MC_CMD_GET_CAPABILITIES/FILTER_ACTION_MARK is set.
19310 #define MC_CMD_GET_CAPABILITIES_V12_OUT_FILTER_ACTION_MARK_MAX_LEN 4
19320 #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_RX_BUFFER_SIZES_LEN 4
19324 #define MC_CMD_GET_CAPABILITIES_V12_OUT_FLAGS3_LEN 4
19326 #define MC_CMD_GET_CAPABILITIES_V12_OUT_WOL_ETHERWAKE_LBN 0
19338 #define MC_CMD_GET_CAPABILITIES_V12_OUT_VDPA_SUPPORTED_LBN 4
19379 /* These bits are reserved for communicating test-specific capabilities to
19380 * host-side test software. All production drivers should treat this field as
19386 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_LO_LEN 4
19390 #define MC_CMD_GET_CAPABILITIES_V12_OUT_TEST_RESERVED_HI_LEN 4
19398 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MIN_INDIRECTION_TABLE_SIZE_LEN 4
19404 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_TABLE_SIZE_LEN 4
19410 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_INDIRECTION_QUEUES_LEN 4
19411 /* The maximum number of queues that can be used by an RSS context in even-
19412 * spreading mode. In even-spreading mode the context has no indirection table
19416 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_MAX_EVEN_SPREADING_QUEUES_LEN 4
19422 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_NUM_CONTEXTS_LEN 4
19427 #define MC_CMD_GET_CAPABILITIES_V12_OUT_RSS_TABLE_POOL_SIZE_LEN 4
19435 #define MC_CMD_GET_CAPABILITIES_V12_OUT_SUPPORTED_QUEUE_SIZES_LEN 4
19441 #define MC_CMD_GET_CAPABILITIES_V12_OUT_GUARANTEED_QUEUE_SIZES_LEN 4
19444 #define MC_CMD_GET_CAPABILITIES_V12_OUT_INDIRECT_MAP_INDEX_COUNT_LEN 4
19445 /* Number of VIs available for external ports 4-7. Information for ports 0-3 is
19450 #define MC_CMD_GET_CAPABILITIES_V12_OUT_NUM_VIS_PER_PORT2_NUM 4
19457 #define MC_CMD_V2_EXTN 0x7f
19460 #define MC_CMD_V2_EXTN_IN_LEN 4
19462 #define MC_CMD_V2_EXTN_IN_EXTENDED_CMD_LBN 0
19475 #define MC_CMD_V2_EXTN_IN_MESSAGE_TYPE_WIDTH 4
19477 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_MC 0x0
19481 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_TSA 0x1
19483 * are used for low-level operations directed at the platform as a whole (e.g.
19488 #define MC_CMD_V2_EXTN_IN_MCDI_MESSAGE_TYPE_PLATFORM 0x2
19495 #define MC_CMD_LINK_PIOBUF 0x92
19503 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_OFST 0
19504 #define MC_CMD_LINK_PIOBUF_IN_PIOBUF_HANDLE_LEN 4
19506 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_OFST 4
19507 #define MC_CMD_LINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
19510 #define MC_CMD_LINK_PIOBUF_OUT_LEN 0
19517 #define MC_CMD_UNLINK_PIOBUF 0x93
19523 #define MC_CMD_UNLINK_PIOBUF_IN_LEN 4
19525 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_OFST 0
19526 #define MC_CMD_UNLINK_PIOBUF_IN_TXQ_INSTANCE_LEN 4
19529 #define MC_CMD_UNLINK_PIOBUF_OUT_LEN 0
19534 * allocate and initialise a v-switch.
19536 #define MC_CMD_VSWITCH_ALLOC 0x94
19543 /* The port to connect to the v-switch's upstream port. */
19544 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19545 #define MC_CMD_VSWITCH_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19546 /* The type of v-switch to create. */
19547 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_OFST 4
19548 #define MC_CMD_VSWITCH_ALLOC_IN_TYPE_LEN 4
19550 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VLAN 0x1
19552 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEB 0x2
19554 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_VEPA 0x3
19556 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_MUX 0x4
19558 #define MC_CMD_VSWITCH_ALLOC_IN_VSWITCH_TYPE_TEST 0x5
19559 /* Flags controlling v-port creation */
19561 #define MC_CMD_VSWITCH_ALLOC_IN_FLAGS_LEN 4
19563 #define MC_CMD_VSWITCH_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
19565 /* The number of VLAN tags to allow for attached v-ports. For VLAN aggregators,
19566 * this must be one or greated, and the attached v-ports must have exactly this
19567 * number of tags. For other v-switch types, this must be zero of greater, and
19568 * is an upper limit on the number of VLAN tags for attached v-ports. An error
19570 * v-ports with this number of tags.
19573 #define MC_CMD_VSWITCH_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
19576 #define MC_CMD_VSWITCH_ALLOC_OUT_LEN 0
19581 * de-allocate a v-switch.
19583 #define MC_CMD_VSWITCH_FREE 0x95
19589 #define MC_CMD_VSWITCH_FREE_IN_LEN 4
19590 /* The port to which the v-switch is connected. */
19591 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_OFST 0
19592 #define MC_CMD_VSWITCH_FREE_IN_UPSTREAM_PORT_ID_LEN 4
19595 #define MC_CMD_VSWITCH_FREE_OUT_LEN 0
19600 * allocate a v-port.
19602 #define MC_CMD_VPORT_ALLOC 0x96
19609 /* The port to which the v-switch is connected. */
19610 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19611 #define MC_CMD_VPORT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19612 /* The type of the new v-port. */
19613 #define MC_CMD_VPORT_ALLOC_IN_TYPE_OFST 4
19614 #define MC_CMD_VPORT_ALLOC_IN_TYPE_LEN 4
19616 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VLAN 0x1
19618 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEB 0x2
19620 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_VEPA 0x3
19621 /* enum: A normal v-port receives packets which match a specified MAC and/or
19624 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_NORMAL 0x4
19625 /* enum: An expansion v-port packets traffic which don't match any other
19626 * v-port.
19628 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_EXPANSION 0x5
19629 /* enum: An test v-port receives packets which match any filters installed by
19632 #define MC_CMD_VPORT_ALLOC_IN_VPORT_TYPE_TEST 0x6
19633 /* Flags controlling v-port creation */
19635 #define MC_CMD_VPORT_ALLOC_IN_FLAGS_LEN 4
19637 #define MC_CMD_VPORT_ALLOC_IN_FLAG_AUTO_PORT_LBN 0
19644 * v-switch.
19647 #define MC_CMD_VPORT_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
19650 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAGS_LEN 4
19652 #define MC_CMD_VPORT_ALLOC_IN_VLAN_TAG_0_LBN 0
19659 #define MC_CMD_VPORT_ALLOC_OUT_LEN 4
19660 /* The handle of the new v-port */
19661 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_OFST 0
19662 #define MC_CMD_VPORT_ALLOC_OUT_VPORT_ID_LEN 4
19667 * de-allocate a v-port.
19669 #define MC_CMD_VPORT_FREE 0x97
19675 #define MC_CMD_VPORT_FREE_IN_LEN 4
19676 /* The handle of the v-port */
19677 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_OFST 0
19678 #define MC_CMD_VPORT_FREE_IN_VPORT_ID_LEN 4
19681 #define MC_CMD_VPORT_FREE_OUT_LEN 0
19686 * allocate a v-adaptor.
19688 #define MC_CMD_VADAPTOR_ALLOC 0x98
19695 /* The port to connect to the v-adaptor's port. */
19696 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19697 #define MC_CMD_VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19698 /* Flags controlling v-adaptor creation */
19700 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAGS_LEN 4
19702 #define MC_CMD_VADAPTOR_ALLOC_IN_FLAG_AUTO_VADAPTOR_LBN 0
19709 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLANS_LEN 4
19712 #define MC_CMD_VADAPTOR_ALLOC_IN_NUM_VLAN_TAGS_LEN 4
19715 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAGS_LEN 4
19717 #define MC_CMD_VADAPTOR_ALLOC_IN_VLAN_TAG_0_LBN 0
19722 /* The MAC address to assign to this v-adaptor */
19726 #define MC_CMD_VADAPTOR_ALLOC_IN_AUTO_MAC 0x0
19729 #define MC_CMD_VADAPTOR_ALLOC_OUT_LEN 0
19734 * de-allocate a v-adaptor.
19736 #define MC_CMD_VADAPTOR_FREE 0x99
19742 #define MC_CMD_VADAPTOR_FREE_IN_LEN 4
19743 /* The port to which the v-adaptor is connected. */
19744 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_OFST 0
19745 #define MC_CMD_VADAPTOR_FREE_IN_UPSTREAM_PORT_ID_LEN 4
19748 #define MC_CMD_VADAPTOR_FREE_OUT_LEN 0
19753 * assign a new MAC address to a v-adaptor.
19755 #define MC_CMD_VADAPTOR_SET_MAC 0x5d
19762 /* The port to which the v-adaptor is connected. */
19763 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_OFST 0
19764 #define MC_CMD_VADAPTOR_SET_MAC_IN_UPSTREAM_PORT_ID_LEN 4
19765 /* The new MAC address to assign to this v-adaptor */
19766 #define MC_CMD_VADAPTOR_SET_MAC_IN_MACADDR_OFST 4
19770 #define MC_CMD_VADAPTOR_SET_MAC_OUT_LEN 0
19775 * read some config of v-adaptor.
19777 #define MC_CMD_VADAPTOR_QUERY 0x61
19783 #define MC_CMD_VADAPTOR_QUERY_IN_LEN 4
19784 /* The port to which the v-adaptor is connected. */
19785 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_OFST 0
19786 #define MC_CMD_VADAPTOR_QUERY_IN_UPSTREAM_PORT_ID_LEN 4
19791 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_OFST 0
19792 #define MC_CMD_VADAPTOR_QUERY_OUT_PORT_FLAGS_LEN 4
19793 /* The v-adaptor flags as defined at MC_CMD_VADAPTOR_ALLOC. */
19794 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_OFST 4
19795 #define MC_CMD_VADAPTOR_QUERY_OUT_VADAPTOR_FLAGS_LEN 4
19798 #define MC_CMD_VADAPTOR_QUERY_OUT_NUM_AVAILABLE_VLAN_TAGS_LEN 4
19805 #define MC_CMD_EVB_PORT_ASSIGN 0x9a
19813 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_OFST 0
19814 #define MC_CMD_EVB_PORT_ASSIGN_IN_PORT_ID_LEN 4
19816 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_OFST 4
19817 #define MC_CMD_EVB_PORT_ASSIGN_IN_FUNCTION_LEN 4
19818 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_OFST 4
19819 #define MC_CMD_EVB_PORT_ASSIGN_IN_PF_LBN 0
19821 #define MC_CMD_EVB_PORT_ASSIGN_IN_VF_OFST 4
19826 #define MC_CMD_EVB_PORT_ASSIGN_OUT_LEN 0
19833 #define MC_CMD_RSS_CONTEXT_ALLOC 0x9e
19841 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_OFST 0
19842 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_UPSTREAM_PORT_ID_LEN 4
19844 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_OFST 4
19845 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_LEN 4
19849 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EXCLUSIVE 0x0
19851 * queues, but the key and indirection table are pre-configured and may not be
19852 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19854 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_SHARED 0x1
19859 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_TYPE_EVEN_SPREADING 0x2
19864 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19871 #define MC_CMD_RSS_CONTEXT_ALLOC_IN_NUM_QUEUES_LEN 4
19876 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_OFST 0
19877 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_UPSTREAM_PORT_ID_LEN 4
19879 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_OFST 4
19880 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_LEN 4
19884 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EXCLUSIVE 0x0
19886 * queues, but the key and indirection table are pre-configured and may not be
19887 * changed. For this mode, NUM_QUEUES must 2, 4, 8, 16, 32 or 64.
19889 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_SHARED 0x1
19894 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_TYPE_EVEN_SPREADING 0x2
19899 * the indirection table will be in the range 0 to NUM_QUEUES-1. For even-
19906 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_NUM_QUEUES_LEN 4
19915 #define MC_CMD_RSS_CONTEXT_ALLOC_V2_IN_INDIRECTION_TABLE_SIZE_LEN 4
19918 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_LEN 4
19920 * host, although a value of 0xFFFFFFFF is guaranteed never to be a valid
19923 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_OFST 0
19924 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_LEN 4
19926 #define MC_CMD_RSS_CONTEXT_ALLOC_OUT_RSS_CONTEXT_ID_INVALID 0xffffffff
19933 #define MC_CMD_RSS_CONTEXT_FREE 0x9f
19939 #define MC_CMD_RSS_CONTEXT_FREE_IN_LEN 4
19941 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_OFST 0
19942 #define MC_CMD_RSS_CONTEXT_FREE_IN_RSS_CONTEXT_ID_LEN 4
19945 #define MC_CMD_RSS_CONTEXT_FREE_OUT_LEN 0
19952 #define MC_CMD_RSS_CONTEXT_SET_KEY 0xa0
19960 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19961 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19962 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19963 #define MC_CMD_RSS_CONTEXT_SET_KEY_IN_TOEPLITZ_KEY_OFST 4
19967 #define MC_CMD_RSS_CONTEXT_SET_KEY_OUT_LEN 0
19974 #define MC_CMD_RSS_CONTEXT_GET_KEY 0xa1
19980 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_LEN 4
19982 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_OFST 0
19983 #define MC_CMD_RSS_CONTEXT_GET_KEY_IN_RSS_CONTEXT_ID_LEN 4
19987 /* The 40-byte Toeplitz hash key (TBD endianness issues?) */
19988 #define MC_CMD_RSS_CONTEXT_GET_KEY_OUT_TOEPLITZ_KEY_OFST 4
19998 #define MC_CMD_RSS_CONTEXT_SET_TABLE 0xa2
20006 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
20007 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
20008 /* The 128-byte indirection table (1 byte per entry) */
20009 #define MC_CMD_RSS_CONTEXT_SET_TABLE_IN_INDIRECTION_TABLE_OFST 4
20013 #define MC_CMD_RSS_CONTEXT_SET_TABLE_OUT_LEN 0
20022 #define MC_CMD_RSS_CONTEXT_GET_TABLE 0xa3
20028 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_LEN 4
20030 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_OFST 0
20031 #define MC_CMD_RSS_CONTEXT_GET_TABLE_IN_RSS_CONTEXT_ID_LEN 4
20035 /* The 128-byte indirection table (1 byte per entry) */
20036 #define MC_CMD_RSS_CONTEXT_GET_TABLE_OUT_INDIRECTION_TABLE_OFST 4
20044 #define MC_CMD_RSS_CONTEXT_SET_FLAGS 0xe1
20052 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
20053 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
20056 * in this case, the MODE fields may be set to non-zero values, and will take
20060 * reject any attempt to set the FLAGS field to a value > 0xff with EINVAL. In
20066 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_OFST 4
20067 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_FLAGS_LEN 4
20068 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_OFST 4
20069 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV4_EN_LBN 0
20071 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV4_EN_OFST 4
20074 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_IPV6_EN_OFST 4
20077 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TOEPLITZ_TCPV6_EN_OFST 4
20080 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_OFST 4
20081 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_LBN 4
20082 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_RESERVED_WIDTH 4
20083 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_OFST 4
20085 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV4_RSS_MODE_WIDTH 4
20086 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_OFST 4
20088 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV4_RSS_MODE_WIDTH 4
20089 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_OFST 4
20091 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV4_RSS_MODE_WIDTH 4
20092 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_OFST 4
20094 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_TCP_IPV6_RSS_MODE_WIDTH 4
20095 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_OFST 4
20097 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_UDP_IPV6_RSS_MODE_WIDTH 4
20098 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_OFST 4
20100 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_IN_OTHER_IPV6_RSS_MODE_WIDTH 4
20103 #define MC_CMD_RSS_CONTEXT_SET_FLAGS_OUT_LEN 0
20110 #define MC_CMD_RSS_CONTEXT_GET_FLAGS 0xe2
20116 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_LEN 4
20118 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_OFST 0
20119 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_IN_RSS_CONTEXT_ID_LEN 4
20125 * capability), the _EN bits report the state. If any _MODE bits are non-zero
20128 * guaranteed to be consistent with the _EN flags for a freshly-allocated RSS
20136 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_OFST 4
20137 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_FLAGS_LEN 4
20138 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_OFST 4
20139 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV4_EN_LBN 0
20141 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV4_EN_OFST 4
20144 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_IPV6_EN_OFST 4
20147 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TOEPLITZ_TCPV6_EN_OFST 4
20150 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_OFST 4
20151 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_LBN 4
20152 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_RESERVED_WIDTH 4
20153 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_OFST 4
20155 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV4_RSS_MODE_WIDTH 4
20156 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_OFST 4
20158 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV4_RSS_MODE_WIDTH 4
20159 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_OFST 4
20161 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV4_RSS_MODE_WIDTH 4
20162 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_OFST 4
20164 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_TCP_IPV6_RSS_MODE_WIDTH 4
20165 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_OFST 4
20167 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_UDP_IPV6_RSS_MODE_WIDTH 4
20168 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_OFST 4
20170 #define MC_CMD_RSS_CONTEXT_GET_FLAGS_OUT_OTHER_IPV6_RSS_MODE_WIDTH 4
20175 * Add a MAC address to a v-port
20177 #define MC_CMD_VPORT_ADD_MAC_ADDRESS 0xa8
20184 /* The handle of the v-port */
20185 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_OFST 0
20186 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_VPORT_ID_LEN 4
20188 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_IN_MACADDR_OFST 4
20192 #define MC_CMD_VPORT_ADD_MAC_ADDRESS_OUT_LEN 0
20197 * Delete a MAC address from a v-port
20199 #define MC_CMD_VPORT_DEL_MAC_ADDRESS 0xa9
20206 /* The handle of the v-port */
20207 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_OFST 0
20208 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_VPORT_ID_LEN 4
20210 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_IN_MACADDR_OFST 4
20214 #define MC_CMD_VPORT_DEL_MAC_ADDRESS_OUT_LEN 0
20219 * Delete a MAC address from a v-port
20221 #define MC_CMD_VPORT_GET_MAC_ADDRESSES 0xaa
20227 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN 4
20228 /* The handle of the v-port */
20229 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_OFST 0
20230 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID_LEN 4
20233 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN 4
20236 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LEN(num) (4+6*(num))
20237 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_NUM(len) (((len)-4)/6)
20239 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_OFST 0
20240 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT_LEN 4
20242 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_OFST 4
20244 #define MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_MINNUM 0
20251 * Replace VLAN tags and/or MAC addresses of an existing v-port. If the v-port
20252 * has already been passed to another function (v-port's user), then that
20255 #define MC_CMD_VPORT_RECONFIGURE 0xeb
20262 /* The handle of the v-port */
20263 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_OFST 0
20264 #define MC_CMD_VPORT_RECONFIGURE_IN_VPORT_ID_LEN 4
20266 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_OFST 4
20267 #define MC_CMD_VPORT_RECONFIGURE_IN_FLAGS_LEN 4
20268 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_OFST 4
20269 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_VLAN_TAGS_LBN 0
20271 #define MC_CMD_VPORT_RECONFIGURE_IN_REPLACE_MACADDRS_OFST 4
20276 * v-switch.
20279 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_VLAN_TAGS_LEN 4
20282 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAGS_LEN 4
20284 #define MC_CMD_VPORT_RECONFIGURE_IN_VLAN_TAG_0_LBN 0
20291 #define MC_CMD_VPORT_RECONFIGURE_IN_NUM_MACADDRS_LEN 4
20295 #define MC_CMD_VPORT_RECONFIGURE_IN_MACADDRS_NUM 4
20298 #define MC_CMD_VPORT_RECONFIGURE_OUT_LEN 4
20299 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_OFST 0
20300 #define MC_CMD_VPORT_RECONFIGURE_OUT_FLAGS_LEN 4
20301 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_OFST 0
20302 #define MC_CMD_VPORT_RECONFIGURE_OUT_RESET_DONE_LBN 0
20310 #define MC_CMD_GET_CLOCK 0xac
20316 #define MC_CMD_GET_CLOCK_IN_LEN 0
20321 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_OFST 0
20322 #define MC_CMD_GET_CLOCK_OUT_SYS_FREQ_LEN 4
20324 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_OFST 4
20325 #define MC_CMD_GET_CLOCK_OUT_DPCPU_FREQ_LEN 4
20332 #define MC_CMD_TRIGGER_INTERRUPT 0xe3
20338 #define MC_CMD_TRIGGER_INTERRUPT_IN_LEN 4
20340 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_OFST 0
20341 #define MC_CMD_TRIGGER_INTERRUPT_IN_INTR_LEVEL_LEN 4
20344 #define MC_CMD_TRIGGER_INTERRUPT_OUT_LEN 0
20351 #define MC_CMD_DUMP_DO 0xe8
20358 #define MC_CMD_DUMP_DO_IN_PADDING_OFST 0
20359 #define MC_CMD_DUMP_DO_IN_PADDING_LEN 4
20360 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_OFST 4
20361 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_LEN 4
20362 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM 0x0 /* enum */
20363 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_DEFAULT 0x1 /* enum */
20365 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20366 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_NVRAM 0x1 /* enum */
20367 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY 0x2 /* enum */
20368 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_HOST_MEMORY_MLI 0x3 /* enum */
20369 #define MC_CMD_DUMP_DO_IN_DUMP_LOCATION_UART 0x4 /* enum */
20371 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20373 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20375 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20377 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20379 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20380 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_PAGE_SIZE 0x1000 /* enum */
20382 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20384 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20385 #define MC_CMD_DUMP_DO_IN_HOST_MEMORY_MLI_MAX_DEPTH 0x2 /* enum */
20387 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20391 #define MC_CMD_DUMP_DO_IN_UART_PORT_SRC 0xff
20393 #define MC_CMD_DUMP_DO_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20395 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_LEN 4
20396 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM 0x0 /* enum */
20397 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_NVRAM_DUMP_PARTITION 0x1 /* enum */
20399 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20403 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20405 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20407 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20409 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20411 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20413 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20415 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20417 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20419 #define MC_CMD_DUMP_DO_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20422 #define MC_CMD_DUMP_DO_OUT_LEN 4
20423 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_OFST 0
20424 #define MC_CMD_DUMP_DO_OUT_DUMPFILE_SIZE_LEN 4
20431 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED 0xe9
20438 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_OFST 0
20439 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_ENABLE_LEN 4
20440 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_OFST 4
20441 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_LEN 4
20445 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_TYPE_LEN 4
20449 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20451 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_NVRAM_OFFSET_LEN 4
20453 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20455 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20457 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20459 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20461 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20463 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_UART_PORT_LEN 4
20465 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPSPEC_SRC_CUSTOM_SIZE_LEN 4
20467 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_LEN 4
20471 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_TYPE_LEN 4
20475 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_PARTITION_TYPE_ID_LEN 4
20477 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_NVRAM_OFFSET_LEN 4
20479 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_LO_LEN 4
20481 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_ADDR_HI_LEN 4
20483 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_LO_LEN 4
20485 …e MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_ROOT_ADDR_HI_LEN 4
20487 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_HOST_MEMORY_MLI_DEPTH_LEN 4
20489 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_UART_PORT_LEN 4
20491 #define MC_CMD_DUMP_CONFIGURE_UNSOLICITED_IN_DUMPFILE_DST_CUSTOM_SIZE_LEN 4
20498 #define MC_CMD_GET_FUNCTION_INFO 0xec
20504 #define MC_CMD_GET_FUNCTION_INFO_IN_LEN 0
20508 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_OFST 0
20509 #define MC_CMD_GET_FUNCTION_INFO_OUT_PF_LEN 4
20510 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_OFST 4
20511 #define MC_CMD_GET_FUNCTION_INFO_OUT_VF_LEN 4
20515 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_OFST 0
20516 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_PF_LEN 4
20517 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_OFST 4
20518 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_VF_LEN 4
20523 #define MC_CMD_GET_FUNCTION_INFO_OUT_V2_INTF_LEN 4
20532 #define MC_CMD_ENABLE_OFFLINE_BIST 0xed
20538 #define MC_CMD_ENABLE_OFFLINE_BIST_IN_LEN 0
20541 #define MC_CMD_ENABLE_OFFLINE_BIST_OUT_LEN 0
20548 #define MC_CMD_KR_TUNE 0xf1
20554 #define MC_CMD_KR_TUNE_IN_LENMIN 4
20557 #define MC_CMD_KR_TUNE_IN_LEN(num) (4+4*(num))
20558 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_NUM(len) (((len)-4)/4)
20560 #define MC_CMD_KR_TUNE_IN_KR_TUNE_OP_OFST 0
20563 #define MC_CMD_KR_TUNE_IN_RXEQ_GET 0x0
20565 #define MC_CMD_KR_TUNE_IN_RXEQ_SET 0x1
20567 #define MC_CMD_KR_TUNE_IN_TXEQ_GET 0x2
20569 #define MC_CMD_KR_TUNE_IN_TXEQ_SET 0x3
20571 #define MC_CMD_KR_TUNE_IN_RECAL 0x4
20575 #define MC_CMD_KR_TUNE_IN_START_EYE_PLOT 0x5
20580 #define MC_CMD_KR_TUNE_IN_POLL_EYE_PLOT 0x6
20582 #define MC_CMD_KR_TUNE_IN_READ_FOM 0x7
20584 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_RUN 0x8
20586 #define MC_CMD_KR_TUNE_IN_LINK_TRAIN_CMD 0x9
20591 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_OFST 4
20592 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_LEN 4
20593 #define MC_CMD_KR_TUNE_IN_KR_TUNE_ARGS_MINNUM 0
20598 #define MC_CMD_KR_TUNE_OUT_LEN 0
20601 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_LEN 4
20603 #define MC_CMD_KR_TUNE_RXEQ_GET_IN_KR_TUNE_OP_OFST 0
20610 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LENMIN 4
20613 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LEN(num) (0+4*(num))
20614 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20616 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_OFST 0
20617 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LEN 4
20621 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_OFST 0
20622 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_ID_LBN 0
20624 /* enum: Attenuation (0-15, Huntington) */
20625 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_ATT 0x0
20626 /* enum: CTLE Boost (0-15, Huntington) */
20627 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST 0x1
20628 /* enum: Edge DFE Tap1 (Huntington - 0 - max negative, 64 - zero, 127 - max
20629 * positive, Medford - 0-31)
20631 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP1 0x2
20632 /* enum: Edge DFE Tap2 (Huntington - 0 - max negative, 32 - zero, 63 - max
20633 * positive, Medford - 0-31)
20635 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP2 0x3
20636 /* enum: Edge DFE Tap3 (Huntington - 0 - max negative, 32 - zero, 63 - max
20637 * positive, Medford - 0-16)
20639 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP3 0x4
20640 /* enum: Edge DFE Tap4 (Huntington - 0 - max negative, 32 - zero, 63 - max
20641 * positive, Medford - 0-16)
20643 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP4 0x5
20644 /* enum: Edge DFE Tap5 (Huntington - 0 - max negative, 32 - zero, 63 - max
20645 * positive, Medford - 0-16)
20647 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_TAP5 0x6
20648 /* enum: Edge DFE DLEV (0-128 for Medford) */
20649 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_EDFE_DLEV 0x7
20650 /* enum: Variable Gain Amplifier (0-15, Medford) */
20651 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_VGA 0x8
20652 /* enum: CTLE EQ Capacitor (0-15, Medford) */
20653 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQC 0x9
20654 /* enum: CTLE EQ Resistor (0-7, Medford) */
20655 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_EQRES 0xa
20656 /* enum: CTLE gain (0-31, Medford2) */
20657 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_GAIN 0xb
20658 /* enum: CTLE pole (0-31, Medford2) */
20659 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_POLE 0xc
20660 /* enum: CTLE peaking (0-31, Medford2) */
20661 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CTLE_PEAK 0xd
20662 /* enum: DFE Tap1 - even path (Medford2 - 6 bit signed (-29 - +29)) */
20663 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_EVEN 0xe
20664 /* enum: DFE Tap1 - odd path (Medford2 - 6 bit signed (-29 - +29)) */
20665 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_ODD 0xf
20666 /* enum: DFE Tap2 (Medford2 - 6 bit signed (-20 - +20)) */
20667 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2 0x10
20668 /* enum: DFE Tap3 (Medford2 - 6 bit signed (-20 - +20)) */
20669 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3 0x11
20670 /* enum: DFE Tap4 (Medford2 - 6 bit signed (-20 - +20)) */
20671 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4 0x12
20672 /* enum: DFE Tap5 (Medford2 - 6 bit signed (-24 - +24)) */
20673 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5 0x13
20674 /* enum: DFE Tap6 (Medford2 - 6 bit signed (-24 - +24)) */
20675 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP6 0x14
20676 /* enum: DFE Tap7 (Medford2 - 6 bit signed (-24 - +24)) */
20677 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP7 0x15
20678 /* enum: DFE Tap8 (Medford2 - 6 bit signed (-24 - +24)) */
20679 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP8 0x16
20680 /* enum: DFE Tap9 (Medford2 - 6 bit signed (-24 - +24)) */
20681 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP9 0x17
20682 /* enum: DFE Tap10 (Medford2 - 6 bit signed (-24 - +24)) */
20683 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP10 0x18
20684 /* enum: DFE Tap11 (Medford2 - 6 bit signed (-24 - +24)) */
20685 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP11 0x19
20686 /* enum: DFE Tap12 (Medford2 - 6 bit signed (-24 - +24)) */
20687 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP12 0x1a
20688 /* enum: I/Q clk offset (Medford2 - 4 bit signed (-5 - +5))) */
20689 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_IQ_OFF 0x1b
20691 * (Medford2 - 6 bit signed (-29 - +29)))
20693 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_EVEN 0x1c
20695 * (Medford2 - 6 bit signed (-29 - +29)))
20697 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1N_OFF_ODD 0x1d
20699 * (Medford2 - 6 bit signed (-29 - +29)))
20701 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_EVEN 0x1e
20703 * (Medford2 - 6 bit signed (-29 - +29)))
20705 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_H1P_OFF_ODD 0x1f
20707 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_PVT 0x20
20709 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_CDR_INTEG 0x21
20710 /* enum: CTLE Boost stages - retimer lineside (Medford2 with DS250x retimer - 4
20713 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_LS 0x22
20714 /* enum: DFE Tap1 - retimer lineside (Medford2 with DS250x retimer (-31 - 31))
20716 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_LS 0x23
20717 /* enum: DFE Tap2 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20719 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_LS 0x24
20720 /* enum: DFE Tap3 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20722 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_LS 0x25
20723 /* enum: DFE Tap4 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20725 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_LS 0x26
20726 /* enum: DFE Tap5 - retimer lineside (Medford2 with DS250x retimer (-15 - 15))
20728 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_LS 0x27
20729 /* enum: CTLE Boost stages - retimer hostside (Medford2 with DS250x retimer - 4
20732 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_BOOST_RT_HS 0x28
20733 /* enum: DFE Tap1 - retimer hostside (Medford2 with DS250x retimer (-31 - 31))
20735 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP1_RT_HS 0x29
20736 /* enum: DFE Tap2 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20738 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP2_RT_HS 0x2a
20739 /* enum: DFE Tap3 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20741 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP3_RT_HS 0x2b
20742 /* enum: DFE Tap4 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20744 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP4_RT_HS 0x2c
20745 /* enum: DFE Tap5 - retimer hostside (Medford2 with DS250x retimer (-15 - 15))
20747 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_DFE_TAP5_RT_HS 0x2d
20748 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_LANE_OFST 0
20751 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_0 0x0 /* enum */
20752 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_1 0x1 /* enum */
20753 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_2 0x2 /* enum */
20754 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_3 0x3 /* enum */
20755 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20756 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_AUTOCAL_OFST 0
20759 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_OFST 0
20761 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_RESERVED_WIDTH 4
20762 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20765 #define MC_CMD_KR_TUNE_RXEQ_GET_OUT_PARAM_CURRENT_OFST 0
20773 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_LEN(num) (4+4*(num))
20774 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20776 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_KR_TUNE_OP_OFST 0
20782 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_OFST 4
20783 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LEN 4
20787 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_OFST 4
20788 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_ID_LBN 0
20792 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_LANE_OFST 4
20797 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_AUTOCAL_OFST 4
20800 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_OFST 4
20802 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED_WIDTH 4
20803 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_PARAM_INITIAL_OFST 4
20806 #define MC_CMD_KR_TUNE_RXEQ_SET_IN_RESERVED2_OFST 4
20811 #define MC_CMD_KR_TUNE_RXEQ_SET_OUT_LEN 0
20814 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_LEN 4
20816 #define MC_CMD_KR_TUNE_TXEQ_GET_IN_KR_TUNE_OP_OFST 0
20823 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LENMIN 4
20826 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LEN(num) (0+4*(num))
20827 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_NUM(len) (((len)-0)/4)
20829 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_OFST 0
20830 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LEN 4
20834 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_OFST 0
20835 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_ID_LBN 0
20838 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV 0x0
20839 /* enum: De-Emphasis Tap1 Magnitude (0-7) (Huntington) */
20840 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_MODE 0x1
20841 /* enum: De-Emphasis Tap1 Fine */
20842 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_DTLEV 0x2
20843 /* enum: De-Emphasis Tap2 Magnitude (0-6) (Huntington) */
20844 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2 0x3
20845 /* enum: De-Emphasis Tap2 Fine (Huntington) */
20846 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_D2TLEV 0x4
20847 /* enum: Pre-Emphasis Magnitude (Huntington) */
20848 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_E 0x5
20849 /* enum: Pre-Emphasis Fine (Huntington) */
20850 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_ETLEV 0x6
20852 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_PREDRV_DLY 0x7
20854 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_SR_SET 0x8
20856 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_RT_SET 0x9
20858 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_FINE 0xa
20859 /* enum: Pre-cursor Tap (Medford, Medford2) */
20860 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV 0xb
20861 /* enum: Post-cursor Tap (Medford, Medford2) */
20862 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY 0xc
20864 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_LS 0xd
20865 /* enum: Pre-cursor Tap (Retimer Lineside) */
20866 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_LS 0xe
20867 /* enum: Post-cursor Tap (Retimer Lineside) */
20868 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_LS 0xf
20870 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TX_LEV_RT_HS 0x10
20871 /* enum: Pre-cursor Tap (Retimer Hostside) */
20872 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_ADV_RT_HS 0x11
20873 /* enum: Post-cursor Tap (Retimer Hostside) */
20874 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_TAP_DLY_RT_HS 0x12
20875 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_LANE_OFST 0
20878 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_0 0x0 /* enum */
20879 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_1 0x1 /* enum */
20880 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_2 0x2 /* enum */
20881 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_3 0x3 /* enum */
20882 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_LANE_ALL 0x4 /* enum */
20883 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED_OFST 0
20886 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_PARAM_INITIAL_OFST 0
20889 #define MC_CMD_KR_TUNE_TXEQ_GET_OUT_RESERVED2_OFST 0
20897 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_LEN(num) (4+4*(num))
20898 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_NUM(len) (((len)-4)/4)
20900 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_KR_TUNE_OP_OFST 0
20906 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_OFST 4
20907 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LEN 4
20911 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_OFST 4
20912 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_ID_LBN 0
20916 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_LANE_OFST 4
20921 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED_OFST 4
20924 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_PARAM_INITIAL_OFST 4
20927 #define MC_CMD_KR_TUNE_TXEQ_SET_IN_RESERVED2_OFST 4
20932 #define MC_CMD_KR_TUNE_TXEQ_SET_OUT_LEN 0
20935 #define MC_CMD_KR_TUNE_RECAL_IN_LEN 4
20937 #define MC_CMD_KR_TUNE_RECAL_IN_KR_TUNE_OP_OFST 0
20944 #define MC_CMD_KR_TUNE_RECAL_OUT_LEN 0
20949 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
20954 /* Port-relative lane to scan eye on */
20955 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_OFST 4
20956 #define MC_CMD_KR_TUNE_START_EYE_PLOT_IN_LANE_LEN 4
20961 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_KR_TUNE_OP_OFST 0
20966 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_OFST 4
20967 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_LEN 4
20968 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_OFST 4
20969 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_NUM_LBN 0
20971 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_LANE_ABS_REL_OFST 4
20976 #define MC_CMD_KR_TUNE_START_EYE_PLOT_V2_IN_BER_LEN 4
20979 #define MC_CMD_KR_TUNE_START_EYE_PLOT_OUT_LEN 0
20982 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_LEN 4
20984 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_IN_KR_TUNE_OP_OFST 0
20991 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LENMIN 0
20994 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_LEN(num) (0+2*(num))
20995 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_NUM(len) (((len)-0)/2)
20996 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_OFST 0
20998 #define MC_CMD_KR_TUNE_POLL_EYE_PLOT_OUT_SAMPLES_MINNUM 0
21005 #define MC_CMD_KR_TUNE_READ_FOM_IN_KR_TUNE_OP_OFST 0
21010 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_OFST 4
21011 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_LEN 4
21012 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_OFST 4
21013 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_NUM_LBN 0
21015 #define MC_CMD_KR_TUNE_READ_FOM_IN_LANE_ABS_REL_OFST 4
21020 #define MC_CMD_KR_TUNE_READ_FOM_OUT_LEN 4
21021 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_OFST 0
21022 #define MC_CMD_KR_TUNE_READ_FOM_OUT_FOM_LEN 4
21027 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_KR_TUNE_OP_OFST 0
21032 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_OFST 4
21033 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_RUN_LEN 4
21034 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_STOP 0x0 /* enum */
21035 #define MC_CMD_KR_TUNE_LINK_TRAIN_RUN_IN_START 0x1 /* enum */
21040 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_KR_TUNE_OP_OFST 0
21045 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_OFST 4
21046 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_LANE_LEN 4
21049 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_INITIALIZE_LEN 4
21052 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_PRESET_LEN 4
21053 /* C(-1) request */
21055 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CM1_LEN 4
21056 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_HOLD 0x0 /* enum */
21057 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_INCREMENT 0x1 /* enum */
21058 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_REQ_DECREMENT 0x2 /* enum */
21059 /* C(0) request */
21061 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_C0_LEN 4
21066 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_IN_CP1_LEN 4
21072 /* C(-1) status */
21073 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_OFST 0
21074 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_STATUS_LEN 4
21075 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_NOT_UPDATED 0x0 /* enum */
21076 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_UPDATED 0x1 /* enum */
21077 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MINIMUM 0x2 /* enum */
21078 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_STATUS_MAXIMUM 0x3 /* enum */
21079 /* C(0) status */
21080 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_OFST 4
21081 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_STATUS_LEN 4
21086 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_STATUS_LEN 4
21089 /* C(-1) value */
21091 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CM1_VALUE_LEN 4
21092 /* C(0) value */
21094 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_C0_VALUE_LEN 4
21097 #define MC_CMD_KR_TUNE_LINK_TRAIN_CMD_OUT_CP1_VALUE_LEN 4
21103 * - not used for V3 licensing
21105 #define MC_CMD_LICENSING 0xf3
21111 #define MC_CMD_LICENSING_IN_LEN 4
21113 #define MC_CMD_LICENSING_IN_OP_OFST 0
21114 #define MC_CMD_LICENSING_IN_OP_LEN 4
21115 /* enum: re-read and apply licenses after a license key partition update; note
21116 * that this operation returns a zero-length response
21118 #define MC_CMD_LICENSING_IN_OP_UPDATE_LICENSE 0x0
21120 #define MC_CMD_LICENSING_IN_OP_GET_KEY_STATS 0x1
21125 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_OFST 0
21126 #define MC_CMD_LICENSING_OUT_VALID_APP_KEYS_LEN 4
21130 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_OFST 4
21131 #define MC_CMD_LICENSING_OUT_INVALID_APP_KEYS_LEN 4
21134 #define MC_CMD_LICENSING_OUT_BLACKLISTED_APP_KEYS_LEN 4
21137 #define MC_CMD_LICENSING_OUT_UNVERIFIABLE_APP_KEYS_LEN 4
21141 #define MC_CMD_LICENSING_OUT_WRONG_NODE_APP_KEYS_LEN 4
21146 #define MC_CMD_LICENSING_OUT_LICENSING_STATE_LEN 4
21147 /* licensing subsystem self-test report (for manftest) */
21149 #define MC_CMD_LICENSING_OUT_LICENSING_SELF_TEST_LEN 4
21150 /* enum: licensing subsystem self-test failed */
21151 #define MC_CMD_LICENSING_OUT_SELF_TEST_FAIL 0x0
21152 /* enum: licensing subsystem self-test passed */
21153 #define MC_CMD_LICENSING_OUT_SELF_TEST_PASS 0x1
21159 * - V3 licensing (Medford)
21161 #define MC_CMD_LICENSING_V3 0xd0
21167 #define MC_CMD_LICENSING_V3_IN_LEN 4
21169 #define MC_CMD_LICENSING_V3_IN_OP_OFST 0
21170 #define MC_CMD_LICENSING_V3_IN_OP_LEN 4
21171 /* enum: re-read and apply licenses after a license key partition update; note
21172 * that this operation returns a zero-length response
21174 #define MC_CMD_LICENSING_V3_IN_OP_UPDATE_LICENSE 0x0
21178 #define MC_CMD_LICENSING_V3_IN_OP_REPORT_LICENSE 0x1
21183 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_OFST 0
21184 #define MC_CMD_LICENSING_V3_OUT_VALID_KEYS_LEN 4
21188 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_OFST 4
21189 #define MC_CMD_LICENSING_V3_OUT_INVALID_KEYS_LEN 4
21192 #define MC_CMD_LICENSING_V3_OUT_UNVERIFIABLE_KEYS_LEN 4
21195 #define MC_CMD_LICENSING_V3_OUT_WRONG_NODE_KEYS_LEN 4
21200 #define MC_CMD_LICENSING_V3_OUT_LICENSING_STATE_LEN 4
21201 /* licensing subsystem self-test report (for manftest) */
21203 #define MC_CMD_LICENSING_V3_OUT_LICENSING_SELF_TEST_LEN 4
21204 /* enum: licensing subsystem self-test failed */
21205 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_FAIL 0x0
21206 /* enum: licensing subsystem self-test passed */
21207 #define MC_CMD_LICENSING_V3_OUT_SELF_TEST_PASS 0x1
21212 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_LO_LEN 4
21216 #define MC_CMD_LICENSING_V3_OUT_LICENSED_APPS_HI_LEN 4
21226 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_LO_LEN 4
21230 #define MC_CMD_LICENSING_V3_OUT_LICENSED_FEATURES_HI_LEN 4
21244 #define MC_CMD_GET_LICENSED_APP_STATE 0xf5
21250 #define MC_CMD_GET_LICENSED_APP_STATE_IN_LEN 4
21252 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_OFST 0
21253 #define MC_CMD_GET_LICENSED_APP_STATE_IN_APP_ID_LEN 4
21256 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LEN 4
21258 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_OFST 0
21259 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_STATE_LEN 4
21261 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_NOT_LICENSED 0x0
21263 #define MC_CMD_GET_LICENSED_APP_STATE_OUT_LICENSED 0x1
21268 * Change configuration related to the parser-dispatcher subsystem.
21270 #define MC_CMD_SET_PARSER_DISP_CONFIG 0xf9
21279 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_LEN(num) (8+4*(num))
21280 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_NUM(len) (((len)-8)/4)
21282 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_OFST 0
21283 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TYPE_LEN 4
21284 /* enum: Per-TXQ enable for multicast UDP destination lookup for possible
21287 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_TXQ_MCAST_UDP_DST_LOOKUP_EN 0x0
21288 /* enum: Per-v-adaptor enable for suppression of self-transmissions on the
21292 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VADAPTOR_SUPPRESS_SELF_TX 0x1
21296 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_OFST 4
21297 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_ENTITY_LEN 4
21302 #define MC_CMD_SET_PARSER_DISP_CONFIG_IN_VALUE_LEN 4
21308 #define MC_CMD_SET_PARSER_DISP_CONFIG_OUT_LEN 0
21316 #define MC_CMD_GET_WORKAROUNDS 0x59
21325 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_OFST 0
21326 #define MC_CMD_GET_WORKAROUNDS_OUT_IMPLEMENTED_LEN 4
21327 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_OFST 4
21328 #define MC_CMD_GET_WORKAROUNDS_OUT_ENABLED_LEN 4
21330 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG17230 0x2
21332 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35388 0x4
21334 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG35017 0x8
21336 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG41750 0x10
21338 * - before adding code that queries this workaround, remember that there's
21342 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG42008 0x20
21344 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG26807 0x40
21346 #define MC_CMD_GET_WORKAROUNDS_OUT_BUG61265 0x80
21353 #define MC_CMD_PRIVILEGE_MASK 0x5a
21360 /* The target function to have its mask read or set e.g. PF 0 = 0xFFFF0000, VF
21361 * 1,3 = 0x00030001
21363 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_OFST 0
21364 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_LEN 4
21365 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_OFST 0
21366 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_PF_LBN 0
21368 #define MC_CMD_PRIVILEGE_MASK_IN_FUNCTION_VF_OFST 0
21371 #define MC_CMD_PRIVILEGE_MASK_IN_VF_NULL 0xffff /* enum */
21375 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_OFST 4
21376 #define MC_CMD_PRIVILEGE_MASK_IN_NEW_MASK_LEN 4
21377 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN 0x1 /* enum */
21378 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK 0x2 /* enum */
21379 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD 0x4 /* enum */
21380 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP 0x8 /* enum */
21381 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS 0x10 /* enum */
21383 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING 0x20
21384 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST 0x40 /* enum */
21385 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST 0x80 /* enum */
21386 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST 0x100 /* enum */
21387 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST 0x200 /* enum */
21388 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS 0x400 /* enum */
21392 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING_TX 0x800
21396 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_CHANGE_MAC 0x1000
21402 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_UNRESTRICTED_VLAN 0x2000
21406 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE 0x4000
21408 * administrator-level operations that are not allowed from the local host once
21410 * SF-117064-DG for background).
21412 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN_TSA_UNBOUND 0x8000
21413 /* enum: Control the Match-Action Engine if present. See mcdi_mae.yml. */
21414 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_MAE 0x10000
21418 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ALLOC_CLIENT 0x20000
21422 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_FUNC_DMA 0x40000
21424 * the device and to on-device DDR. It allows clients to use TX-DESC2CMPT-DESC
21425 * descriptors, and to use TX-SEG-DESC and TX-MEM2MEM-DESC with an address
21428 #define MC_CMD_PRIVILEGE_MASK_IN_GRP_ARBITRARY_DMA 0x80000
21432 #define MC_CMD_PRIVILEGE_MASK_IN_DO_CHANGE 0x80000000
21435 #define MC_CMD_PRIVILEGE_MASK_OUT_LEN 4
21437 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_OFST 0
21438 #define MC_CMD_PRIVILEGE_MASK_OUT_OLD_MASK_LEN 4
21445 #define MC_CMD_LINK_STATE_MODE 0x5c
21453 * e.g. VF 1,3 = 0x00030001
21455 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_OFST 0
21456 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_LEN 4
21457 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_OFST 0
21458 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_PF_LBN 0
21460 #define MC_CMD_LINK_STATE_MODE_IN_FUNCTION_VF_OFST 0
21464 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_OFST 4
21465 #define MC_CMD_LINK_STATE_MODE_IN_NEW_MODE_LEN 4
21466 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_AUTO 0x0 /* enum */
21467 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_UP 0x1 /* enum */
21468 #define MC_CMD_LINK_STATE_MODE_IN_LINK_STATE_DOWN 0x2 /* enum */
21471 #define MC_CMD_LINK_STATE_MODE_IN_DO_NOT_CHANGE 0xffffffff
21474 #define MC_CMD_LINK_STATE_MODE_OUT_LEN 4
21475 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_OFST 0
21476 #define MC_CMD_LINK_STATE_MODE_OUT_OLD_MODE_LEN 4
21479 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_LEN 4
21481 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_OFST 0
21484 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_VXLAN_UDP_PORT 0x12b5
21486 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_IANA_GENEVE_UDP_PORT 0x17c1
21487 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_UDP_PORT_LBN 0
21493 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_VXLAN 0x0
21495 #define TUNNEL_ENCAP_UDP_PORT_ENTRY_GENEVE 0x1
21503 * parser-dispatcher will attempt to parse traffic on these ports as tunnel
21508 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS 0x117
21514 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LENMIN 4
21517 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_LEN(num) (4+4*(num))
21518 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_NUM(len) (((len)-4)/4)
21520 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_FLAGS_OFST 0
21522 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_OFST 0
21523 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_UNLOADING_LBN 0
21531 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_OFST 4
21532 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_LEN 4
21533 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_IN_ENTRIES_MINNUM 0
21540 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_FLAGS_OFST 0
21542 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_OFST 0
21543 #define MC_CMD_SET_TUNNEL_ENCAP_UDP_PORTS_OUT_RESETTING_LBN 0
21556 #define MC_CMD_SET_EVQ_TMR 0x120
21563 /* Function-relative queue instance */
21564 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_OFST 0
21565 #define MC_CMD_SET_EVQ_TMR_IN_INSTANCE_LEN 4
21567 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_OFST 4
21568 #define MC_CMD_SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS_LEN 4
21571 #define MC_CMD_SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS_LEN 4
21574 #define MC_CMD_SET_EVQ_TMR_IN_TMR_MODE_LEN 4
21575 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS 0x0 /* enum */
21576 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START 0x1 /* enum */
21577 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START 0x2 /* enum */
21578 #define MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF 0x3 /* enum */
21583 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_OFST 0
21584 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_LOAD_ACT_NS_LEN 4
21586 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_OFST 4
21587 #define MC_CMD_SET_EVQ_TMR_OUT_TMR_RELOAD_ACT_NS_LEN 4
21594 #define MC_CMD_GET_EVQ_TMR_PROPERTIES 0x122
21600 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_IN_LEN 0
21605 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_OFST 0
21606 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_FLAGS_LEN 4
21612 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_OFST 4
21613 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_NS_PER_COUNT_LEN 4
21618 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_MAX_COUNT_LEN 4
21624 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_TMR_REG_STEP_LEN 4
21629 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_MAX_NS_LEN 4
21634 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_MCDI_TMR_STEP_NS_LEN 4
21642 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_NS_PER_COUNT_LEN 4
21648 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_MAX_COUNT_LEN 4
21655 #define MC_CMD_GET_EVQ_TMR_PROPERTIES_OUT_BUG35388_TMR_STEP_LEN 4
21661 * be found within XN-200418-TC.
21663 #define CLIENT_HANDLE_LEN 4
21664 #define CLIENT_HANDLE_OPAQUE_OFST 0
21665 #define CLIENT_HANDLE_OPAQUE_LEN 4
21667 #define CLIENT_HANDLE_NULL 0xffffffff
21669 #define CLIENT_HANDLE_SELF 0xfffffffe
21670 #define CLIENT_HANDLE_OPAQUE_LBN 0
21675 /* The instance of the scheduler. Refer to XN-200389-AW (snic/hnic) and
21676 * XN-200425-TC (cdx) for the location of these schedulers in the hardware.
21678 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_OFST 0
21680 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_A 0x0 /* enum */
21681 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_A 0x1 /* enum */
21682 #define SCHED_CREDIT_CHECK_RESULT_HUB_B 0x2 /* enum */
21683 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_C 0x3 /* enum */
21684 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_TX 0x4 /* enum */
21685 #define SCHED_CREDIT_CHECK_RESULT_HUB_HOST_D 0x5 /* enum */
21686 #define SCHED_CREDIT_CHECK_RESULT_HUB_REPLAY 0x6 /* enum */
21687 #define SCHED_CREDIT_CHECK_RESULT_DMAC_H2C 0x7 /* enum */
21688 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_B 0x8 /* enum */
21689 #define SCHED_CREDIT_CHECK_RESULT_HUB_NET_REPLAY 0x9 /* enum */
21690 #define SCHED_CREDIT_CHECK_RESULT_ADAPTER_C2H_C 0xa /* enum */
21691 #define SCHED_CREDIT_CHECK_RESULT_A2_H2C_C 0xb /* enum */
21692 #define SCHED_CREDIT_CHECK_RESULT_A3_SOFT_ADAPTOR_C 0xc /* enum */
21693 #define SCHED_CREDIT_CHECK_RESULT_A4_DPU_WRITE_C 0xd /* enum */
21694 #define SCHED_CREDIT_CHECK_RESULT_JRC_RRU 0xe /* enum */
21695 #define SCHED_CREDIT_CHECK_RESULT_CDM_SINK 0xf /* enum */
21696 #define SCHED_CREDIT_CHECK_RESULT_PCIE_SINK 0x10 /* enum */
21697 #define SCHED_CREDIT_CHECK_RESULT_UPORT_SINK 0x11 /* enum */
21698 #define SCHED_CREDIT_CHECK_RESULT_PSX_SINK 0x12 /* enum */
21699 #define SCHED_CREDIT_CHECK_RESULT_A5_DPU_READ_C 0x13 /* enum */
21700 #define SCHED_CREDIT_CHECK_RESULT_SCHED_INSTANCE_LBN 0
21706 #define SCHED_CREDIT_CHECK_RESULT_DEST 0x0
21708 #define SCHED_CREDIT_CHECK_RESULT_SOURCE 0x1
21710 * SF-120268-TC)
21712 #define SCHED_CREDIT_CHECK_RESULT_DEST_CREDIT1 0x2
21715 /* Level of node in scheduler hierarchy (level 0 is the bottom of the
21723 #define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_OFST 4
21724 #define SCHED_CREDIT_CHECK_RESULT_NODE_INDEX_LEN 4
21729 #define SCHED_CREDIT_CHECK_RESULT_EXPECTED_CREDITS_LEN 4
21734 #define SCHED_CREDIT_CHECK_RESULT_ACTUAL_CREDITS_LEN 4
21743 #define MC_CMD_GET_DESC_ADDR_INFO 0x1b7
21749 #define MC_CMD_GET_DESC_ADDR_INFO_IN_LEN 0
21752 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_LEN 4
21753 /* The type of mapping; see SF-nnnnnn-xx (EF100 driver writer's guide, once
21756 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_OFST 0
21757 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_TYPE_LEN 4
21759 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_FLAT 0x0
21763 #define MC_CMD_GET_DESC_ADDR_INFO_OUT_MAPPING_REGIONED 0x1
21770 #define MC_CMD_GET_DESC_ADDR_REGIONS 0x1b8
21776 #define MC_CMD_GET_DESC_ADDR_REGIONS_IN_LEN 0
21782 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_LEN(num) (0+32*(num))
21783 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_NUM(len) (((len)-0)/32)
21787 #define MC_CMD_GET_DESC_ADDR_REGIONS_OUT_REGIONS_OFST 0
21798 #define MC_CMD_SET_DESC_ADDR_REGIONS 0x1b9
21808 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_NUM(len) (((len)-8)/8)
21813 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_OFST 0
21814 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_SET_REGION_MASK_LEN 4
21816 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_OFST 4
21817 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_RSVD_LEN 4
21826 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_LO_LEN 4
21830 #define MC_CMD_SET_DESC_ADDR_REGIONS_IN_TRGT_ADDR_BASE_HI_LEN 4
21838 #define MC_CMD_SET_DESC_ADDR_REGIONS_OUT_LEN 0
21852 #define MC_CMD_CLIENT_CMD 0x1ba
21858 #define MC_CMD_CLIENT_CMD_IN_LEN 4
21860 #define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_OFST 0
21861 #define MC_CMD_CLIENT_CMD_IN_CLIENT_ID_LEN 4
21864 #define MC_CMD_CLIENT_CMD_OUT_LEN 0
21871 * unit. See also MC_CMD_CLIENT_CMD. See XN-200265-TC for background, concepts
21873 * clients". The newly-created client is a child of the client which sent this
21878 #define MC_CMD_CLIENT_ALLOC 0x1bb
21884 #define MC_CMD_CLIENT_ALLOC_IN_LEN 0
21887 #define MC_CMD_CLIENT_ALLOC_OUT_LEN 4
21889 #define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_OFST 0
21890 #define MC_CMD_CLIENT_ALLOC_OUT_CLIENT_ID_LEN 4
21899 #define MC_CMD_CLIENT_FREE 0x1bc
21905 #define MC_CMD_CLIENT_FREE_IN_LEN 4
21909 #define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_OFST 0
21910 #define MC_CMD_CLIENT_FREE_IN_CLIENT_ID_LEN 4
21913 #define MC_CMD_CLIENT_FREE_OUT_LEN 0
21923 * created are then owned by the user-client. Only the VI owner can call this
21927 #define MC_CMD_SET_VI_USER 0x1be
21934 /* Function-relative VI number to modify. */
21935 #define MC_CMD_SET_VI_USER_IN_INSTANCE_OFST 0
21936 #define MC_CMD_SET_VI_USER_IN_INSTANCE_LEN 4
21941 #define MC_CMD_SET_VI_USER_IN_CLIENT_ID_OFST 4
21942 #define MC_CMD_SET_VI_USER_IN_CLIENT_ID_LEN 4
21945 #define MC_CMD_SET_VI_USER_OUT_LEN 0
21980 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES 0x1c4
21986 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_LEN 4
21991 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
21992 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
21995 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LENMIN 0
21998 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_LEN(num) (0+6*(num))
21999 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_NUM(len) (((len)-0)/6)
22001 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_OFST 0
22003 #define MC_CMD_GET_CLIENT_MAC_ADDRESSES_OUT_MAC_ADDRS_MINNUM 0
22014 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES 0x1c5
22020 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LENMIN 4
22023 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_LEN(num) (4+6*(num))
22024 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_NUM(len) (((len)-4)/6)
22026 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_OFST 0
22027 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_CLIENT_HANDLE_LEN 4
22029 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_OFST 4
22031 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_IN_MAC_ADDRS_MINNUM 0
22036 #define MC_CMD_SET_CLIENT_MAC_ADDRESSES_OUT_LEN 0
22047 #define MC_CMD_CHECK_SCHEDULER_CREDITS 0x1c8
22055 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_OFST 0
22056 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_FLAGS_LEN 4
22057 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_OFST 0
22058 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_REPORT_ALL_LBN 0
22061 * into pages. This field specifies which (0-indexed) page to request. A
22062 * request with PAGE=0 will snapshot the results, and subsequent requests with
22063 * PAGE>0 will return data from the most recent snapshot. The GENERATION field
22067 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_OFST 4
22068 #define MC_CMD_CHECK_SCHEDULER_CREDITS_IN_PAGE_LEN 4
22075 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_NUM(len) (((len)-16)/16)
22077 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_OFST 0
22078 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_TOTAL_RESULTS_LEN 4
22080 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_OFST 4
22081 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_NUM_PAGES_LEN 4
22084 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_THIS_PAGE_LEN 4
22085 /* Result generation count. Incremented any time a request is made with PAGE=0.
22088 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_GENERATION_LEN 4
22092 #define MC_CMD_CHECK_SCHEDULER_CREDITS_OUT_RESULTS_MINNUM 0
22101 #define MC_CMD_VIRTIO_GET_FEATURES 0x168
22107 #define MC_CMD_VIRTIO_GET_FEATURES_IN_LEN 4
22111 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_OFST 0
22112 #define MC_CMD_VIRTIO_GET_FEATURES_IN_DEVICE_ID_LEN 4
22114 #define MC_CMD_VIRTIO_GET_FEATURES_IN_RESERVED 0x0
22116 #define MC_CMD_VIRTIO_GET_FEATURES_IN_NET 0x1
22118 #define MC_CMD_VIRTIO_GET_FEATURES_IN_BLOCK 0x2
22124 * specification ( https://docs.oasis-
22125 * open.org/virtio/virtio/v1.1/csprd01/virtio-v1.1-csprd01.pdf )
22127 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_OFST 0
22129 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_OFST 0
22130 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LEN 4
22131 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_LO_LBN 0
22133 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_OFST 4
22134 #define MC_CMD_VIRTIO_GET_FEATURES_OUT_FEATURES_HI_LEN 4
22145 #define MC_CMD_VIRTIO_TEST_FEATURES 0x169
22155 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_OFST 0
22156 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_DEVICE_ID_LEN 4
22159 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_OFST 4
22160 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_RESERVED_LEN 4
22167 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_LO_LEN 4
22171 #define MC_CMD_VIRTIO_TEST_FEATURES_IN_FEATURES_HI_LEN 4
22176 #define MC_CMD_VIRTIO_TEST_FEATURES_OUT_LEN 0
22186 #define MC_CMD_VIRTIO_INIT_QUEUE 0x16a
22196 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_QUEUE_TYPE_OFST 0
22199 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_RXQ 0x0
22201 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NET_TXQ 0x1
22203 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_BLOCK 0x2
22212 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_VF_NULL 0xffff
22213 /* Desired instance. This is the function-local index of the associated VI, not
22216 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_OFST 4
22217 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INSTANCE_LEN 4
22220 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_SIZE_LEN 4
22223 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FLAGS_LEN 4
22225 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USE_PASID_LBN 0
22231 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_LO_LEN 4
22235 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_DESC_TBL_ADDR_HI_LEN 4
22242 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_LO_LEN 4
22246 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_AVAIL_RING_ADDR_HI_LEN 4
22253 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_LO_LEN 4
22257 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_USED_RING_ADDR_HI_LEN 4
22264 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_PASID_LEN 4
22271 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_NO_VECTOR 0xffff
22276 * the features returned from MC_CMD_VIRTIO_GET_FEATURES. Features are per-
22283 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_LO_LEN 4
22287 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_FEATURES_HI_LEN 4
22299 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_AVAIL_IDX_LEN 4
22302 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_PIDX_LEN 4
22310 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_USED_IDX_LEN 4
22313 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_INITIAL_CIDX_LEN 4
22319 #define MC_CMD_VIRTIO_INIT_QUEUE_REQ_MPORT_SELECTOR_LEN 4
22322 #define MC_CMD_VIRTIO_INIT_QUEUE_RESP_LEN 0
22329 #define MC_CMD_VIRTIO_FINI_QUEUE 0x16b
22337 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_QUEUE_TYPE_OFST 0
22349 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_VF_NULL 0xffff
22351 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_OFST 4
22352 #define MC_CMD_VIRTIO_FINI_QUEUE_REQ_INSTANCE_LEN 4
22357 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_OFST 0
22358 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_AVAIL_IDX_LEN 4
22360 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_OFST 0
22361 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_PIDX_LEN 4
22363 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_OFST 4
22364 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_USED_IDX_LEN 4
22366 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_OFST 4
22367 #define MC_CMD_VIRTIO_FINI_QUEUE_RESP_FINAL_CIDX_LEN 4
22375 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET 0x16c
22385 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_DEVICE_ID_OFST 0
22397 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_VF_NULL 0xffff
22399 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_OFST 4
22400 #define MC_CMD_VIRTIO_GET_DOORBELL_OFFSET_REQ_INSTANCE_LEN 4
22405 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_OFST 0
22406 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_RX_DBL_OFFSET_LEN 4
22408 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_OFST 4
22409 #define MC_CMD_VIRTIO_GET_NET_DOORBELL_OFFSET_RESP_TX_DBL_OFFSET_LEN 4
22412 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_LEN 4
22414 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_OFST 0
22415 #define MC_CMD_VIRTIO_GET_BLOCK_DOORBELL_OFFSET_RESP_DBL_OFFSET_LEN 4
22422 #define PCIE_FUNCTION_PF_OFST 0
22427 #define PCIE_FUNCTION_PF_ANY 0xfffe
22429 #define PCIE_FUNCTION_PF_NULL 0xffff
22430 #define PCIE_FUNCTION_PF_LBN 0
22438 #define PCIE_FUNCTION_VF_ANY 0xfffe
22442 #define PCIE_FUNCTION_VF_NULL 0xffff
22448 #define PCIE_FUNCTION_INTF_OFST 4
22449 #define PCIE_FUNCTION_INTF_LEN 4
22453 #define PCIE_FUNCTION_INTF_HOST 0x0
22457 #define PCIE_FUNCTION_INTF_AP 0x1
22469 #define MC_CMD_GET_CLIENT_HANDLE 0x1c3
22477 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_OFST 0
22478 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_LEN 4
22479 /* enum: Obtain a client handle for a PCIe function-type client. */
22480 #define MC_CMD_GET_CLIENT_HANDLE_IN_TYPE_FUNC 0x0
22481 /* PCIe Function ID (as struct PCIE_FUNCTION). Valid when TYPE==FUNC. Use: -
22482 * INTF=CALLER, PF=PF_NULL, VF=VF_NULL to refer to the calling function -
22484 * a sibling VF of the calling VF. - INTF=CALLER, PF=..., VF=VF_NULL to refer
22485 * to a PF on the calling interface - INTF=CALLER, PF=..., VF=... to refer to a
22486 * VF on the calling interface - INTF=..., PF=PF_NULL, VF=VF_NULL to refer to
22487 * the named interface itself - INTF=..., PF=..., VF=VF_NULL to refer to a PF
22488 * on a named interface - INTF=..., PF=..., VF=... to refer to a VF on a named
22494 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_OFST 4
22496 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_OFST 4
22497 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_LO_LEN 4
22501 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_HI_LEN 4
22507 #define MC_CMD_GET_CLIENT_HANDLE_IN_PCIE_FUNCTION_INTF_NULL 0xffffffff
22509 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_PF_OFST 4
22514 #define MC_CMD_GET_CLIENT_HANDLE_IN_FUNC_INTF_LEN 4
22517 #define MC_CMD_GET_CLIENT_HANDLE_OUT_LEN 4
22518 #define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_OFST 0
22519 #define MC_CMD_GET_CLIENT_HANDLE_OUT_HANDLE_LEN 4
22522 #define MAE_FIELD_FLAGS_LEN 4
22523 #define MAE_FIELD_FLAGS_FLAT_OFST 0
22524 #define MAE_FIELD_FLAGS_FLAT_LEN 4
22525 #define MAE_FIELD_FLAGS_SUPPORT_STATUS_OFST 0
22526 #define MAE_FIELD_FLAGS_SUPPORT_STATUS_LBN 0
22528 #define MAE_FIELD_FLAGS_MASK_AFFECTS_CLASS_OFST 0
22531 #define MAE_FIELD_FLAGS_MATCH_AFFECTS_CLASS_OFST 0
22534 #define MAE_FIELD_FLAGS_FLAT_LBN 0
22547 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
22548 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
22549 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
22551 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
22552 #define MAE_ENC_FIELD_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
22612 #define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_LEN 4
22616 #define MAE_ENC_FIELD_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
22628 #define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_LEN 4
22632 #define MAE_ENC_FIELD_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
22671 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_LBN 0
22690 #define MAE_ENC_FIELD_PAIRS_ENC_HAS_OVLAN_MASK_LBN 0
22706 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_LEN 4
22710 #define MAE_ENC_FIELD_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
22734 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_OFST 0
22735 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LEN 4
22736 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_LBN 0
22738 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_OFST 4
22739 #define MAE_FIELD_MASK_VALUE_PAIRS_INGRESS_MPORT_SELECTOR_MASK_LEN 4
22743 #define MAE_FIELD_MASK_VALUE_PAIRS_MARK_LEN 4
22747 #define MAE_FIELD_MASK_VALUE_PAIRS_MARK_MASK_LEN 4
22807 #define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_LEN 4
22811 #define MAE_FIELD_MASK_VALUE_PAIRS_SRC_IP4_BE_MASK_LEN 4
22823 #define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_LEN 4
22827 #define MAE_FIELD_MASK_VALUE_PAIRS_DST_IP4_BE_MASK_LEN 4
22867 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_LEN 4
22871 #define MAE_FIELD_MASK_VALUE_PAIRS_IP_FLAGS_BE_MASK_LEN 4
22899 #define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_LEN 4
22903 #define MAE_FIELD_MASK_VALUE_PAIRS_ENCAP_TYPE_MASK_LEN 4
22907 #define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_LEN 4
22911 #define MAE_FIELD_MASK_VALUE_PAIRS_OUTER_RULE_ID_MASK_LEN 4
22971 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_LEN 4
22975 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_SRC_IP4_BE_MASK_LEN 4
22987 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_LEN 4
22991 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_DST_IP4_BE_MASK_LEN 4
23027 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_LEN 4
23031 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_IP_FLAGS_BE_MASK_LEN 4
23051 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_LEN 4
23055 #define MAE_FIELD_MASK_VALUE_PAIRS_ENC_VNET_ID_BE_MASK_LEN 4
23061 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_OFST 0
23062 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LEN 4
23063 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_LBN 0
23065 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_OFST 4
23066 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_INGRESS_MPORT_SELECTOR_MASK_LEN 4
23070 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_LEN 4
23074 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_MARK_MASK_LEN 4
23134 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_LEN 4
23138 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_SRC_IP4_BE_MASK_LEN 4
23150 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_LEN 4
23154 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_DST_IP4_BE_MASK_LEN 4
23194 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_LEN 4
23198 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IP_FLAGS_BE_MASK_LEN 4
23226 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_LEN 4
23230 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENCAP_TYPE_MASK_LEN 4
23234 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_LEN 4
23238 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_OUTER_RULE_ID_MASK_LEN 4
23298 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_LEN 4
23302 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_SRC_IP4_BE_MASK_LEN 4
23314 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_LEN 4
23318 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_DST_IP4_BE_MASK_LEN 4
23354 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_LEN 4
23358 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_IP_FLAGS_BE_MASK_LEN 4
23378 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_LEN 4
23382 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_ENC_VNET_ID_BE_MASK_LEN 4
23386 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_LEN 4
23388 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_IS_IP_FRAG_LBN 0
23400 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_HAS_OVLAN_LBN 4
23420 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_FLAGS_MASK_LEN 4
23432 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_LEN 4
23436 #define MAE_FIELD_MASK_VALUE_PAIRS_V2_CT_MARK_MASK_LEN 4
23478 * 32-bits or within any NIC interface field that needs store the value
23480 * refer to m-ports.
23482 #define MAE_MPORT_SELECTOR_LEN 4
23483 /* Used to force the tools to output bitfield-style defines for this structure.
23485 #define MAE_MPORT_SELECTOR_FLAT_OFST 0
23486 #define MAE_MPORT_SELECTOR_FLAT_LEN 4
23487 /* enum: An m-port selector value that is guaranteed never to represent a real
23490 #define MAE_MPORT_SELECTOR_NULL 0x0
23491 /* enum: The m-port assigned to the calling client. */
23492 #define MAE_MPORT_SELECTOR_ASSIGNED 0x1000000
23493 #define MAE_MPORT_SELECTOR_TYPE_OFST 0
23497 #define MAE_MPORT_SELECTOR_TYPE_PPORT 0x2
23501 #define MAE_MPORT_SELECTOR_TYPE_FUNC 0x3
23503 #define MAE_MPORT_SELECTOR_TYPE_MPORT_ID 0x4
23504 /* enum: The MPORT assigned to a given PCIe function (see also FWRIVERHD-1108)
23506 #define MAE_MPORT_SELECTOR_TYPE_MH_FUNC 0x5
23508 #define MAE_MPORT_SELECTOR_TYPE_INVALID 0xff
23509 #define MAE_MPORT_SELECTOR_MPORT_ID_OFST 0
23510 #define MAE_MPORT_SELECTOR_MPORT_ID_LBN 0
23512 #define MAE_MPORT_SELECTOR_PPORT_ID_OFST 0
23513 #define MAE_MPORT_SELECTOR_PPORT_ID_LBN 0
23514 #define MAE_MPORT_SELECTOR_PPORT_ID_WIDTH 4
23515 #define MAE_MPORT_SELECTOR_FUNC_INTF_ID_OFST 0
23517 #define MAE_MPORT_SELECTOR_FUNC_INTF_ID_WIDTH 4
23518 #define MAE_MPORT_SELECTOR_HOST_PRIMARY 0x1 /* enum */
23519 #define MAE_MPORT_SELECTOR_NIC_EMBEDDED 0x2 /* enum */
23521 #define MAE_MPORT_SELECTOR_CALLER 0xf
23522 #define MAE_MPORT_SELECTOR_CALLER_INTF 0xf /* enum */
23523 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_OFST 0
23525 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_WIDTH 4
23526 #define MAE_MPORT_SELECTOR_FUNC_PF_ID_OFST 0
23529 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_OFST 0
23530 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_LBN 0
23533 #define MAE_MPORT_SELECTOR_FUNC_VF_ID_NULL 0xffff
23535 * client. - When used by a PF with VF_ID == VF_ID_NULL, the mport selector
23537 * clients use ASSIGNED to achieve this behaviour). - When used by a PF with
23539 * function. - When used by a VF with VF_ID == VF_ID_NULL, the mport selector
23540 * relates to the PF owning the calling function. - When used by a VF with
23542 * calling function. - Not meaningful used by a client that is not a PCIe
23545 #define MAE_MPORT_SELECTOR_FUNC_PF_ID_CALLER 0xff
23549 #define MAE_MPORT_SELECTOR_FUNC_MH_PF_ID_CALLER 0xf
23550 #define MAE_MPORT_SELECTOR_FLAT_LBN 0
23564 * cannot administer), and 4. Some could be implementation-specific and fail
23566 * SF-123581-TC section 4.3 for more details.
23570 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_OFST 0
23571 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LEN 4
23572 #define MAE_LINK_ENDPOINT_SELECTOR_MPORT_SELECTOR_LBN 0
23575 #define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_OFST 4
23576 #define MAE_LINK_ENDPOINT_SELECTOR_LINK_END_LEN 4
23582 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_OFST 0
23584 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_OFST 0
23585 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LEN 4
23586 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LO_LBN 0
23588 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_OFST 4
23589 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_HI_LEN 4
23592 /* enum: Set FLAT to this value to obtain backward-compatible behaviour in
23597 #define MAE_LINK_ENDPOINT_SELECTOR_MAE_LINK_ENDPOINT_COMPAT 0x0
23598 #define MAE_LINK_ENDPOINT_SELECTOR_FLAT_LBN 0
23604 * Describes capabilities of the MAE (Match-Action Engine)
23606 #define MC_CMD_MAE_GET_CAPS 0x140
23612 #define MC_CMD_MAE_GET_CAPS_IN_LEN 0
23620 #define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_OFST 0
23621 #define MC_CMD_MAE_GET_CAPS_OUT_MATCH_FIELD_COUNT_LEN 4
23622 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
23623 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
23624 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_OFST 4
23625 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_VXLAN_LBN 0
23627 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_NVGRE_OFST 4
23630 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_GENEVE_OFST 4
23633 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_TYPE_L2GRE_OFST 4
23638 #define MC_CMD_MAE_GET_CAPS_OUT_COUNTERS_LEN 4
23641 #define MC_CMD_MAE_GET_CAPS_OUT_AR_COUNTERS_LEN 4
23647 #define MC_CMD_MAE_GET_CAPS_OUT_COUNTER_LISTS_LEN 4
23650 #define MC_CMD_MAE_GET_CAPS_OUT_ENCAP_HEADER_LIMIT_LEN 4
23653 #define MC_CMD_MAE_GET_CAPS_OUT_RSVD_LEN 4
23656 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SETS_LEN 4
23659 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_SET_LISTS_LEN 4
23662 #define MC_CMD_MAE_GET_CAPS_OUT_OUTER_RULES_LEN 4
23665 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_RULES_LEN 4
23670 #define MC_CMD_MAE_GET_CAPS_OUT_ACTION_PRIOS_LEN 4
23675 #define MC_CMD_MAE_GET_CAPS_OUT_OUTER_PRIOS_LEN 4
23682 #define MC_CMD_MAE_GET_CAPS_OUT_API_VER_LEN 4
23690 #define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_OFST 0
23691 #define MC_CMD_MAE_GET_CAPS_V2_OUT_MATCH_FIELD_COUNT_LEN 4
23692 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
23693 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
23694 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_OFST 4
23695 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_VXLAN_LBN 0
23697 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_NVGRE_OFST 4
23700 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_GENEVE_OFST 4
23703 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_TYPE_L2GRE_OFST 4
23708 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTERS_LEN 4
23711 #define MC_CMD_MAE_GET_CAPS_V2_OUT_AR_COUNTERS_LEN 4
23717 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_LISTS_LEN 4
23720 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ENCAP_HEADER_LIMIT_LEN 4
23723 #define MC_CMD_MAE_GET_CAPS_V2_OUT_RSVD_LEN 4
23726 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SETS_LEN 4
23729 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_SET_LISTS_LEN 4
23732 #define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_RULES_LEN 4
23735 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_RULES_LEN 4
23740 #define MC_CMD_MAE_GET_CAPS_V2_OUT_ACTION_PRIOS_LEN 4
23745 #define MC_CMD_MAE_GET_CAPS_V2_OUT_OUTER_PRIOS_LEN 4
23752 #define MC_CMD_MAE_GET_CAPS_V2_OUT_API_VER_LEN 4
23756 * COUNTER_TYPES_SUPPORTED==0x1). See also
23760 #define MC_CMD_MAE_GET_CAPS_V2_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
23763 #define MC_CMD_MAE_GET_CAPS_V2_OUT_CT_COUNTERS_LEN 4
23771 #define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_OFST 0
23772 #define MC_CMD_MAE_GET_CAPS_V3_OUT_MATCH_FIELD_COUNT_LEN 4
23773 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_OFST 4
23774 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPES_SUPPORTED_LEN 4
23775 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_OFST 4
23776 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_VXLAN_LBN 0
23778 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_NVGRE_OFST 4
23781 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_GENEVE_OFST 4
23784 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_TYPE_L2GRE_OFST 4
23789 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTERS_LEN 4
23792 #define MC_CMD_MAE_GET_CAPS_V3_OUT_AR_COUNTERS_LEN 4
23798 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_LISTS_LEN 4
23801 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ENCAP_HEADER_LIMIT_LEN 4
23804 #define MC_CMD_MAE_GET_CAPS_V3_OUT_RSVD_LEN 4
23807 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SETS_LEN 4
23810 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_SET_LISTS_LEN 4
23813 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_RULES_LEN 4
23816 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_RULES_LEN 4
23821 #define MC_CMD_MAE_GET_CAPS_V3_OUT_ACTION_PRIOS_LEN 4
23826 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OUTER_PRIOS_LEN 4
23833 #define MC_CMD_MAE_GET_CAPS_V3_OUT_API_VER_LEN 4
23837 * COUNTER_TYPES_SUPPORTED==0x1). See also
23841 #define MC_CMD_MAE_GET_CAPS_V3_OUT_COUNTER_TYPES_SUPPORTED_LEN 4
23844 #define MC_CMD_MAE_GET_CAPS_V3_OUT_CT_COUNTERS_LEN 4
23847 #define MC_CMD_MAE_GET_CAPS_V3_OUT_OR_COUNTERS_LEN 4
23852 * Get a level of support for match fields when used in match-action rules
23854 #define MC_CMD_MAE_GET_AR_CAPS 0x141
23860 #define MC_CMD_MAE_GET_AR_CAPS_IN_LEN 0
23863 #define MC_CMD_MAE_GET_AR_CAPS_OUT_LENMIN 4
23866 #define MC_CMD_MAE_GET_AR_CAPS_OUT_LEN(num) (4+4*(num))
23867 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
23869 #define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_OFST 0
23870 #define MC_CMD_MAE_GET_AR_CAPS_OUT_COUNT_LEN 4
23875 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_OFST 4
23876 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_LEN 4
23877 #define MC_CMD_MAE_GET_AR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
23886 #define MC_CMD_MAE_GET_OR_CAPS 0x142
23892 #define MC_CMD_MAE_GET_OR_CAPS_IN_LEN 0
23895 #define MC_CMD_MAE_GET_OR_CAPS_OUT_LENMIN 4
23898 #define MC_CMD_MAE_GET_OR_CAPS_OUT_LEN(num) (4+4*(num))
23899 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_NUM(len) (((len)-4)/4)
23901 #define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_OFST 0
23902 #define MC_CMD_MAE_GET_OR_CAPS_OUT_COUNT_LEN 4
23904 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_OFST 4
23905 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_LEN 4
23906 #define MC_CMD_MAE_GET_OR_CAPS_OUT_FIELD_FLAGS_MINNUM 0
23913 * Allocate match-action-engine counters, which can be referenced in various
23916 #define MC_CMD_MAE_COUNTER_ALLOC 0x143
23924 #define MC_CMD_MAE_COUNTER_ALLOC_IN_LEN 4
23926 #define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_OFST 0
23927 #define MC_CMD_MAE_COUNTER_ALLOC_IN_REQUESTED_COUNT_LEN 4
23932 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_OFST 0
23933 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_REQUESTED_COUNT_LEN 4
23935 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_OFST 4
23936 #define MC_CMD_MAE_COUNTER_ALLOC_V2_IN_COUNTER_TYPE_LEN 4
23944 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_LEN(num) (8+4*(num))
23945 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NUM(len) (((len)-8)/4)
23950 * counts wrap from 0xffffffff to 1.
23952 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_OFST 0
23953 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_LEN 4
23954 /* enum: Generation counter 0 is reserved and unused. */
23955 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_GENERATION_COUNT_INVALID 0x0
23960 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_OFST 4
23961 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_COUNT_LEN 4
23964 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_LEN 4
23969 #define MC_CMD_MAE_COUNTER_ALLOC_OUT_COUNTER_ID_NULL 0xffffffff
23976 * Free match-action-engine counters
23978 #define MC_CMD_MAE_COUNTER_FREE 0x144
23989 #define MC_CMD_MAE_COUNTER_FREE_IN_LEN(num) (4+4*(num))
23990 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_NUM(len) (((len)-4)/4)
23992 #define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_OFST 0
23993 #define MC_CMD_MAE_COUNTER_FREE_IN_COUNTER_ID_COUNT_LEN 4
23995 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_OFST 4
23996 #define MC_CMD_MAE_COUNTER_FREE_IN_FREE_COUNTER_ID_LEN 4
24004 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_OFST 0
24005 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_ID_COUNT_LEN 4
24007 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_OFST 4
24008 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_FREE_COUNTER_ID_LEN 4
24014 #define MC_CMD_MAE_COUNTER_FREE_V2_IN_COUNTER_TYPE_LEN 4
24022 #define MC_CMD_MAE_COUNTER_FREE_OUT_LEN(num) (8+4*(num))
24023 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_NUM(len) (((len)-8)/4)
24035 #define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_OFST 0
24036 #define MC_CMD_MAE_COUNTER_FREE_OUT_GENERATION_COUNT_LEN 4
24042 #define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_OFST 4
24043 #define MC_CMD_MAE_COUNTER_FREE_OUT_COUNTER_ID_COUNT_LEN 4
24051 #define MC_CMD_MAE_COUNTER_FREE_OUT_FREED_COUNTER_ID_LEN 4
24067 #define MC_CMD_MAE_COUNTERS_STREAM_START 0x151
24073 * with COUNTER_TYPES_MASK=0x1 (i.e. AR counters only).
24077 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_QID_OFST 0
24083 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_OFST 4
24084 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_FLAGS_LEN 4
24085 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_OFST 4
24086 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_ZERO_SQUASH_DISABLE_LBN 0
24088 #define MC_CMD_MAE_COUNTERS_STREAM_START_IN_COUNTER_STALL_EN_OFST 4
24095 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_QID_OFST 0
24101 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_OFST 4
24102 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_FLAGS_LEN 4
24103 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_OFST 4
24104 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_ZERO_SQUASH_DISABLE_LBN 0
24106 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_STALL_EN_OFST 4
24111 * 0x3 requests both AR and CT counters. A value of zero is invalid. Counter
24119 #define MC_CMD_MAE_COUNTERS_STREAM_START_V2_IN_COUNTER_TYPES_MASK_LEN 4
24122 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_LEN 4
24123 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_OFST 0
24124 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_FLAGS_LEN 4
24125 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_OFST 0
24126 #define MC_CMD_MAE_COUNTERS_STREAM_START_OUT_USES_CREDITS_LBN 0
24134 #define MC_CMD_MAE_COUNTERS_STREAM_STOP 0x152
24142 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_IN_QID_OFST 0
24146 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_LEN 4
24153 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_OFST 0
24154 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_OUT_GENERATION_COUNT_LEN 4
24157 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LENMIN 4
24160 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_LEN(num) (0+4*(num))
24161 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_NUM(len) (((len)-0)/4)
24163 * MAE_COUNTER_TYPE_AR==0, this response is backwards-compatible with V1. The
24169 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_OFST 0
24170 #define MC_CMD_MAE_COUNTERS_STREAM_STOP_V2_OUT_GENERATION_COUNT_LEN 4
24183 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS 0x153
24189 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_LEN 4
24191 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_OFST 0
24192 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_IN_NUM_CREDITS_LEN 4
24195 #define MC_CMD_MAE_COUNTERS_STREAM_GIVE_CREDITS_OUT_LEN 0
24201 * header must be constructed as a valid packet with 0-length payload.
24207 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC 0x148
24213 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LENMIN 4
24216 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_LEN(num) (4+1*(num))
24217 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_NUM(len) (((len)-4)/1)
24218 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_OFST 0
24219 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_ENCAP_TYPE_LEN 4
24220 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_OFST 4
24222 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_IN_HDR_DATA_MINNUM 0
24227 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_LEN 4
24228 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_OFST 0
24229 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_LEN 4
24233 #define MC_CMD_MAE_ENCAP_HEADER_ALLOC_OUT_ENCAP_HEADER_ID_NULL 0xffffffff
24240 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE 0x149
24250 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_NUM(len) (((len)-8)/1)
24251 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_OFST 0
24252 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_EH_ID_LEN 4
24253 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_OFST 4
24254 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_ENCAP_TYPE_LEN 4
24257 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_IN_HDR_DATA_MINNUM 0
24262 #define MC_CMD_MAE_ENCAP_HEADER_UPDATE_OUT_LEN 0
24269 #define MC_CMD_MAE_ENCAP_HEADER_FREE 0x14a
24275 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LENMIN 4
24278 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_LEN(num) (0+4*(num))
24279 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_NUM(len) (((len)-0)/4)
24281 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_OFST 0
24282 #define MC_CMD_MAE_ENCAP_HEADER_FREE_IN_EH_ID_LEN 4
24288 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LENMIN 4
24291 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_LEN(num) (0+4*(num))
24292 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_NUM(len) (((len)-0)/4)
24294 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_OFST 0
24295 #define MC_CMD_MAE_ENCAP_HEADER_FREE_OUT_FREED_EH_ID_LEN 4
24309 #define MC_CMD_MAE_MAC_ADDR_ALLOC 0x15e
24317 #define MC_CMD_MAE_MAC_ADDR_ALLOC_IN_MAC_ADDR_OFST 0
24321 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_LEN 4
24322 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_OFST 0
24323 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_LEN 4
24327 #define MC_CMD_MAE_MAC_ADDR_ALLOC_OUT_MAC_ID_NULL 0xffffffff
24334 #define MC_CMD_MAE_MAC_ADDR_FREE 0x15f
24340 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LENMIN 4
24343 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_LEN(num) (0+4*(num))
24344 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_NUM(len) (((len)-0)/4)
24346 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_OFST 0
24347 #define MC_CMD_MAE_MAC_ADDR_FREE_IN_MAC_ID_LEN 4
24353 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LENMIN 4
24356 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_LEN(num) (0+4*(num))
24357 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_NUM(len) (((len)-0)/4)
24359 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_OFST 0
24360 #define MC_CMD_MAE_MAC_ADDR_FREE_OUT_FREED_MAC_ID_LEN 4
24373 #define MC_CMD_MAE_ACTION_SET_ALLOC 0x14d
24380 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_OFST 0
24381 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAGS_LEN 4
24382 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_OFST 0
24383 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_PUSH_LBN 0
24385 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_OFST 0
24386 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN_POP_LBN 4
24388 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DECAP_OFST 0
24391 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_OFST 0
24394 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_FLAG_OFST 0
24397 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_NAT_OFST 0
24400 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_DECR_IP_TTL_OFST 0
24403 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_SRC_MPORT_OFST 0
24406 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SUPPRESS_SELF_DELIVERY_OFST 0
24409 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_C_PL_OFST 0
24412 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_D_PL_OFST 0
24415 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0
24418 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DO_SET_NET_CHAN_OFST 0
24421 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_PLUGIN_OFST 0
24424 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_LACP_INC_L4_OFST 0
24428 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_VLAN0_TCI_BE_OFST 4
24439 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
24441 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_RSVD_LEN 4
24444 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_ENCAP_HEADER_ID_LEN 4
24445 /* An m-port selector identifying the m-port that the modified packet should be
24450 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DELIVER_LEN 4
24455 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_LIST_ID_LEN 4
24459 * it can supply a COUNTER_ID instead of allocating a single-element counter
24462 * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and
24466 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_COUNTER_ID_LEN 4
24470 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_MARK_VALUE_LEN 4
24473 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_SRC_MAC_ID_LEN 4
24476 #define MC_CMD_MAE_ACTION_SET_ALLOC_IN_DST_MAC_ID_LEN 4
24483 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_OFST 0
24484 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAGS_LEN 4
24485 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_OFST 0
24486 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_PUSH_LBN 0
24488 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_OFST 0
24489 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN_POP_LBN 4
24491 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DECAP_OFST 0
24494 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_OFST 0
24497 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_FLAG_OFST 0
24500 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_NAT_OFST 0
24503 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DECR_IP_TTL_OFST 0
24506 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_SRC_MPORT_OFST 0
24509 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SUPPRESS_SELF_DELIVERY_OFST 0
24512 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_C_PL_OFST 0
24515 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_D_PL_OFST 0
24518 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0
24521 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_SET_NET_CHAN_OFST 0
24524 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_PLUGIN_OFST 0
24527 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_LACP_INC_L4_OFST 0
24531 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_VLAN0_TCI_BE_OFST 4
24542 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
24544 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_RSVD_LEN 4
24547 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_ENCAP_HEADER_ID_LEN 4
24548 /* An m-port selector identifying the m-port that the modified packet should be
24553 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DELIVER_LEN 4
24558 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_LIST_ID_LEN 4
24562 * it can supply a COUNTER_ID instead of allocating a single-element counter
24565 * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and
24569 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_COUNTER_ID_LEN 4
24573 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_MARK_VALUE_LEN 4
24576 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_SRC_MAC_ID_LEN 4
24579 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DST_MAC_ID_LEN 4
24580 /* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
24582 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_REPORTED_SRC_MPORT_LEN 4
24583 /* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
24589 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_DSCP_ENCAP_COPY_LBN 0
24606 #define MC_CMD_MAE_ACTION_SET_ALLOC_V2_IN_DO_ECN_ENCAP_COPY_LBN 0
24629 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAGS_OFST 0
24630 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAGS_LEN 4
24631 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_OFST 0
24632 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_PUSH_LBN 0
24634 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_OFST 0
24635 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN_POP_LBN 4
24637 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DECAP_OFST 0
24640 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_OFST 0
24643 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_FLAG_OFST 0
24646 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_NAT_OFST 0
24649 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DECR_IP_TTL_OFST 0
24652 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_SRC_MPORT_OFST 0
24655 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SUPPRESS_SELF_DELIVERY_OFST 0
24658 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_C_PL_OFST 0
24661 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_D_PL_OFST 0
24664 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_REPLACE_RDP_OUT_HOST_CHAN_OFST 0
24667 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_SET_NET_CHAN_OFST 0
24670 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_PLUGIN_OFST 0
24673 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_LACP_INC_L4_OFST 0
24677 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_VLAN0_TCI_BE_OFST 4
24688 /* Reserved. Ignored by firmware. Should be set to zero or 0xffffffff. */
24690 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RSVD_LEN 4
24693 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_ENCAP_HEADER_ID_LEN 4
24694 /* An m-port selector identifying the m-port that the modified packet should be
24699 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DELIVER_LEN 4
24704 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_LIST_ID_LEN 4
24708 * it can supply a COUNTER_ID instead of allocating a single-element counter
24711 * is not valid to supply a non-NULL value for both COUNTER_LIST_ID and
24715 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_COUNTER_ID_LEN 4
24719 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_MARK_VALUE_LEN 4
24722 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_SRC_MAC_ID_LEN 4
24725 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DST_MAC_ID_LEN 4
24726 /* Source m-port ID to be reported for DO_SET_SRC_MPORT action. */
24728 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_REPORTED_SRC_MPORT_LEN 4
24729 /* Actions for modifying the Differentiated Services Code-Point (DSCP) bits
24735 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_DSCP_ENCAP_COPY_LBN 0
24752 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_DO_ECN_ENCAP_COPY_LBN 0
24773 #define MC_CMD_MAE_ACTION_SET_ALLOC_V3_IN_RDP_C_PL_LBN 0
24791 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_LEN 4
24796 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_OFST 0
24797 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_AS_ID_LEN 4
24800 #define MC_CMD_MAE_ACTION_SET_ALLOC_OUT_ACTION_SET_ID_NULL 0xffffffff
24806 #define MC_CMD_MAE_ACTION_SET_FREE 0x14e
24812 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LENMIN 4
24815 #define MC_CMD_MAE_ACTION_SET_FREE_IN_LEN(num) (0+4*(num))
24816 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_NUM(len) (((len)-0)/4)
24818 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_OFST 0
24819 #define MC_CMD_MAE_ACTION_SET_FREE_IN_AS_ID_LEN 4
24825 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LENMIN 4
24828 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_LEN(num) (0+4*(num))
24829 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_NUM(len) (((len)-0)/4)
24831 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_OFST 0
24832 #define MC_CMD_MAE_ACTION_SET_FREE_OUT_FREED_AS_ID_LEN 4
24846 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC 0x14f
24855 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_LEN(num) (4+4*(num))
24856 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_NUM(len) (((len)-4)/4)
24858 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_OFST 0
24859 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_COUNT_LEN 4
24869 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_OFST 4
24870 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_IN_AS_IDS_LEN 4
24876 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_LEN 4
24880 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_OFST 0
24881 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ASL_ID_LEN 4
24885 #define MC_CMD_MAE_ACTION_SET_LIST_ALLOC_OUT_ACTION_SET_LIST_ID_NULL 0xffffffff
24890 * Free match-action-engine redirect_lists
24892 #define MC_CMD_MAE_ACTION_SET_LIST_FREE 0x150
24898 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LENMIN 4
24901 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_LEN(num) (0+4*(num))
24902 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_NUM(len) (((len)-0)/4)
24904 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_OFST 0
24905 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_IN_ASL_ID_LEN 4
24911 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LENMIN 4
24914 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_LEN(num) (0+4*(num))
24915 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_NUM(len) (((len)-0)/4)
24917 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_OFST 0
24918 #define MC_CMD_MAE_ACTION_SET_LIST_FREE_OUT_FREED_ASL_ID_LEN 4
24930 #define MC_CMD_MAE_OUTER_RULE_INSERT 0x15a
24940 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_NUM(len) (((len)-16)/1)
24942 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_OFST 0
24943 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ENCAP_TYPE_LEN 4
24950 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_OFST 4
24951 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_PRIO_LEN 4
24954 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_LOOKUP_CONTROL_LEN 4
24956 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_DO_CT_LBN 0
24967 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_CT_TCP_FLAGS_INHIBIT_LBN 4
24977 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_ACTION_CONTROL_LEN 4
24982 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_COUNTER_ID_LEN 4
24986 #define MC_CMD_MAE_OUTER_RULE_INSERT_IN_FIELD_MATCH_CRITERIA_MINNUM 0
24991 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_LEN 4
24992 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_OFST 0
24993 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OR_ID_LEN 4
24996 #define MC_CMD_MAE_OUTER_RULE_INSERT_OUT_OUTER_RULE_ID_NULL 0xffffffff
25002 #define MC_CMD_MAE_OUTER_RULE_REMOVE 0x15b
25008 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LENMIN 4
25011 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_LEN(num) (0+4*(num))
25012 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_NUM(len) (((len)-0)/4)
25014 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_OFST 0
25015 #define MC_CMD_MAE_OUTER_RULE_REMOVE_IN_OR_ID_LEN 4
25021 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LENMIN 4
25024 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_LEN(num) (0+4*(num))
25025 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_NUM(len) (((len)-0)/4)
25027 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_OFST 0
25028 #define MC_CMD_MAE_OUTER_RULE_REMOVE_OUT_REMOVED_OR_ID_LEN 4
25035 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_OFST 0
25036 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_LEN 4
25037 #define MAE_ACTION_RULE_RESPONSE_ASL_ID_LBN 0
25039 /* Only one of ASL_ID or AS_ID may have a non-NULL value. */
25040 #define MAE_ACTION_RULE_RESPONSE_AS_ID_OFST 4
25041 #define MAE_ACTION_RULE_RESPONSE_AS_ID_LEN 4
25044 /* Controls lookup flow when this rule is hit. See sub-fields for details. More
25045 * info on the lookup sequence can be found in SF-122976-TC. It is an error to
25049 #define MAE_ACTION_RULE_RESPONSE_LOOKUP_CONTROL_LEN 4
25051 #define MAE_ACTION_RULE_RESPONSE_DO_CT_LBN 0
25074 #define MAE_ACTION_RULE_RESPONSE_COUNTER_ID_LEN 4
25086 #define MC_CMD_MAE_ACTION_RULE_INSERT 0x15c
25096 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_NUM(len) (((len)-28)/1)
25098 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_OFST 0
25099 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_PRIO_LEN 4
25101 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RESPONSE_OFST 4
25105 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_RSVD_LEN 4
25109 #define MC_CMD_MAE_ACTION_RULE_INSERT_IN_MATCH_CRITERIA_MINNUM 0
25114 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_LEN 4
25115 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_OFST 0
25116 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_AR_ID_LEN 4
25119 #define MC_CMD_MAE_ACTION_RULE_INSERT_OUT_ACTION_RULE_ID_NULL 0xffffffff
25127 #define MC_CMD_MAE_ACTION_RULE_UPDATE 0x15d
25135 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_OFST 0
25136 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_AR_ID_LEN 4
25138 #define MC_CMD_MAE_ACTION_RULE_UPDATE_IN_RESPONSE_OFST 4
25142 #define MC_CMD_MAE_ACTION_RULE_UPDATE_OUT_LEN 0
25148 #define MC_CMD_MAE_ACTION_RULE_DELETE 0x155
25154 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LENMIN 4
25157 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_LEN(num) (0+4*(num))
25158 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_NUM(len) (((len)-0)/4)
25160 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_OFST 0
25161 #define MC_CMD_MAE_ACTION_RULE_DELETE_IN_AR_ID_LEN 4
25167 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LENMIN 4
25170 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_LEN(num) (0+4*(num))
25171 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_NUM(len) (((len)-0)/4)
25173 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_OFST 0
25174 #define MC_CMD_MAE_ACTION_RULE_DELETE_OUT_DELETED_AR_ID_LEN 4
25182 * Return the m-port corresponding to a selector.
25184 #define MC_CMD_MAE_MPORT_LOOKUP 0x160
25190 #define MC_CMD_MAE_MPORT_LOOKUP_IN_LEN 4
25191 #define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_OFST 0
25192 #define MC_CMD_MAE_MPORT_LOOKUP_IN_MPORT_SELECTOR_LEN 4
25195 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_LEN 4
25196 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_OFST 0
25197 #define MC_CMD_MAE_MPORT_LOOKUP_OUT_MPORT_ID_LEN 4
25202 * Allocates a m-port, which can subsequently be used in action rules as a
25205 #define MC_CMD_MAE_MPORT_ALLOC 0x163
25212 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
25215 #define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_OFST 0
25216 #define MC_CMD_MAE_MPORT_ALLOC_IN_TYPE_LEN 4
25217 /* enum: Traffic can be sent to this type of m-port using an override
25218 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
25219 * nominated m-port, and will be delivered with metadata identifying the alias
25220 * m-port.
25222 #define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_ALIAS 0x1
25223 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
25224 * VNIC by specifying the created m-port as an m-port selector at queue
25227 #define MC_CMD_MAE_MPORT_ALLOC_IN_MPORT_TYPE_VNIC 0x2
25228 /* 128-bit value for use by the driver. */
25229 #define MC_CMD_MAE_MPORT_ALLOC_IN_UUID_OFST 4
25234 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
25237 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_OFST 0
25238 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_TYPE_LEN 4
25239 /* enum: Traffic can be sent to this type of m-port using an override
25240 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
25241 * nominated m-port, and will be delivered with metadata identifying the alias
25242 * m-port.
25244 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_ALIAS 0x1
25245 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
25246 * VNIC by specifying the created m-port as an m-port selector at queue
25249 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_MPORT_TYPE_VNIC 0x2
25250 /* 128-bit value for use by the driver. */
25251 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_UUID_OFST 4
25253 /* An m-port selector identifying the VNIC to which traffic should be
25255 * the m-port assigned to the calling client).
25258 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_IN_DELIVER_MPORT_LEN 4
25262 /* The type of m-port to allocate. Firmware may return ENOTSUP for certain
25265 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_OFST 0
25266 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_TYPE_LEN 4
25267 /* enum: Traffic can be sent to this type of m-port using an override
25268 * descriptor. Traffic received on this type of m-port will go to the VNIC on a
25269 * nominated m-port, and will be delivered with metadata identifying the alias
25270 * m-port.
25272 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_ALIAS 0x1
25273 /* enum: This type of m-port has a VNIC attached. Queues can be created on this
25274 * VNIC by specifying the created m-port as an m-port selector at queue
25277 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_MPORT_TYPE_VNIC 0x2
25278 /* 128-bit value for use by the driver. */
25279 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_IN_UUID_OFST 4
25283 #define MC_CMD_MAE_MPORT_ALLOC_OUT_LEN 4
25284 /* ID of newly-allocated m-port. */
25285 #define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_OFST 0
25286 #define MC_CMD_MAE_MPORT_ALLOC_OUT_MPORT_ID_LEN 4
25290 /* ID of newly-allocated m-port. */
25291 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_OFST 0
25292 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_MPORT_ID_LEN 4
25294 * using an alias type m-port. This value is guaranteed unique on the VNIC
25299 #define MC_CMD_MAE_MPORT_ALLOC_ALIAS_OUT_LABEL_LEN 4
25302 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_LEN 4
25303 /* ID of newly-allocated m-port. */
25304 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_OFST 0
25305 #define MC_CMD_MAE_MPORT_ALLOC_VNIC_OUT_MPORT_ID_LEN 4
25310 * Free a m-port which was previously allocated by the driver.
25312 #define MC_CMD_MAE_MPORT_FREE 0x164
25318 #define MC_CMD_MAE_MPORT_FREE_IN_LEN 4
25320 #define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_OFST 0
25321 #define MC_CMD_MAE_MPORT_FREE_IN_MPORT_ID_LEN 4
25324 #define MC_CMD_MAE_MPORT_FREE_OUT_LEN 0
25328 #define MAE_MPORT_DESC_MPORT_ID_OFST 0
25329 #define MAE_MPORT_DESC_MPORT_ID_LEN 4
25330 #define MAE_MPORT_DESC_MPORT_ID_LBN 0
25333 #define MAE_MPORT_DESC_FLAGS_OFST 4
25334 #define MAE_MPORT_DESC_FLAGS_LEN 4
25338 #define MAE_MPORT_DESC_CALLER_FLAGS_LEN 4
25340 #define MAE_MPORT_DESC_CAN_RECEIVE_ON_LBN 0
25353 /* Not the ideal name; it's really the type of thing connected to the m-port */
25355 #define MAE_MPORT_DESC_MPORT_TYPE_LEN 4
25357 #define MAE_MPORT_DESC_MPORT_TYPE_NET_PORT 0x0
25358 /* enum: Adds metadata and delivers to another m-port */
25359 #define MAE_MPORT_DESC_MPORT_TYPE_ALIAS 0x1
25361 #define MAE_MPORT_DESC_MPORT_TYPE_VNIC 0x2
25364 /* 128-bit value available to drivers for m-port identification. */
25373 #define MAE_MPORT_DESC_RESERVED_LO_LEN 4
25377 #define MAE_MPORT_DESC_RESERVED_HI_LEN 4
25384 #define MAE_MPORT_DESC_NET_PORT_IDX_LEN 4
25387 /* The m-port delivered to */
25389 #define MAE_MPORT_DESC_ALIAS_DELIVER_MPORT_ID_LEN 4
25394 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_LEN 4
25395 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_FUNCTION 0x1 /* enum */
25396 #define MAE_MPORT_DESC_VNIC_CLIENT_TYPE_PLUGIN 0x2 /* enum */
25404 #define MAE_MPORT_DESC_VNIC_FUNCTION_INTERFACE_LEN 4
25414 #define MAE_MPORT_DESC_VF_IDX_NULL 0xffff
25419 #define MAE_MPORT_DESC_VNIC_PLUGIN_TBD_LEN 4
25426 * Firmware maintains a per-client journal of mport creations and deletions.
25427 * This journal is clear-on-read, i.e. repeated calls of this command will
25431 #define MC_CMD_MAE_MPORT_READ_JOURNAL 0x147
25437 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_LEN 4
25439 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_OFST 0
25440 #define MC_CMD_MAE_MPORT_READ_JOURNAL_IN_FLAGS_LEN 4
25447 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_NUM(len) (((len)-12)/1)
25449 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_OFST 0
25450 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_FLAGS_LEN 4
25451 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_OFST 0
25452 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MORE_LBN 0
25455 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_OFST 4
25456 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_COUNT_LEN 4
25458 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_SIZEOF_MPORT_DESC_LEN 4
25465 #define MC_CMD_MAE_MPORT_READ_JOURNAL_OUT_MPORT_DESC_DATA_MINNUM 0
25470 * describes the location and properties of one N-bit field within a wider
25471 * M-bit key/mask/response value.
25475 #define TABLE_FIELD_DESCR_FIELD_ID_OFST 0
25479 #define TABLE_FIELD_DESCR_FIELD_ID_LBN 0
25487 #define TABLE_FIELD_DESCR_WIDTH_OFST 4
25497 #define TABLE_FIELD_DESCR_MASK_NEVER 0x0
25499 #define TABLE_FIELD_DESCR_MASK_EXACT 0x1
25501 #define TABLE_FIELD_DESCR_MASK_TERNARY 0x2
25502 /* enum: Whole field match: mask must be all 1 bits, or all 0 bits. */
25503 #define TABLE_FIELD_DESCR_MASK_WHOLE_FIELD 0x3
25504 /* enum: Longest prefix match: mask must be 1 bit(s) followed by 0 bit(s). */
25505 #define TABLE_FIELD_DESCR_MASK_LPM 0x4
25509 * currently use version 0.
25521 #define MC_CMD_TABLE_LIST 0x1c9
25527 #define MC_CMD_TABLE_LIST_IN_LEN 4
25528 /* Index of the first item to be returned in the TABLE_ID sequence. (Set to 0
25532 #define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_OFST 0
25533 #define MC_CMD_TABLE_LIST_IN_FIRST_TABLE_ID_INDEX_LEN 4
25536 #define MC_CMD_TABLE_LIST_OUT_LENMIN 4
25539 #define MC_CMD_TABLE_LIST_OUT_LEN(num) (4+4*(num))
25540 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_NUM(len) (((len)-4)/4)
25542 #define MC_CMD_TABLE_LIST_OUT_N_TABLES_OFST 0
25543 #define MC_CMD_TABLE_LIST_OUT_N_TABLES_LEN 4
25545 * items can be obtained by repeating the call with a non-zero
25548 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_OFST 4
25549 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_LEN 4
25550 #define MC_CMD_TABLE_LIST_OUT_TABLE_ID_MINNUM 0
25563 #define MC_CMD_TABLE_DESCRIPTOR 0x1ca
25571 #define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_OFST 0
25572 #define MC_CMD_TABLE_DESCRIPTOR_IN_TABLE_ID_LEN 4
25575 /* Index of the first item to be returned in the FIELDS sequence. (Set to 0 for
25579 #define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_OFST 4
25580 #define MC_CMD_TABLE_DESCRIPTOR_IN_FIRST_FIELDS_INDEX_LEN 4
25587 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_NUM(len) (((len)-20)/8)
25589 #define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_OFST 0
25590 #define MC_CMD_TABLE_DESCRIPTOR_OUT_MAX_ENTRIES_LEN 4
25595 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_OFST 4
25601 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_DIRECT 0x1
25603 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_BCAM 0x2
25607 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_TCAM 0x3
25608 /* enum: STCAM (semi-TCAM) table: like a TCAM but entries shared a limited
25611 #define MC_CMD_TABLE_DESCRIPTOR_OUT_TYPE_STCAM 0x4
25624 /* Number of priorities for STCAM or TCAM; otherwise 0. The priority of a table
25626 * 0=highest to N_PRIORITIES-1=lowest.
25630 /* Maximum number of masks for STCAM; otherwise 0. */
25637 #define MC_CMD_TABLE_DESCRIPTOR_OUT_ALLOC_MASKS_LBN 0
25642 * always set to 0 indicating the original MC_CMD_TABLE_INSERT/UPDATE/DELETE
25650 * by repeating the call with a non-zero FIRST_FIELDS_INDEX.
25655 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_LO_LEN 4
25659 #define MC_CMD_TABLE_DESCRIPTOR_OUT_FIELDS_HI_LEN 4
25675 #define MC_CMD_TABLE_INSERT 0x1cd
25684 #define MC_CMD_TABLE_INSERT_IN_LEN(num) (12+4*(num))
25685 #define MC_CMD_TABLE_INSERT_IN_DATA_NUM(len) (((len)-12)/4)
25687 #define MC_CMD_TABLE_INSERT_IN_TABLE_ID_OFST 0
25688 #define MC_CMD_TABLE_INSERT_IN_TABLE_ID_LEN 4
25692 #define MC_CMD_TABLE_INSERT_IN_KEY_WIDTH_OFST 4
25694 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
25701 * data is required and this must be 0).
25705 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
25706 * reports ALLOC_MASKS==1. Otherwise set to 0.
25710 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
25713 /* (32-bit alignment padding - set to 0) */
25716 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
25717 * data values. Each of these items is logically treated as a single wide N-bit
25720 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
25722 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
25725 #define MC_CMD_TABLE_INSERT_IN_DATA_LEN 4
25731 #define MC_CMD_TABLE_INSERT_OUT_LEN 0
25742 #define MC_CMD_TABLE_DELETE 0x1cf
25751 #define MC_CMD_TABLE_DELETE_IN_LEN(num) (12+4*(num))
25752 #define MC_CMD_TABLE_DELETE_IN_DATA_NUM(len) (((len)-12)/4)
25754 #define MC_CMD_TABLE_DELETE_IN_TABLE_ID_OFST 0
25755 #define MC_CMD_TABLE_DELETE_IN_TABLE_ID_LEN 4
25759 #define MC_CMD_TABLE_DELETE_IN_KEY_WIDTH_OFST 4
25761 /* Width in bits of supplied mask data (0 for direct/BCAM tables, or for STCAM
25768 * data is required and this must be 0).
25772 /* Mask ID for STCAM table - used instead of mask data if the table descriptor
25773 * reports ALLOC_MASKS==1. Otherwise set to 0.
25777 /* Priority for TCAM or STCAM, in range 0..N_PRIORITIES-1, otherwise 0. */
25780 /* (32-bit alignment padding - set to 0) */
25783 /* Sequence of key, mask (if MASK_WIDTH > 0), and response (if RESP_WIDTH > 0)
25784 * data values. Each of these items is logically treated as a single wide N-bit
25787 * N-bit value is padded with 0 bits at the MSB end if necessary to make a
25789 * sequence of 32-bit words, bits [31:0] first, then bits [63:32], etc.
25792 #define MC_CMD_TABLE_DELETE_IN_DATA_LEN 4
25798 #define MC_CMD_TABLE_DELETE_OUT_LEN 0
25800 /* MC_CMD_QUEUE_HANDLE structuredef: On X4, to distinguish between full-
25801 * featured (X2-style) VIs and low-latency (X3-style) queues, we use the top
25806 #define MC_CMD_QUEUE_HANDLE_LEN 4
25810 #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_OFST 0
25811 #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LEN 4
25812 #define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_OFST 0
25813 #define MC_CMD_QUEUE_HANDLE_QUEUE_NUM_LBN 0
25815 #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_OFST 0
25818 /* enum: Indicates that the queue instance is a full-featured VI */
25819 #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_FF_VI 0x0
25821 #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_TXQ 0x1
25823 #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_RXQ 0x2
25825 #define MC_CMD_QUEUE_HANDLE_QUEUE_TYPE_LL_EVQ 0x3
25826 #define MC_CMD_QUEUE_HANDLE_QUEUE_HANDLE_LBN 0
25832 * Allocate low latency (X3-style) queues for current PCI function. Can be
25835 #define MC_CMD_ALLOC_LL_QUEUES 0x1dd
25843 #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_OFST 0
25844 #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_TXQ_COUNT_LEN 4
25846 #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_OFST 4
25847 #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_TXQ_COUNT_LEN 4
25850 #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_RXQ_COUNT_LEN 4
25853 #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_RXQ_COUNT_LEN 4
25856 #define MC_CMD_ALLOC_LL_QUEUES_IN_MIN_EVQ_COUNT_LEN 4
25859 #define MC_CMD_ALLOC_LL_QUEUES_IN_MAX_EVQ_COUNT_LEN 4
25865 #define MC_CMD_ALLOC_LL_QUEUES_OUT_LEN(num) (12+4*(num))
25866 #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_NUM(len) (((len)-12)/4)
25868 #define MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_OFST 0
25869 #define MC_CMD_ALLOC_LL_QUEUES_OUT_TXQ_COUNT_LEN 4
25871 #define MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_OFST 4
25872 #define MC_CMD_ALLOC_LL_QUEUES_OUT_RXQ_COUNT_LEN 4
25875 #define MC_CMD_ALLOC_LL_QUEUES_OUT_EVQ_COUNT_LEN 4
25882 #define MC_CMD_ALLOC_LL_QUEUES_OUT_QUEUES_LEN 4
25890 * Free low latency (X3-style) queues for current PCI function.
25892 #define MC_CMD_FREE_LL_QUEUES 0x1de
25901 #define MC_CMD_FREE_LL_QUEUES_IN_LEN(num) (4+4*(num))
25902 #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_NUM(len) (((len)-4)/4)
25904 #define MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_OFST 0
25905 #define MC_CMD_FREE_LL_QUEUES_IN_QUEUE_COUNT_LEN 4
25910 #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_OFST 4
25911 #define MC_CMD_FREE_LL_QUEUES_IN_QUEUES_LEN 4
25917 #define MC_CMD_FREE_LL_QUEUES_OUT_LEN 0