Lines Matching +full:0 +full:x8c20
65 #define InterFrameGap 0x03 /* 3 means InterFrameGap = the shortest one */
76 #define OCP_STD_PHY_BASE 0xa400
152 { PCI_VDEVICE(REALTEK, 0x2502) },
153 { PCI_VDEVICE(REALTEK, 0x2600) },
154 { PCI_VDEVICE(REALTEK, 0x8129) },
155 { PCI_VDEVICE(REALTEK, 0x8136), RTL_CFG_NO_GBIT },
156 { PCI_VDEVICE(REALTEK, 0x8161) },
157 { PCI_VDEVICE(REALTEK, 0x8162) },
158 { PCI_VDEVICE(REALTEK, 0x8167) },
159 { PCI_VDEVICE(REALTEK, 0x8168) },
160 { PCI_VDEVICE(NCUBE, 0x8168) },
161 { PCI_VDEVICE(REALTEK, 0x8169) },
162 { PCI_VENDOR_ID_DLINK, 0x4300,
163 PCI_VENDOR_ID_DLINK, 0x4b10, 0, 0 },
164 { PCI_VDEVICE(DLINK, 0x4300) },
165 { PCI_VDEVICE(DLINK, 0x4302) },
166 { PCI_VDEVICE(AT, 0xc107) },
167 { PCI_VDEVICE(USR, 0x0116) },
168 { PCI_VENDOR_ID_LINKSYS, 0x1032, PCI_ANY_ID, 0x0024 },
169 { 0x0001, 0x8168, PCI_ANY_ID, 0x2410 },
170 { PCI_VDEVICE(REALTEK, 0x8125) },
171 { PCI_VDEVICE(REALTEK, 0x8126) },
172 { PCI_VDEVICE(REALTEK, 0x3000) },
173 { PCI_VDEVICE(REALTEK, 0x5000) },
180 MAC0 = 0, /* Ethernet hardware address. */
183 CounterAddrLow = 0x10,
184 CounterAddrHigh = 0x14,
185 TxDescStartAddrLow = 0x20,
186 TxDescStartAddrHigh = 0x24,
187 TxHDescStartAddrLow = 0x28,
188 TxHDescStartAddrHigh = 0x2c,
189 FLASH = 0x30,
190 ERSR = 0x36,
191 ChipCmd = 0x37,
192 TxPoll = 0x38,
193 IntrMask = 0x3c,
194 IntrStatus = 0x3e,
196 TxConfig = 0x40,
200 RxConfig = 0x44,
212 Cfg9346 = 0x50,
213 Config0 = 0x51,
214 Config1 = 0x52,
215 Config2 = 0x53,
218 Config3 = 0x54,
219 Config4 = 0x55,
220 Config5 = 0x56,
221 PHYAR = 0x60,
222 PHYstatus = 0x6c,
223 RxMaxSize = 0xda,
224 CPlusCmd = 0xe0,
225 IntrMitigate = 0xe2,
230 #define RTL_COALESCE_RX_FRAMES GENMASK(3, 0)
232 #define RTL_COALESCE_T_MAX 0x0fU
235 RxDescAddrLow = 0xe4,
236 RxDescAddrHigh = 0xe8,
237 EarlyTxThres = 0xec, /* 8169. Unit of 32 bytes. */
239 #define NoEarlyTx 0x3f /* Max value : no early transmit. */
241 MaxTxPacketSize = 0xec, /* 8101/8168. Unit of 128 bytes. */
244 #define EarlySize 0x27
246 FuncEvent = 0xf0,
247 FuncEventMask = 0xf4,
248 FuncPresetState = 0xf8,
249 IBCR0 = 0xf8,
250 IBCR2 = 0xf9,
251 IBIMR0 = 0xfa,
252 IBISR0 = 0xfb,
253 FuncForceEvent = 0xfc,
257 CSIDR = 0x64,
258 CSIAR = 0x68,
259 #define CSIAR_FLAG 0x80000000
260 #define CSIAR_WRITE_CMD 0x80000000
261 #define CSIAR_BYTE_ENABLE 0x0000f000
262 #define CSIAR_ADDR_MASK 0x00000fff
263 PMCH = 0x6f,
267 EPHYAR = 0x80,
268 #define EPHYAR_FLAG 0x80000000
269 #define EPHYAR_WRITE_CMD 0x80000000
270 #define EPHYAR_REG_MASK 0x1f
272 #define EPHYAR_DATA_MASK 0xffff
273 DLLPR = 0xd0,
276 DBG_REG = 0xd1,
279 TWSI = 0xd2,
280 MCU = 0xd3,
288 EFUSEAR = 0xdc,
289 #define EFUSEAR_FLAG 0x80000000
290 #define EFUSEAR_WRITE_CMD 0x80000000
291 #define EFUSEAR_READ_CMD 0x00000000
292 #define EFUSEAR_REG_MASK 0x03ff
294 #define EFUSEAR_DATA_MASK 0xff
295 MISC_1 = 0xf2,
300 LED_CTRL = 0x18,
301 LED_FREQ = 0x1a,
302 EEE_LED = 0x1b,
303 ERIDR = 0x70,
304 ERIAR = 0x74,
305 #define ERIAR_FLAG 0x80000000
306 #define ERIAR_WRITE_CMD 0x80000000
307 #define ERIAR_READ_CMD 0x00000000
310 #define ERIAR_EXGMAC (0x00 << ERIAR_TYPE_SHIFT)
311 #define ERIAR_MSIX (0x01 << ERIAR_TYPE_SHIFT)
312 #define ERIAR_ASF (0x02 << ERIAR_TYPE_SHIFT)
313 #define ERIAR_OOB (0x02 << ERIAR_TYPE_SHIFT)
315 #define ERIAR_MASK_0001 (0x1 << ERIAR_MASK_SHIFT)
316 #define ERIAR_MASK_0011 (0x3 << ERIAR_MASK_SHIFT)
317 #define ERIAR_MASK_0100 (0x4 << ERIAR_MASK_SHIFT)
318 #define ERIAR_MASK_0101 (0x5 << ERIAR_MASK_SHIFT)
319 #define ERIAR_MASK_1111 (0xf << ERIAR_MASK_SHIFT)
320 EPHY_RXER_NUM = 0x7c,
321 OCPDR = 0xb0, /* OCP GPHY access */
322 #define OCPDR_WRITE_CMD 0x80000000
323 #define OCPDR_READ_CMD 0x00000000
324 #define OCPDR_REG_MASK 0x7f
326 #define OCPDR_DATA_MASK 0xffff
327 OCPAR = 0xb4,
328 #define OCPAR_FLAG 0x80000000
329 #define OCPAR_GPHY_WRITE_CMD 0x8000f060
330 #define OCPAR_GPHY_READ_CMD 0x0000f060
331 GPHY_OCP = 0xb8,
332 RDSAR1 = 0xd0, /* 8168c only. Undocumented on 8168dp */
333 MISC = 0xf0, /* 8168e only. */
342 LEDSEL0 = 0x18,
343 INT_CFG0_8125 = 0x34,
344 #define INT_CFG0_ENABLE_8125 BIT(0)
346 IntrMask_8125 = 0x38,
347 IntrStatus_8125 = 0x3c,
348 INT_CFG1_8125 = 0x7a,
349 LEDSEL2 = 0x84,
350 LEDSEL1 = 0x86,
351 TxPoll_8125 = 0x90,
352 LEDSEL3 = 0x96,
353 MAC0_BKP = 0x19e0,
354 RSS_CTRL_8125 = 0x4500,
355 Q_NUM_CTRL_8125 = 0x4800,
356 EEE_TXIDLE_TIMER_8125 = 0x6048,
359 #define LEDSEL_MASK_8125 0x23f
369 SYSErr = 0x8000,
370 PCSTimeout = 0x4000,
371 SWInt = 0x0100,
372 TxDescUnavail = 0x0080,
373 RxFIFOOver = 0x0040,
374 LinkChg = 0x0020,
375 RxOverflow = 0x0010,
376 TxErr = 0x0008,
377 TxOK = 0x0004,
378 RxErr = 0x0002,
379 RxOK = 0x0001,
388 StopReq = 0x80,
389 CmdReset = 0x10,
390 CmdRxEnb = 0x08,
391 CmdTxEnb = 0x04,
392 RxBufEmpty = 0x01,
395 HPQ = 0x80, /* Poll cmd on the high prio queue */
396 NPQ = 0x40, /* Poll cmd on the low prio queue */
397 FSWInt = 0x01, /* Forced software interrupt */
400 Cfg9346_Lock = 0x00,
401 Cfg9346_Unlock = 0xc0,
404 AcceptErr = 0x20,
405 AcceptRunt = 0x10,
406 #define RX_CONFIG_ACCEPT_ERR_MASK 0x30
407 AcceptBroadcast = 0x08,
408 AcceptMulticast = 0x04,
409 AcceptMyPhys = 0x02,
410 AcceptAllPhys = 0x01,
411 #define RX_CONFIG_ACCEPT_OK_MASK 0x0f
412 #define RX_CONFIG_ACCEPT_MASK 0x3f
416 TxDMAShift = 8, /* DMA burst value (0-7) is shift this many bits */
425 PMEnable = (1 << 0), /* Power Management Enable */
430 PCI_Clock_66MHz = 0x01,
431 PCI_Clock_33MHz = 0x00,
438 Beacon_en = (1 << 0), /* 8168 only. Reserved in the 8168b */
449 PMEStatus = (1 << 0), /* PME status can be reset by PCI RST# */
450 ASPM_en = (1 << 0), /* ASPM enable */
463 Mac_dbgo_sel = 0x001c, // 8168
468 #define INTT_MASK GENMASK(1, 0)
472 TBI_Enable = 0x80,
473 TxFlowCtrl = 0x40,
474 RxFlowCtrl = 0x20,
475 _1000bpsF = 0x10,
476 _100bps = 0x08,
477 _10bps = 0x04,
478 LinkStatus = 0x02,
479 FullDup = 0x01,
482 CounterReset = 0x1,
485 CounterDump = 0x8,
503 #define TD_MSS_MAX 0x07ffu /* MSS value */
524 #define GTTCPHO_MAX 0x7f
528 #define TCPHO_MAX 0x3ff
539 PID0 = (1 << 17), /* Protocol ID bit 0/2 */
794 for (i = 0; i < ETH_ALEN; i++) in rtl_read_mac_from_reg()
808 for (i = 0; i < n; i++) { in rtl_loop_wait()
850 if (ret < 0) in rtl8168_led_mod_ctrl()
859 return 0; in rtl8168_led_mod_ctrl()
868 if (ret < 0) in rtl8168_get_led_mode()
893 if (ret < 0) in rtl8125_set_led_mode()
903 return 0; in rtl8125_set_led_mode()
913 if (ret < 0) in rtl8125_get_led_mode()
934 pdom[0] = '\0'; in r8169_get_led_name()
939 pfun[0] = '\0'; in r8169_get_led_name()
951 *cmd |= 0xf70 << 18; in r8168fp_adjust_ocp_cmd()
964 if (WARN(addr & 3 || !mask, "addr: 0x%x, mask: 0x%08x\n", addr, mask)) in _rtl_eri_write()
988 RTL_R32(tp, ERIDR) : ~0; in _rtl_eri_read()
1005 rtl_w0w1_eri(tp, addr, p, 0); in rtl_eri_set_bits()
1010 rtl_w0w1_eri(tp, addr, 0, m); in rtl_eri_clear_bits()
1015 return WARN_ONCE(reg & 0xffff0001, "Invalid ocp reg %x!\n", reg); in rtl_ocp_reg_failure()
1036 return 0; in r8168_phy_ocp_read()
1041 (RTL_R32(tp, GPHY_OCP) & 0xffff) : -ETIMEDOUT; in r8168_phy_ocp_read()
1064 return 0; in __r8168_mac_ocp_read()
1103 rtl_eri_set_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1105 rtl_eri_clear_bits(tp, 0x1a8, 0xfc000000); in rtl8168g_phy_suspend_quirk()
1114 if (reg == 0x1f) { in r8168g_mdio_write()
1120 reg -= 0x10; in r8168g_mdio_write()
1130 if (reg == 0x1f) in r8168g_mdio_read()
1131 return tp->ocp_base == OCP_STD_PHY_BASE ? 0 : tp->ocp_base >> 4; in r8168g_mdio_read()
1134 reg -= 0x10; in r8168g_mdio_read()
1141 if (reg == 0x1f) { in mac_mcu_write()
1156 return RTL_R32(tp, PHYAR) & 0x80000000; in DECLARE_RTL_COND()
1161 RTL_W32(tp, PHYAR, 0x80000000 | (reg & 0x1f) << 16 | (value & 0xffff)); in r8169_mdio_write()
1175 RTL_W32(tp, PHYAR, 0x0 | (reg & 0x1f) << 16); in r8169_mdio_read()
1178 RTL_R32(tp, PHYAR) & 0xffff : -ETIMEDOUT; in r8169_mdio_read()
1194 #define R8168DP_1_MDIO_ACCESS_BIT 0x00020000
1198 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) & ~R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_start()
1203 RTL_W32(tp, 0xd0, RTL_R32(tp, 0xd0) | R8168DP_1_MDIO_ACCESS_BIT); in r8168dp_2_mdio_stop()
1221 return 0xc912; in r8168dp_2_mdio_read()
1281 RTL_R32(tp, EPHYAR) & EPHYAR_DATA_MASK : ~0; in rtl_ephy_read()
1286 RTL_W32(tp, OCPAR, 0x0fu << 12 | (reg & 0x0fff)); in r8168dp_ocp_read()
1288 RTL_R32(tp, OCPDR) : ~0; in r8168dp_ocp_read()
1300 RTL_W32(tp, OCPAR, OCPAR_FLAG | ((u32)mask & 0x0f) << 12 | (reg & 0x0fff)); in r8168dp_ocp_write()
1307 _rtl_eri_write(tp, reg, ((u32)mask & 0x0f) << ERIAR_MASK_SHIFT, in r8168ep_ocp_write()
1313 rtl_eri_write(tp, 0xe8, ERIAR_MASK_0001, cmd); in r8168dp_oob_notify()
1315 r8168dp_ocp_write(tp, 0x1, 0x30, 0x00000001); in r8168dp_oob_notify()
1318 #define OOB_CMD_RESET 0x00
1319 #define OOB_CMD_DRIVER_START 0x05
1320 #define OOB_CMD_DRIVER_STOP 0x06
1324 return (tp->mac_version == RTL_GIGA_MAC_VER_31) ? 0xb8 : 0x10; in rtl8168_get_ocp_reg()
1333 return r8168dp_ocp_read(tp, reg) & 0x00000800; in DECLARE_RTL_COND()
1338 return r8168ep_ocp_read(tp, 0x124) & 0x00000001; in DECLARE_RTL_COND()
1343 return RTL_R8(tp, IBISR0) & 0x20; in DECLARE_RTL_COND()
1348 RTL_W8(tp, IBCR2, RTL_R8(tp, IBCR2) & ~0x01); in rtl8168ep_stop_cmac()
1350 RTL_W8(tp, IBISR0, RTL_R8(tp, IBISR0) | 0x20); in rtl8168ep_stop_cmac()
1351 RTL_W8(tp, IBCR0, RTL_R8(tp, IBCR0) & ~0x01); in rtl8168ep_stop_cmac()
1363 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_START); in rtl8168ep_driver_start()
1364 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_start()
1371 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_START); in rtl8125bp_driver_start()
1372 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); in rtl8125bp_driver_start()
1373 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); in rtl8125bp_driver_start()
1396 r8168ep_ocp_write(tp, 0x01, 0x180, OOB_CMD_DRIVER_STOP); in rtl8168ep_driver_stop()
1397 r8168ep_ocp_write(tp, 0x01, 0x30, r8168ep_ocp_read(tp, 0x30) | 0x01); in rtl8168ep_driver_stop()
1404 r8168ep_ocp_write(tp, 0x01, 0x14, OOB_CMD_DRIVER_STOP); in rtl8125bp_driver_stop()
1405 r8168ep_ocp_write(tp, 0x01, 0x18, 0x00); in rtl8125bp_driver_stop()
1406 r8168ep_ocp_write(tp, 0x01, 0x10, 0x01); in rtl8125bp_driver_stop()
1428 return r8168ep_ocp_read(tp, 0x128) & BIT(0); in r8168ep_check_dash()
1470 rtl_eri_clear_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1471 rtl_eri_set_bits(tp, 0xdc, BIT(0)); in rtl_reset_packet_filter()
1484 RTL_R32(tp, EFUSEAR) & EFUSEAR_DATA_MASK : ~0; in rtl8168d_efuse_read()
1506 RTL_W32(tp, IntrMask_8125, 0); in rtl_irq_disable()
1508 RTL_W16(tp, IntrMask, 0); in rtl_irq_disable()
1522 rtl_ack_events(tp, 0xffffffff); in rtl8169_irq_mask_and_ack()
1533 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1534 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1536 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1537 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1539 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1540 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1546 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x00000011); in rtl_link_chg_patch()
1547 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x00000005); in rtl_link_chg_patch()
1549 rtl_eri_write(tp, 0x1bc, ERIAR_MASK_1111, 0x0000001f); in rtl_link_chg_patch()
1550 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_1111, 0x0000003f); in rtl_link_chg_patch()
1554 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x4d02); in rtl_link_chg_patch()
1555 rtl_eri_write(tp, 0x1dc, ERIAR_MASK_0011, 0x0060a); in rtl_link_chg_patch()
1557 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_link_chg_patch()
1578 rtl_eri_set_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1580 rtl_eri_clear_bits(tp, 0x0dc, MagicPacket_v2); in __rtl8169_set_wol()
1583 r8168_mac_ocp_modify(tp, 0xc0b6, 0, BIT(0)); in __rtl8169_set_wol()
1585 r8168_mac_ocp_modify(tp, 0xc0b6, BIT(0), 0); in __rtl8169_set_wol()
1593 r8168_mac_ocp_modify(tp, 0xe0c6, 0x3f, in __rtl8169_set_wol()
1594 wolopts & WAKE_PHY ? 0x13 : 0); in __rtl8169_set_wol()
1619 tp->dev->ethtool->wol_enabled = wolopts ? 1 : 0; in __rtl8169_set_wol()
1633 return 0; in rtl8169_set_wol()
1712 return 0; in rtl8169_set_features()
1718 TxVlanTag | swab16(skb_vlan_tag_get(skb)) : 0x00; in rtl8169_tx_vlan_tag()
1726 __vlan_hwaccel_put_tag(skb, htons(ETH_P_8021Q), swab16(opts2 & 0xffff)); in rtl8169_rx_vlan_tag()
1737 for (i = 0; i < R8169_REGS_SIZE; i += 4) in rtl8169_get_regs()
1790 * is disabled. If 0xff chip may be in a PCI power-save state. in rtl8169_update_counters()
1792 if (val & CmdRxEnb && val != 0xff) in rtl8169_update_counters()
1840 data[0] = le64_to_cpu(counters->tx_packets); in rtl8169_get_ethtool_stats()
1867 * > 1 - the availability of the IntrMitigate (0xe2) register through the
1875 * (0xe0) bit 1 and bit 0.
1878 * bit[1:0] \ speed 1000M 100M 10M
1879 * 0 0 320ns 2.56us 40.96us
1880 * 0 1 2.56us 20.48us 327.7us
1881 * 1 0 5.12us 40.96us 655.4us
1885 * bit[1:0] \ speed 1000M 100M 10M
1886 * 0 0 5us 2.56us 40.96us
1887 * 0 1 40us 20.48us 327.7us
1888 * 1 0 80us 40.96us 655.4us
1892 /* rx/tx scale factors for all CPlusCmd[0:1] cases */
1905 { 0 },
1912 { 0 },
1952 memset(ec, 0, sizeof(*ec)); in rtl_get_coalesce()
1954 /* get rx/tx scale corresponding to current speed and CPlusCmd[0:1] */ in rtl_get_coalesce()
1967 /* ethtool_coalesce states usecs and max_frames must not both be 0 */ in rtl_get_coalesce()
1976 return 0; in rtl_get_coalesce()
1979 /* choose appropriate scale factor and CPlusCmd[0:1] for (speed, usec) */
1990 for (i = 0; i < 4; i++) { in rtl_coalesce_choose_scale()
2009 u16 w = 0, cp01 = 0; in rtl_set_coalesce()
2020 if (scale < 0) in rtl_set_coalesce()
2024 * not only when usecs=0 because of e.g. the following scenario: in rtl_set_coalesce()
2026 * - both rx_usecs=0 & rx_frames=0 in hardware (no delay on RX) in rtl_set_coalesce()
2027 * - rtl_get_coalesce returns rx_usecs=0, rx_frames=1 in rtl_set_coalesce()
2031 * if we want to ignore rx_frames then it has to be set to 0. in rtl_set_coalesce()
2034 rx_fr = 0; in rtl_set_coalesce()
2036 tx_fr = 0; in rtl_set_coalesce()
2066 return 0; in rtl_set_coalesce()
2071 unsigned int timer_val = READ_ONCE(tp->dev->mtu) + ETH_HLEN + 0x20; in rtl_set_eee_txidle_timer()
2077 r8168_mac_ocp_write(tp, 0xe048, timer_val); in rtl_set_eee_txidle_timer()
2094 return 0; in r8169_get_tx_lpi_timer_us()
2114 return 0; in rtl8169_get_eee()
2160 data->tx_pause = tx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2161 data->rx_pause = rx_pause ? 1 : 0; in rtl8169_get_pauseparam()
2174 return 0; in rtl8169_set_pauseparam()
2275 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x500000 ? 8168Bf : 8168Be in rtl8169_get_mac_version()
2279 * (RTL_R32(tp, TxConfig) & 0x700000) == 0x200000 ? 8101Eb : 8101Ec in rtl8169_get_mac_version()
2287 { 0x7cf, 0x64a, RTL_GIGA_MAC_VER_71 }, in rtl8169_get_mac_version()
2288 { 0x7cf, 0x649, RTL_GIGA_MAC_VER_70 }, in rtl8169_get_mac_version()
2291 { 0x7cf, 0x681, RTL_GIGA_MAC_VER_66 }, in rtl8169_get_mac_version()
2294 { 0x7cf, 0x689, RTL_GIGA_MAC_VER_65 }, in rtl8169_get_mac_version()
2295 { 0x7cf, 0x688, RTL_GIGA_MAC_VER_64 }, in rtl8169_get_mac_version()
2298 { 0x7cf, 0x641, RTL_GIGA_MAC_VER_63 }, in rtl8169_get_mac_version()
2301 { 0x7cf, 0x609, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2303 * { 0x7cf, 0x608, RTL_GIGA_MAC_VER_60 }, in rtl8169_get_mac_version()
2304 * { 0x7c8, 0x608, RTL_GIGA_MAC_VER_61 }, in rtl8169_get_mac_version()
2308 { 0x7cf, 0x54b, RTL_GIGA_MAC_VER_53 }, in rtl8169_get_mac_version()
2309 { 0x7cf, 0x54a, RTL_GIGA_MAC_VER_52 }, in rtl8169_get_mac_version()
2312 { 0x7cf, 0x502, RTL_GIGA_MAC_VER_51 }, in rtl8169_get_mac_version()
2315 * { 0x7cf, 0x501, RTL_GIGA_MAC_VER_50 }, in rtl8169_get_mac_version()
2316 * { 0x7cf, 0x500, RTL_GIGA_MAC_VER_49 }, in rtl8169_get_mac_version()
2320 { 0x7cf, 0x541, RTL_GIGA_MAC_VER_46 }, in rtl8169_get_mac_version()
2323 * { 0x7cf, 0x540, RTL_GIGA_MAC_VER_45 }, in rtl8169_get_mac_version()
2326 { 0x7cf, 0x6c0, RTL_GIGA_MAC_VER_46 }, in rtl8169_get_mac_version()
2329 { 0x7cf, 0x5c8, RTL_GIGA_MAC_VER_44 }, in rtl8169_get_mac_version()
2330 { 0x7cf, 0x509, RTL_GIGA_MAC_VER_42 }, in rtl8169_get_mac_version()
2333 * { 0x7cf, 0x4c1, RTL_GIGA_MAC_VER_41 }, in rtl8169_get_mac_version()
2335 { 0x7cf, 0x4c0, RTL_GIGA_MAC_VER_40 }, in rtl8169_get_mac_version()
2338 { 0x7c8, 0x488, RTL_GIGA_MAC_VER_38 }, in rtl8169_get_mac_version()
2339 { 0x7cf, 0x481, RTL_GIGA_MAC_VER_36 }, in rtl8169_get_mac_version()
2340 { 0x7cf, 0x480, RTL_GIGA_MAC_VER_35 }, in rtl8169_get_mac_version()
2343 { 0x7c8, 0x2c8, RTL_GIGA_MAC_VER_34 }, in rtl8169_get_mac_version()
2344 { 0x7cf, 0x2c1, RTL_GIGA_MAC_VER_32 }, in rtl8169_get_mac_version()
2345 { 0x7c8, 0x2c0, RTL_GIGA_MAC_VER_33 }, in rtl8169_get_mac_version()
2348 { 0x7cf, 0x281, RTL_GIGA_MAC_VER_25 }, in rtl8169_get_mac_version()
2349 { 0x7c8, 0x280, RTL_GIGA_MAC_VER_26 }, in rtl8169_get_mac_version()
2354 * { 0x7cf, 0x288, RTL_GIGA_MAC_VER_27 }, in rtl8169_get_mac_version()
2356 { 0x7cf, 0x28a, RTL_GIGA_MAC_VER_28 }, in rtl8169_get_mac_version()
2357 { 0x7cf, 0x28b, RTL_GIGA_MAC_VER_31 }, in rtl8169_get_mac_version()
2360 { 0x7cf, 0x3c9, RTL_GIGA_MAC_VER_23 }, in rtl8169_get_mac_version()
2361 { 0x7cf, 0x3c8, RTL_GIGA_MAC_VER_18 }, in rtl8169_get_mac_version()
2362 { 0x7c8, 0x3c8, RTL_GIGA_MAC_VER_24 }, in rtl8169_get_mac_version()
2363 { 0x7cf, 0x3c0, RTL_GIGA_MAC_VER_19 }, in rtl8169_get_mac_version()
2364 { 0x7cf, 0x3c2, RTL_GIGA_MAC_VER_20 }, in rtl8169_get_mac_version()
2365 { 0x7cf, 0x3c3, RTL_GIGA_MAC_VER_21 }, in rtl8169_get_mac_version()
2366 { 0x7c8, 0x3c0, RTL_GIGA_MAC_VER_22 }, in rtl8169_get_mac_version()
2369 { 0x7c8, 0x380, RTL_GIGA_MAC_VER_17 }, in rtl8169_get_mac_version()
2371 * { 0x7c8, 0x300, RTL_GIGA_MAC_VER_11 }, in rtl8169_get_mac_version()
2375 { 0x7c8, 0x448, RTL_GIGA_MAC_VER_39 }, in rtl8169_get_mac_version()
2376 { 0x7c8, 0x440, RTL_GIGA_MAC_VER_37 }, in rtl8169_get_mac_version()
2377 { 0x7cf, 0x409, RTL_GIGA_MAC_VER_29 }, in rtl8169_get_mac_version()
2378 { 0x7c8, 0x408, RTL_GIGA_MAC_VER_30 }, in rtl8169_get_mac_version()
2379 { 0x7cf, 0x349, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2380 { 0x7cf, 0x249, RTL_GIGA_MAC_VER_08 }, in rtl8169_get_mac_version()
2381 { 0x7cf, 0x348, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2382 { 0x7cf, 0x248, RTL_GIGA_MAC_VER_07 }, in rtl8169_get_mac_version()
2383 { 0x7cf, 0x240, RTL_GIGA_MAC_VER_14 }, in rtl8169_get_mac_version()
2384 { 0x7c8, 0x348, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2385 { 0x7c8, 0x248, RTL_GIGA_MAC_VER_09 }, in rtl8169_get_mac_version()
2386 { 0x7c8, 0x340, RTL_GIGA_MAC_VER_10 }, in rtl8169_get_mac_version()
2389 { 0xfc8, 0x980, RTL_GIGA_MAC_VER_06 }, in rtl8169_get_mac_version()
2390 { 0xfc8, 0x180, RTL_GIGA_MAC_VER_05 }, in rtl8169_get_mac_version()
2391 { 0xfc8, 0x100, RTL_GIGA_MAC_VER_04 }, in rtl8169_get_mac_version()
2392 { 0xfc8, 0x040, RTL_GIGA_MAC_VER_03 }, in rtl8169_get_mac_version()
2393 { 0xfc8, 0x008, RTL_GIGA_MAC_VER_02 }, in rtl8169_get_mac_version()
2396 { 0x000, 0x000, RTL_GIGA_MAC_NONE } in rtl8169_get_mac_version()
2445 RTL_W8(tp, EEE_LED, RTL_R8(tp, EEE_LED) & ~0x07); in rtl8168_config_eee_mac()
2447 rtl_eri_set_bits(tp, 0x1b0, 0x0003); in rtl8168_config_eee_mac()
2452 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125a_config_eee_mac()
2453 r8168_mac_ocp_modify(tp, 0xeb62, 0, BIT(2) | BIT(1)); in rtl8125a_config_eee_mac()
2458 r8168_mac_ocp_modify(tp, 0xe040, 0, BIT(1) | BIT(0)); in rtl8125b_config_eee_mac()
2463 rtl_eri_write(tp, 0xe0, ERIAR_MASK_1111, get_unaligned_le32(addr)); in rtl_rar_exgmac_set()
2464 rtl_eri_write(tp, 0xe4, ERIAR_MASK_1111, get_unaligned_le16(addr + 4)); in rtl_rar_exgmac_set()
2465 rtl_eri_write(tp, 0xf0, ERIAR_MASK_1111, get_unaligned_le16(addr) << 16); in rtl_rar_exgmac_set()
2466 rtl_eri_write(tp, 0xf4, ERIAR_MASK_1111, get_unaligned_le32(addr + 2)); in rtl_rar_exgmac_set()
2473 r8168_mac_ocp_write(tp, 0xdd02, 0x807d); in rtl8168h_2_get_adc_bias_ioffset()
2474 data1 = r8168_mac_ocp_read(tp, 0xdd02); in rtl8168h_2_get_adc_bias_ioffset()
2475 data2 = r8168_mac_ocp_read(tp, 0xdd00); in rtl8168h_2_get_adc_bias_ioffset()
2477 ioffset = (data2 >> 1) & 0x7ff8; in rtl8168h_2_get_adc_bias_ioffset()
2478 ioffset |= data2 & 0x0007; in rtl8168h_2_get_adc_bias_ioffset()
2497 pci_write_config_byte(tp->pci_dev, PCI_LATENCY_TIMER, 0x40); in rtl8169_init_phy()
2498 pci_write_config_byte(tp->pci_dev, PCI_CACHE_LINE_SIZE, 0x08); in rtl8169_init_phy()
2499 /* set undocumented MAC Reg C+CR Offset 0x82h */ in rtl8169_init_phy()
2500 RTL_W8(tp, 0x82, 0x01); in rtl8169_init_phy()
2505 tp->pci_dev->subsystem_device == 0xe000) in rtl8169_init_phy()
2506 phy_write_paged(tp->phydev, 0x0001, 0x10, 0xf01b); in rtl8169_init_phy()
2541 return 0; in rtl_set_mac_address()
2574 tp->dirty_tx = tp->cur_tx = tp->cur_rx = 0; in rtl8169_init_ring_indexes()
2589 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); in rtl_jumbo_config()
2599 RTL_W8(tp, MaxTxPacketSize, jumbo ? 0x24 : 0x3f); in rtl_jumbo_config()
2601 r8169_mod_reg8_cond(tp, Config4, BIT(0), jumbo); in rtl_jumbo_config()
2681 return (RTL_R16(tp, IntrMitigate) & 0x0103) == 0x0103; in DECLARE_RTL_COND()
2733 rtl_ephy_write(tp, 0x19, 0xff64); in rtl_prepare_power_down()
2776 val = 0x000fff00; in rtl8169_set_magic_reg()
2778 val = 0x00ffff00; in rtl8169_set_magic_reg()
2783 val |= 0xff; in rtl8169_set_magic_reg()
2785 RTL_W32(tp, 0x7c, val); in rtl8169_set_magic_reg()
2792 u32 mc_filter[2] = { 0xffffffff, 0xffffffff }; in rtl_set_rx_mode()
2808 mc_filter[1] = mc_filter[0] = 0; in rtl_set_rx_mode()
2815 tmp = mc_filter[0]; in rtl_set_rx_mode()
2816 mc_filter[0] = swab32(mc_filter[1]); in rtl_set_rx_mode()
2822 RTL_W32(tp, MAR0 + 0, mc_filter[0]); in rtl_set_rx_mode()
2852 RTL_R32(tp, CSIDR) : ~0; in rtl_csi_read()
2862 #define RTL_GEN3_RELATED_OFF 0x0890 in rtl_disable_zrxdc_timeout()
2863 #define RTL_GEN3_ZRXDC_NONCOMPL 0x1 in rtl_disable_zrxdc_timeout()
2886 /* According to Realtek the value at config space address 0x070f in rtl_set_aspm_entry_latency()
2889 * bit 0..2: L0: 0 = 1us, 1 = 2us .. 6 = 7us, 7 = 7us (no typo) in rtl_set_aspm_entry_latency()
2890 * bit 3..5: L1: 0 = 1us, 1 = 2us .. 6 = 64us, 7 = 64us in rtl_set_aspm_entry_latency()
2892 if (pdev->cfg_size > 0x070f && in rtl_set_aspm_entry_latency()
2893 pci_write_config_byte(pdev, 0x070f, val) == PCIBIOS_SUCCESSFUL) in rtl_set_aspm_entry_latency()
2898 csi = rtl_csi_read(tp, 0x070c) & 0x00ffffff; in rtl_set_aspm_entry_latency()
2899 rtl_csi_write(tp, 0x070c, csi | val << 24); in rtl_set_aspm_entry_latency()
2905 rtl_set_aspm_entry_latency(tp, 0x27); in rtl_set_def_aspm_entry_latency()
2919 while (len-- > 0) { in __rtl_ephy_init()
2958 rtl_eri_set_bits(tp, 0xd4, 0x1f00); in rtl_enable_exit_l1()
2961 rtl_eri_set_bits(tp, 0xd4, 0x0c00); in rtl_enable_exit_l1()
2964 r8168_mac_ocp_modify(tp, 0xc0ac, 0, 0x1f80); in rtl_enable_exit_l1()
2975 rtl_eri_clear_bits(tp, 0xd4, 0x1f00); in rtl_disable_exit_l1()
2978 r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0); in rtl_disable_exit_l1()
3001 rtl_mod_config5(tp, 0, ASPM_en); in rtl_hw_aspm_clkreq_enable()
3009 rtl_mod_config2(tp, 0, ClkReqEn); in rtl_hw_aspm_clkreq_enable()
3017 r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0); in rtl_hw_aspm_clkreq_enable()
3019 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2)); in rtl_hw_aspm_clkreq_enable()
3028 r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0); in rtl_hw_aspm_clkreq_enable()
3041 rtl_mod_config2(tp, ClkReqEn, 0); in rtl_hw_aspm_clkreq_enable()
3044 rtl_mod_config5(tp, ASPM_en, 0); in rtl_hw_aspm_clkreq_enable()
3054 rtl_eri_write(tp, 0xc8, ERIAR_MASK_1111, (rx_stat << 16) | rx_dyn); in rtl_set_fifo_size()
3055 rtl_eri_write(tp, 0xe8, ERIAR_MASK_1111, (tx_stat << 16) | tx_dyn); in rtl_set_fifo_size()
3062 rtl_eri_write(tp, 0xcc, ERIAR_MASK_0001, low); in rtl8168g_set_pause_thresholds()
3063 rtl_eri_write(tp, 0xd0, ERIAR_MASK_0001, high); in rtl8168g_set_pause_thresholds()
3083 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168cp_1()
3084 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168cp_1()
3085 { 0x03, 0, 0x0042 }, in rtl_hw_start_8168cp_1()
3086 { 0x06, 0x0080, 0x0000 }, in rtl_hw_start_8168cp_1()
3087 { 0x07, 0, 0x2000 } in rtl_hw_start_8168cp_1()
3111 RTL_W8(tp, DBG_REG, 0x20); in rtl_hw_start_8168cp_3()
3117 { 0x02, 0x0800, 0x1000 }, in rtl_hw_start_8168c_1()
3118 { 0x03, 0, 0x0002 }, in rtl_hw_start_8168c_1()
3119 { 0x06, 0x0080, 0x0000 } in rtl_hw_start_8168c_1()
3124 RTL_W8(tp, DBG_REG, 0x06 | FIX_NAK_1 | FIX_NAK_2); in rtl_hw_start_8168c_1()
3134 { 0x01, 0, 0x0001 }, in rtl_hw_start_8168c_2()
3135 { 0x03, 0x0400, 0x0020 } in rtl_hw_start_8168c_2()
3162 { 0x0b, 0x0000, 0x0048 }, in rtl_hw_start_8168d_4()
3163 { 0x19, 0x0020, 0x0050 }, in rtl_hw_start_8168d_4()
3164 { 0x0c, 0x0100, 0x0020 }, in rtl_hw_start_8168d_4()
3165 { 0x10, 0x0004, 0x0000 }, in rtl_hw_start_8168d_4()
3178 { 0x00, 0x0200, 0x0100 }, in rtl_hw_start_8168e_1()
3179 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_1()
3180 { 0x06, 0x0002, 0x0001 }, in rtl_hw_start_8168e_1()
3181 { 0x06, 0x0000, 0x0030 }, in rtl_hw_start_8168e_1()
3182 { 0x07, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3183 { 0x00, 0x0000, 0x0020 }, in rtl_hw_start_8168e_1()
3184 { 0x03, 0x5800, 0x2000 }, in rtl_hw_start_8168e_1()
3185 { 0x03, 0x0000, 0x0001 }, in rtl_hw_start_8168e_1()
3186 { 0x01, 0x0800, 0x1000 }, in rtl_hw_start_8168e_1()
3187 { 0x07, 0x0000, 0x4000 }, in rtl_hw_start_8168e_1()
3188 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168e_1()
3189 { 0x19, 0xffff, 0xfe6c }, in rtl_hw_start_8168e_1()
3190 { 0x0a, 0x0000, 0x0040 } in rtl_hw_start_8168e_1()
3203 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_1()
3209 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168e_2()
3210 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168e_2()
3211 { 0x00, 0x0000, 0x0004 }, in rtl_hw_start_8168e_2()
3212 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168e_2()
3219 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168e_2()
3220 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168e_2()
3221 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168e_2()
3222 rtl_eri_set_bits(tp, 0x1d0, BIT(1)); in rtl_hw_start_8168e_2()
3224 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168e_2()
3225 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168e_2()
3226 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x07ff0060); in rtl_hw_start_8168e_2()
3236 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168e_2()
3243 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168f()
3244 rtl_eri_write(tp, 0xb8, ERIAR_MASK_1111, 0x0000); in rtl_hw_start_8168f()
3245 rtl_set_fifo_size(tp, 0x10, 0x10, 0x02, 0x06); in rtl_hw_start_8168f()
3247 rtl_eri_set_bits(tp, 0x1b0, BIT(4)); in rtl_hw_start_8168f()
3248 rtl_eri_set_bits(tp, 0x1d0, BIT(4) | BIT(1)); in rtl_hw_start_8168f()
3249 rtl_eri_write(tp, 0xcc, ERIAR_MASK_1111, 0x00000050); in rtl_hw_start_8168f()
3250 rtl_eri_write(tp, 0xd0, ERIAR_MASK_1111, 0x00000060); in rtl_hw_start_8168f()
3257 rtl_mod_config5(tp, Spi_en, 0); in rtl_hw_start_8168f()
3265 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8168f_1()
3266 { 0x08, 0x0001, 0x0002 }, in rtl_hw_start_8168f_1()
3267 { 0x09, 0x0000, 0x0080 }, in rtl_hw_start_8168f_1()
3268 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8168f_1()
3269 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8168f_1()
3270 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8168f_1()
3281 { 0x06, 0x00c0, 0x0020 }, in rtl_hw_start_8411()
3282 { 0x0f, 0xffff, 0x5200 }, in rtl_hw_start_8411()
3283 { 0x19, 0x0000, 0x0224 }, in rtl_hw_start_8411()
3284 { 0x00, 0x0000, 0x0008 }, in rtl_hw_start_8411()
3285 { 0x0c, 0x3df0, 0x0200 }, in rtl_hw_start_8411()
3296 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168g()
3297 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168g()
3302 rtl_eri_write(tp, 0x2f8, ERIAR_MASK_0011, 0x1d8f); in rtl_hw_start_8168g()
3306 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3307 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168g()
3311 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168g()
3312 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168g()
3320 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_1()
3321 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_1()
3322 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8168g_1()
3323 { 0x19, 0x8000, 0x0000 } in rtl_hw_start_8168g_1()
3333 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8168g_2()
3334 { 0x0c, 0x3ff0, 0x0820 }, in rtl_hw_start_8168g_2()
3335 { 0x19, 0xffff, 0x7c00 }, in rtl_hw_start_8168g_2()
3336 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8168g_2()
3337 { 0x0d, 0xffff, 0x1666 }, in rtl_hw_start_8168g_2()
3338 { 0x00, 0xffff, 0x10a3 }, in rtl_hw_start_8168g_2()
3339 { 0x06, 0xffff, 0xf050 }, in rtl_hw_start_8168g_2()
3340 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8168g_2()
3341 { 0x1d, 0x4000, 0x0000 }, in rtl_hw_start_8168g_2()
3351 /* 0xf800 */ 0xe008, 0xe00a, 0xe00c, 0xe00e, 0xe027, 0xe04f, 0xe05e, 0xe065, in rtl8411b_fix_phy_down()
3352 /* 0xf810 */ 0xc602, 0xbe00, 0x0000, 0xc502, 0xbd00, 0x074c, 0xc302, 0xbb00, in rtl8411b_fix_phy_down()
3353 /* 0xf820 */ 0x080a, 0x6420, 0x48c2, 0x8c20, 0xc516, 0x64a4, 0x49c0, 0xf009, in rtl8411b_fix_phy_down()
3354 /* 0xf830 */ 0x74a2, 0x8ca5, 0x74a0, 0xc50e, 0x9ca2, 0x1c11, 0x9ca0, 0xe006, in rtl8411b_fix_phy_down()
3355 /* 0xf840 */ 0x74f8, 0x48c4, 0x8cf8, 0xc404, 0xbc00, 0xc403, 0xbc00, 0x0bf2, in rtl8411b_fix_phy_down()
3356 /* 0xf850 */ 0x0c0a, 0xe434, 0xd3c0, 0x49d9, 0xf01f, 0xc526, 0x64a5, 0x1400, in rtl8411b_fix_phy_down()
3357 /* 0xf860 */ 0xf007, 0x0c01, 0x8ca5, 0x1c15, 0xc51b, 0x9ca0, 0xe013, 0xc519, in rtl8411b_fix_phy_down()
3358 /* 0xf870 */ 0x74a0, 0x48c4, 0x8ca0, 0xc516, 0x74a4, 0x48c8, 0x48ca, 0x9ca4, in rtl8411b_fix_phy_down()
3359 /* 0xf880 */ 0xc512, 0x1b00, 0x9ba0, 0x1b1c, 0x483f, 0x9ba2, 0x1b04, 0xc508, in rtl8411b_fix_phy_down()
3360 /* 0xf890 */ 0x9ba0, 0xc505, 0xbd00, 0xc502, 0xbd00, 0x0300, 0x051e, 0xe434, in rtl8411b_fix_phy_down()
3361 /* 0xf8a0 */ 0xe018, 0xe092, 0xde20, 0xd3c0, 0xc50f, 0x76a4, 0x49e3, 0xf007, in rtl8411b_fix_phy_down()
3362 /* 0xf8b0 */ 0x49c0, 0xf103, 0xc607, 0xbe00, 0xc606, 0xbe00, 0xc602, 0xbe00, in rtl8411b_fix_phy_down()
3363 /* 0xf8c0 */ 0x0c4c, 0x0c28, 0x0c2c, 0xdc00, 0xc707, 0x1d00, 0x8de2, 0x48c1, in rtl8411b_fix_phy_down()
3364 /* 0xf8d0 */ 0xc502, 0xbd00, 0x00aa, 0xe0c0, 0xc502, 0xbd00, 0x0132 in rtl8411b_fix_phy_down()
3370 for (i = 0; i < ARRAY_SIZE(fix_data); i++) in rtl8411b_fix_phy_down()
3371 __r8168_mac_ocp_write(tp, 0xf800 + 2 * i, fix_data[i]); in rtl8411b_fix_phy_down()
3378 { 0x00, 0x0008, 0x0000 }, in rtl_hw_start_8411_2()
3379 { 0x0c, 0x37d0, 0x0820 }, in rtl_hw_start_8411_2()
3380 { 0x1e, 0x0000, 0x0001 }, in rtl_hw_start_8411_2()
3381 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8411_2()
3382 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8411_2()
3383 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8411_2()
3384 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8411_2()
3385 { 0x06, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3386 { 0x04, 0x0000, 0x0010 }, in rtl_hw_start_8411_2()
3387 { 0x1d, 0x0000, 0x4000 }, in rtl_hw_start_8411_2()
3397 r8168_mac_ocp_write(tp, 0xFC28, 0x0000); in rtl_hw_start_8411_2()
3398 r8168_mac_ocp_write(tp, 0xFC2A, 0x0000); in rtl_hw_start_8411_2()
3399 r8168_mac_ocp_write(tp, 0xFC2C, 0x0000); in rtl_hw_start_8411_2()
3400 r8168_mac_ocp_write(tp, 0xFC2E, 0x0000); in rtl_hw_start_8411_2()
3401 r8168_mac_ocp_write(tp, 0xFC30, 0x0000); in rtl_hw_start_8411_2()
3402 r8168_mac_ocp_write(tp, 0xFC32, 0x0000); in rtl_hw_start_8411_2()
3403 r8168_mac_ocp_write(tp, 0xFC34, 0x0000); in rtl_hw_start_8411_2()
3404 r8168_mac_ocp_write(tp, 0xFC36, 0x0000); in rtl_hw_start_8411_2()
3406 r8168_mac_ocp_write(tp, 0xFC26, 0x0000); in rtl_hw_start_8411_2()
3410 r8168_mac_ocp_write(tp, 0xFC26, 0x8000); in rtl_hw_start_8411_2()
3412 r8168_mac_ocp_write(tp, 0xFC2A, 0x0743); in rtl_hw_start_8411_2()
3413 r8168_mac_ocp_write(tp, 0xFC2C, 0x0801); in rtl_hw_start_8411_2()
3414 r8168_mac_ocp_write(tp, 0xFC2E, 0x0BE9); in rtl_hw_start_8411_2()
3415 r8168_mac_ocp_write(tp, 0xFC30, 0x02FD); in rtl_hw_start_8411_2()
3416 r8168_mac_ocp_write(tp, 0xFC32, 0x0C25); in rtl_hw_start_8411_2()
3417 r8168_mac_ocp_write(tp, 0xFC34, 0x00A9); in rtl_hw_start_8411_2()
3418 r8168_mac_ocp_write(tp, 0xFC36, 0x012D); in rtl_hw_start_8411_2()
3424 { 0x1e, 0x0800, 0x0001 }, in rtl_hw_start_8168h_1()
3425 { 0x1d, 0x0000, 0x0800 }, in rtl_hw_start_8168h_1()
3426 { 0x05, 0xffff, 0x2089 }, in rtl_hw_start_8168h_1()
3427 { 0x06, 0xffff, 0x5881 }, in rtl_hw_start_8168h_1()
3428 { 0x04, 0xffff, 0x854a }, in rtl_hw_start_8168h_1()
3429 { 0x01, 0xffff, 0x068b } in rtl_hw_start_8168h_1()
3435 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168h_1()
3436 rtl8168g_set_pause_thresholds(tp, 0x38, 0x48); in rtl_hw_start_8168h_1()
3442 rtl_eri_set_bits(tp, 0xdc, 0x001c); in rtl_hw_start_8168h_1()
3444 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168h_1()
3448 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3449 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168h_1()
3458 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8168h_1()
3462 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8168h_1()
3463 if (rg_saw_cnt > 0) { in rtl_hw_start_8168h_1()
3467 sw_cnt_1ms_ini &= 0x0fff; in rtl_hw_start_8168h_1()
3468 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8168h_1()
3471 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8168h_1()
3472 r8168_mac_ocp_modify(tp, 0xe052, 0x6000, 0x8008); in rtl_hw_start_8168h_1()
3473 r8168_mac_ocp_modify(tp, 0xe0d6, 0x01ff, 0x017f); in rtl_hw_start_8168h_1()
3474 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8168h_1()
3476 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8168h_1()
3477 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8168h_1()
3478 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8168h_1()
3479 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8168h_1()
3486 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8168ep()
3487 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8168ep()
3493 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8168ep()
3497 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3498 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8168ep()
3502 rtl_w0w1_eri(tp, 0x2fc, 0x01, 0x06); in rtl_hw_start_8168ep()
3512 { 0x00, 0x0000, 0x0080 }, in rtl_hw_start_8168ep_3()
3513 { 0x0d, 0x0100, 0x0200 }, in rtl_hw_start_8168ep_3()
3514 { 0x19, 0x8021, 0x0000 }, in rtl_hw_start_8168ep_3()
3515 { 0x1e, 0x0000, 0x2000 }, in rtl_hw_start_8168ep_3()
3525 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x0271); in rtl_hw_start_8168ep_3()
3526 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8168ep_3()
3527 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8168ep_3()
3533 { 0x19, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3534 { 0x59, 0x0040, 0x1100 }, in rtl_hw_start_8117()
3541 rtl_set_fifo_size(tp, 0x08, 0x10, 0x02, 0x06); in rtl_hw_start_8117()
3542 rtl8168g_set_pause_thresholds(tp, 0x2f, 0x5f); in rtl_hw_start_8117()
3548 rtl_eri_set_bits(tp, 0xd4, 0x0010); in rtl_hw_start_8117()
3550 rtl_eri_write(tp, 0x5f0, ERIAR_MASK_0011, 0x4f87); in rtl_hw_start_8117()
3554 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3555 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8117()
3564 rtl_eri_clear_bits(tp, 0x1b0, BIT(12)); in rtl_hw_start_8117()
3568 rg_saw_cnt = phy_read_paged(tp->phydev, 0x0c42, 0x13) & 0x3fff; in rtl_hw_start_8117()
3569 if (rg_saw_cnt > 0) { in rtl_hw_start_8117()
3572 sw_cnt_1ms_ini = (16000000 / rg_saw_cnt) & 0x0fff; in rtl_hw_start_8117()
3573 r8168_mac_ocp_modify(tp, 0xd412, 0x0fff, sw_cnt_1ms_ini); in rtl_hw_start_8117()
3576 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0070); in rtl_hw_start_8117()
3577 r8168_mac_ocp_write(tp, 0xea80, 0x0003); in rtl_hw_start_8117()
3578 r8168_mac_ocp_modify(tp, 0xe052, 0x0000, 0x0009); in rtl_hw_start_8117()
3579 r8168_mac_ocp_modify(tp, 0xd420, 0x0fff, 0x047f); in rtl_hw_start_8117()
3581 r8168_mac_ocp_write(tp, 0xe63e, 0x0001); in rtl_hw_start_8117()
3582 r8168_mac_ocp_write(tp, 0xe63e, 0x0000); in rtl_hw_start_8117()
3583 r8168_mac_ocp_write(tp, 0xc094, 0x0000); in rtl_hw_start_8117()
3584 r8168_mac_ocp_write(tp, 0xc09e, 0x0000); in rtl_hw_start_8117()
3593 { 0x01, 0, 0x6e65 }, in rtl_hw_start_8102e_1()
3594 { 0x02, 0, 0x091f }, in rtl_hw_start_8102e_1()
3595 { 0x03, 0, 0xc2f9 }, in rtl_hw_start_8102e_1()
3596 { 0x06, 0, 0xafb5 }, in rtl_hw_start_8102e_1()
3597 { 0x07, 0, 0x0e00 }, in rtl_hw_start_8102e_1()
3598 { 0x19, 0, 0xec80 }, in rtl_hw_start_8102e_1()
3599 { 0x01, 0, 0x2e65 }, in rtl_hw_start_8102e_1()
3600 { 0x01, 0, 0x6e65 } in rtl_hw_start_8102e_1()
3631 rtl_ephy_write(tp, 0x03, 0xc2f9); in rtl_hw_start_8102e_3()
3637 { 0x01, 0xffff, 0x6fe5 }, in rtl_hw_start_8401()
3638 { 0x03, 0xffff, 0x0599 }, in rtl_hw_start_8401()
3639 { 0x06, 0xffff, 0xaf25 }, in rtl_hw_start_8401()
3640 { 0x07, 0xffff, 0x8e68 }, in rtl_hw_start_8401()
3650 { 0x07, 0, 0x4000 }, in rtl_hw_start_8105e_1()
3651 { 0x19, 0, 0x0200 }, in rtl_hw_start_8105e_1()
3652 { 0x19, 0, 0x0020 }, in rtl_hw_start_8105e_1()
3653 { 0x1e, 0, 0x2000 }, in rtl_hw_start_8105e_1()
3654 { 0x03, 0, 0x0001 }, in rtl_hw_start_8105e_1()
3655 { 0x19, 0, 0x0100 }, in rtl_hw_start_8105e_1()
3656 { 0x19, 0, 0x0004 }, in rtl_hw_start_8105e_1()
3657 { 0x0a, 0, 0x0020 } in rtl_hw_start_8105e_1()
3661 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8105e_1()
3664 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) & ~0x010000); in rtl_hw_start_8105e_1()
3677 rtl_ephy_write(tp, 0x1e, rtl_ephy_read(tp, 0x1e) | 0x8000); in rtl_hw_start_8105e_2()
3683 { 0x19, 0xffff, 0xff64 }, in rtl_hw_start_8402()
3684 { 0x1e, 0, 0x4000 } in rtl_hw_start_8402()
3690 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8402()
3696 rtl_set_fifo_size(tp, 0x00, 0x00, 0x02, 0x06); in rtl_hw_start_8402()
3698 rtl_eri_write(tp, 0xc0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3699 rtl_eri_write(tp, 0xb8, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3700 rtl_w0w1_eri(tp, 0x0d4, 0x0e00, 0xff00); in rtl_hw_start_8402()
3703 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8402()
3711 RTL_W32(tp, FuncEvent, RTL_R32(tp, FuncEvent) | 0x002800); in rtl_hw_start_8106()
3718 rtl_set_aspm_entry_latency(tp, 0x2f); in rtl_hw_start_8106()
3720 rtl_eri_write(tp, 0x1d0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3723 rtl_eri_write(tp, 0x1b0, ERIAR_MASK_0011, 0x0000); in rtl_hw_start_8106()
3730 return r8168_mac_ocp_read(tp, 0xe00e) & BIT(13); in DECLARE_RTL_COND()
3737 RTL_W16(tp, 0x382, 0x221b); in rtl_hw_start_8125_common()
3738 RTL_W32(tp, RSS_CTRL_8125, 0); in rtl_hw_start_8125_common()
3739 RTL_W16(tp, Q_NUM_CTRL_8125, 0); in rtl_hw_start_8125_common()
3742 r8168_mac_ocp_modify(tp, 0xd40a, 0x0010, 0x0000); in rtl_hw_start_8125_common()
3744 RTL_W8(tp, Config1, RTL_R8(tp, Config1) & ~0x10); in rtl_hw_start_8125_common()
3746 r8168_mac_ocp_write(tp, 0xc140, 0xffff); in rtl_hw_start_8125_common()
3747 r8168_mac_ocp_write(tp, 0xc142, 0xffff); in rtl_hw_start_8125_common()
3749 r8168_mac_ocp_modify(tp, 0xd3e2, 0x0fff, 0x03a9); in rtl_hw_start_8125_common()
3750 r8168_mac_ocp_modify(tp, 0xd3e4, 0x00ff, 0x0000); in rtl_hw_start_8125_common()
3751 r8168_mac_ocp_modify(tp, 0xe860, 0x0000, 0x0080); in rtl_hw_start_8125_common()
3754 r8168_mac_ocp_modify(tp, 0xeb58, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3758 RTL_W8(tp, 0xD8, RTL_R8(tp, 0xD8) & ~0x02); in rtl_hw_start_8125_common()
3762 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0400); in rtl_hw_start_8125_common()
3764 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0200); in rtl_hw_start_8125_common()
3766 r8168_mac_ocp_modify(tp, 0xe614, 0x0700, 0x0300); in rtl_hw_start_8125_common()
3769 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0000); in rtl_hw_start_8125_common()
3771 r8168_mac_ocp_modify(tp, 0xe63e, 0x0c30, 0x0020); in rtl_hw_start_8125_common()
3773 r8168_mac_ocp_modify(tp, 0xc0b4, 0x0000, 0x000c); in rtl_hw_start_8125_common()
3774 r8168_mac_ocp_modify(tp, 0xeb6a, 0x00ff, 0x0033); in rtl_hw_start_8125_common()
3775 r8168_mac_ocp_modify(tp, 0xeb50, 0x03e0, 0x0040); in rtl_hw_start_8125_common()
3776 r8168_mac_ocp_modify(tp, 0xe056, 0x00f0, 0x0030); in rtl_hw_start_8125_common()
3777 r8168_mac_ocp_modify(tp, 0xe040, 0x1000, 0x0000); in rtl_hw_start_8125_common()
3778 r8168_mac_ocp_modify(tp, 0xea1c, 0x0003, 0x0001); in rtl_hw_start_8125_common()
3781 r8168_mac_ocp_modify(tp, 0xea1c, 0x0300, 0x0000); in rtl_hw_start_8125_common()
3783 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3784 r8168_mac_ocp_modify(tp, 0xe0c0, 0x4f0f, 0x4403); in rtl_hw_start_8125_common()
3785 r8168_mac_ocp_modify(tp, 0xe052, 0x0080, 0x0068); in rtl_hw_start_8125_common()
3786 r8168_mac_ocp_modify(tp, 0xd430, 0x0fff, 0x047f); in rtl_hw_start_8125_common()
3788 r8168_mac_ocp_modify(tp, 0xea1c, 0x0004, 0x0000); in rtl_hw_start_8125_common()
3789 r8168_mac_ocp_modify(tp, 0xeb54, 0x0000, 0x0001); in rtl_hw_start_8125_common()
3791 r8168_mac_ocp_modify(tp, 0xeb54, 0x0001, 0x0000); in rtl_hw_start_8125_common()
3792 RTL_W16(tp, 0x1880, RTL_R16(tp, 0x1880) & ~0x0030); in rtl_hw_start_8125_common()
3794 r8168_mac_ocp_write(tp, 0xe098, 0xc302); in rtl_hw_start_8125_common()
3809 { 0x04, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3810 { 0x0a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3811 { 0x23, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3812 { 0x20, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3813 { 0x21, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3814 { 0x29, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3816 { 0x44, 0xffff, 0xd000 }, in rtl_hw_start_8125a_2()
3817 { 0x4a, 0xffff, 0x8653 }, in rtl_hw_start_8125a_2()
3818 { 0x63, 0xffff, 0xab66 }, in rtl_hw_start_8125a_2()
3819 { 0x60, 0xffff, 0x9455 }, in rtl_hw_start_8125a_2()
3820 { 0x61, 0xffff, 0x99ff }, in rtl_hw_start_8125a_2()
3821 { 0x69, 0xffff, 0xfe04 }, in rtl_hw_start_8125a_2()
3832 { 0x0b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3833 { 0x1e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3834 { 0x4b, 0xffff, 0xa908 }, in rtl_hw_start_8125b()
3835 { 0x5e, 0xffff, 0x20eb }, in rtl_hw_start_8125b()
3836 { 0x22, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3837 { 0x62, 0x0030, 0x0020 }, in rtl_hw_start_8125b()
3914 RTL_W8(tp, INT_CFG0_8125, 0x00); in rtl_hw_start_8125()
3922 for (i = 0xa00; i < 0xb00; i += 4) in rtl_hw_start_8125()
3923 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3928 for (i = 0xa00; i < 0xa80; i += 4) in rtl_hw_start_8125()
3929 RTL_W32(tp, i, 0); in rtl_hw_start_8125()
3930 RTL_W16(tp, INT_CFG1_8125, 0x0000); in rtl_hw_start_8125()
3937 r8168_mac_ocp_modify(tp, 0xea84, 0, BIT(1) | BIT(0)); in rtl_hw_start_8125()
3952 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8168()
3970 RTL_W16(tp, IntrMitigate, 0x0000); in rtl_hw_start_8169()
4017 return 0; in rtl8169_change_mtu()
4024 desc->opts2 = 0; in rtl8169_mark_to_asic()
4042 mapping = dma_map_page(d, data, 0, R8169_RX_BUF_SIZE, DMA_FROM_DEVICE); in rtl8169_alloc_rx_data()
4059 for (i = 0; i < NUM_RX_DESC && tp->Rx_databuff[i]; i++) { in rtl8169_rx_clear()
4065 tp->RxDescArray[i].addr = 0; in rtl8169_rx_clear()
4066 tp->RxDescArray[i].opts1 = 0; in rtl8169_rx_clear()
4074 for (i = 0; i < NUM_RX_DESC; i++) { in rtl8169_rx_fill()
4088 return 0; in rtl8169_rx_fill()
4095 memset(tp->tx_skb, 0, sizeof(tp->tx_skb)); in rtl8169_init_ring()
4096 memset(tp->Rx_databuff, 0, sizeof(tp->Rx_databuff)); in rtl8169_init_ring()
4108 memset(desc, 0, sizeof(*desc)); in rtl8169_unmap_tx_skb()
4109 memset(tx_skb, 0, sizeof(*tx_skb)); in rtl8169_unmap_tx_skb()
4117 for (i = 0; i < n; i++) { in rtl8169_tx_clear_range()
4183 for (i = 0; i < NUM_RX_DESC; i++) in rtl_reset_work()
4217 opts1 = opts[0] | len; in rtl8169_tx_map()
4226 return 0; in rtl8169_tx_map()
4235 for (cur_frag = 0; cur_frag < info->nr_frags; cur_frag++) { in rtl8169_xmit_frags()
4246 return 0; in rtl8169_xmit_frags()
4277 unsigned int padto = 0, len = skb->len; in rtl8125_quirk_udp_padto()
4304 unsigned int padto = 0; in rtl_quirk_packet_padto()
4331 opts[0] |= TD_LSO; in rtl8169_tso_csum_v1()
4332 opts[0] |= mss << TD0_MSS_SHIFT; in rtl8169_tso_csum_v1()
4337 opts[0] |= TD0_IP_CS | TD0_TCP_CS; in rtl8169_tso_csum_v1()
4339 opts[0] |= TD0_IP_CS | TD0_UDP_CS; in rtl8169_tso_csum_v1()
4353 opts[0] |= TD1_GTSENV4; in rtl8169_tso_csum_v2()
4355 if (skb_cow_head(skb, 0)) in rtl8169_tso_csum_v2()
4359 opts[0] |= TD1_GTSENV6; in rtl8169_tso_csum_v2()
4364 opts[0] |= skb_transport_offset(skb) << GTTCPHO_SHIFT; in rtl8169_tso_csum_v2()
4423 RTL_W16(tp, TxPoll_8125, BIT(0)); in rtl8169_doorbell()
4446 opts[0] = 0; in rtl8169_start_xmit()
4484 stop_queue = !netif_subqueue_maybe_stop(dev, 0, rtl_tx_slots_avail(tp), in rtl8169_start_xmit()
4572 netdev_err(dev, "PCI error (cmd = 0x%04x, status_errs = 0x%04x)\n", in rtl8169_pcierr_interrupt()
4581 unsigned int dirty_tx, bytes_compl = 0, pkts_compl = 0; in rtl_tx()
4609 netif_subqueue_completed_wake(dev, 0, pkts_compl, bytes_compl, in rtl_tx()
4645 for (count = 0; count < budget; count++, tp->cur_rx++) { in rtl_rx()
4679 pkt_size = status & GENMASK(13, 0); in rtl_rx()
4731 if ((status & 0xffff) == 0xffff || !(status & tp->irq_mask)) in rtl8169_interrupt()
4760 if (RTL_R32(tp, TxConfig) == ~0) { in rtl_task()
4762 if (ret < 0) { in rtl_task()
4834 return 0; in r8169_phy_connect()
4898 return 0; in rtl8169_close()
4934 if (retval < 0) in rtl_open()
4941 if (retval < 0) in rtl_open()
5027 return 0; in rtl8169_runtime_resume()
5040 return 0; in rtl8169_suspend()
5063 return 0; in rtl8169_runtime_suspend()
5071 return 0; in rtl8169_runtime_suspend()
5189 value = rtl_eri_read(tp, 0xe0); in rtl_read_mac_address()
5191 value = rtl_eri_read(tp, 0xe4); in rtl_read_mac_address()
5212 if (phyaddr > 0) in r8169_mdio_read_reg()
5223 if (phyaddr > 0) in r8169_mdio_write_reg()
5228 return 0; in r8169_mdio_write_reg()
5236 if (addr > 0) in r8169_mdio_read_reg_c45()
5242 return 0; in r8169_mdio_read_reg_c45()
5250 if (addr > 0 || devnum != MDIO_MMD_VEND2 || regnum <= MDIO_STAT2) in r8169_mdio_write_reg_c45()
5255 return 0; in r8169_mdio_write_reg_c45()
5271 r8169_mdio_write(tp, 0x1f, 0); in r8169_mdio_register()
5280 new_bus->irq[0] = PHY_MAC_INTERRUPT; in r8169_mdio_register()
5297 tp->phydev = mdiobus_get_phy(new_bus, 0); in r8169_mdio_register()
5304 …dev_err(&pdev->dev, "no dedicated PHY driver found for PHY ID 0x%08x, maybe realtek.ko needs to be… in r8169_mdio_register()
5323 return 0; in r8169_mdio_register()
5334 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8168g()
5337 r8168_mac_ocp_modify(tp, 0xe8de, 0, BIT(15)); in rtl_hw_init_8168g()
5349 r8168_mac_ocp_modify(tp, 0xe8de, BIT(14), 0); in rtl_hw_init_8125()
5352 r8168_mac_ocp_write(tp, 0xc0aa, 0x07d0); in rtl_hw_init_8125()
5353 r8168_mac_ocp_write(tp, 0xc0a6, 0x0150); in rtl_hw_init_8125()
5354 r8168_mac_ocp_write(tp, 0xc01e, 0x5555); in rtl_hw_init_8125()
5379 return 0; in rtl_jumbo_max()
5429 r8168_mac_ocp_read(tp, 0xc0b2) & 0xf) in rtl_aspm_is_safe()
5453 tp->supports_gmii = ent->driver_data == RTL_CFG_NO_GBIT ? 0 : 1; in rtl_init_one()
5466 if (rc < 0) in rtl_init_one()
5469 if (pcim_set_mwi(pdev) < 0) in rtl_init_one()
5474 if (region < 0) in rtl_init_one()
5483 if (txconfig == ~0U) in rtl_init_one()
5486 xid = (txconfig >> 20) & 0xfcf; in rtl_init_one()
5500 rc = 0; in rtl_init_one()
5523 if (rc < 0) in rtl_init_one()
5526 tp->irq = pci_irq_vector(pdev, 0); in rtl_init_one()
5641 return 0; in rtl_init_one()