Lines Matching +full:super +full:- +full:frames
1 // SPDX-License-Identifier: GPL-2.0+
7 * https://github.com/microchip-ung/sparx-5_reginfo
17 #define SUPER_VCAP_BLK_SIZE 3072 /* addresses per Super VCAP block */
50 .vtype = VCAP_TYPE_IS0, /* CLM-0 */
56 .last_cid = SPARX5_VCAP_CID_IS0_L2 - 1,
57 .blockno = 8, /* Maps block 8-9 */
62 .vtype = VCAP_TYPE_IS0, /* CLM-1 */
68 .last_cid = SPARX5_VCAP_CID_IS0_L4 - 1,
69 .blockno = 6, /* Maps block 6-7 */
74 .vtype = VCAP_TYPE_IS0, /* CLM-2 */
81 .blockno = 4, /* Maps block 4-5 */
86 .vtype = VCAP_TYPE_IS2, /* IS2-0 */
92 .last_cid = SPARX5_VCAP_CID_IS2_L2 - 1,
93 .blockno = 0, /* Maps block 0-1 */
98 .vtype = VCAP_TYPE_IS2, /* IS2-1 */
105 .blockno = 2, /* Maps block 2-3 */
157 fname, sparx5_vcaps[admin->vtype].name); in sparx5_vcap_type_err()
160 /* Await the super VCAP completion of the current operation */
195 u32 size = count - 1; in _sparx5_vcap_range_init()
197 switch (admin->vtype) { in _sparx5_vcap_range_init()
251 _sparx5_vcap_range_init(sparx5, admin, admin->first_valid_addr, in sparx5_vcap_block_init()
252 admin->last_valid_addr - in sparx5_vcap_block_init()
253 admin->first_valid_addr); in sparx5_vcap_block_init()
262 return vcap_keyset_name(port->sparx5->vcap_ctrl, keyset); in sparx5_vcap_keyset_name()
268 return (rule->vcap_chain_id >= SPARX5_VCAP_CID_IS0_L0 && in sparx5_vcap_is0_is_first_chain()
269 rule->vcap_chain_id < SPARX5_VCAP_CID_IS0_L1) || in sparx5_vcap_is0_is_first_chain()
270 ((rule->vcap_chain_id >= SPARX5_VCAP_CID_IS0_L2 && in sparx5_vcap_is0_is_first_chain()
271 rule->vcap_chain_id < SPARX5_VCAP_CID_IS0_L3)) || in sparx5_vcap_is0_is_first_chain()
272 ((rule->vcap_chain_id >= SPARX5_VCAP_CID_IS0_L4 && in sparx5_vcap_is0_is_first_chain()
273 rule->vcap_chain_id < SPARX5_VCAP_CID_IS0_L5)); in sparx5_vcap_is0_is_first_chain()
279 return (rule->vcap_chain_id >= SPARX5_VCAP_CID_IS2_L0 && in sparx5_vcap_is2_is_first_chain()
280 rule->vcap_chain_id < SPARX5_VCAP_CID_IS2_L1) || in sparx5_vcap_is2_is_first_chain()
281 ((rule->vcap_chain_id >= SPARX5_VCAP_CID_IS2_L2 && in sparx5_vcap_is2_is_first_chain()
282 rule->vcap_chain_id < SPARX5_VCAP_CID_IS2_L3)); in sparx5_vcap_is2_is_first_chain()
287 return (rule->vcap_chain_id >= SPARX5_VCAP_CID_ES2_L0 && in sparx5_vcap_es2_is_first_chain()
288 rule->vcap_chain_id < SPARX5_VCAP_CID_ES2_L1); in sparx5_vcap_es2_is_first_chain()
299 range = port->portno / BITS_PER_TYPE(u32); in sparx5_vcap_add_ingress_range_port_mask()
300 /* Port bit set to match-any */ in sparx5_vcap_add_ingress_range_port_mask()
301 port_mask = ~BIT(port->portno % BITS_PER_TYPE(u32)); in sparx5_vcap_add_ingress_range_port_mask()
315 /* Port bit set to match-any */ in sparx5_vcap_add_wide_port_mask()
318 range = port->portno / BITS_PER_BYTE; in sparx5_vcap_add_wide_port_mask()
319 port_mask.mask[range] = ~BIT(port->portno % BITS_PER_BYTE); in sparx5_vcap_add_wide_port_mask()
331 * 0-2: Physical/Logical egress port number 0-31, 32–63, 64. in sparx5_vcap_add_egress_range_port_mask()
332 * 3-5: Virtual Interface Number 0-31, 32-63, 64. in sparx5_vcap_add_egress_range_port_mask()
333 * 6: CPU queue Number 0-7. in sparx5_vcap_add_egress_range_port_mask()
335 * Use physical/logical port ranges (0-2) in sparx5_vcap_add_egress_range_port_mask()
337 range = port->portno / BITS_PER_TYPE(u32); in sparx5_vcap_add_egress_range_port_mask()
338 /* Port bit set to match-any */ in sparx5_vcap_add_egress_range_port_mask()
339 port_mask = ~BIT(port->portno % BITS_PER_TYPE(u32)); in sparx5_vcap_add_egress_range_port_mask()
411 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_is0_get_port_keysets()
412 int portno = port->portno; in sparx5_vcap_is0_get_port_keysets()
465 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_is2_get_port_keysets()
466 int portno = port->portno; in sparx5_vcap_is2_get_port_keysets()
552 /* IS2 non-classified frames generate MAC_ETYPE */ in sparx5_vcap_is2_get_port_keysets()
594 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_es0_get_port_keysets()
595 int portno = port->portno; in sparx5_vcap_es0_get_port_keysets()
619 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_es2_get_port_keysets()
620 int portno = port->portno; in sparx5_vcap_es2_get_port_keysets()
682 int lookup, err = -EINVAL; in sparx5_vcap_get_port_keyset()
685 switch (admin->vtype) { in sparx5_vcap_get_port_keyset()
706 sparx5_vcap_type_err(port->sparx5, admin, __func__); in sparx5_vcap_get_port_keyset()
718 switch (admin->vtype) { in sparx5_vcap_is_known_etype()
755 if (!kslist || kslist->cnt == 0) in sparx5_vcap_validate_keyset()
762 switch (admin->vtype) { in sparx5_vcap_validate_keyset()
764 lookup = sparx5_vcap_is0_cid_to_lookup(rule->vcap_chain_id); in sparx5_vcap_validate_keyset()
769 lookup = sparx5_vcap_is2_cid_to_lookup(rule->vcap_chain_id); in sparx5_vcap_validate_keyset()
777 lookup = sparx5_vcap_es2_cid_to_lookup(rule->vcap_chain_id); in sparx5_vcap_validate_keyset()
783 sparx5_vcap_type_err(port->sparx5, admin, __func__); in sparx5_vcap_validate_keyset()
788 for (idx = 0; idx < kslist->cnt; ++idx) in sparx5_vcap_validate_keyset()
790 if (kslist->keysets[idx] == keysets[jdx]) in sparx5_vcap_validate_keyset()
791 return kslist->keysets[idx]; in sparx5_vcap_validate_keyset()
795 sparx5_vcap_keyset_name(ndev, kslist->keysets[0])); in sparx5_vcap_validate_keyset()
797 return -ENOENT; in sparx5_vcap_validate_keyset()
809 if (field && field->width == SPX5_PORTS) in sparx5_vcap_ingress_add_default_fields()
811 else if (field && field->width == BITS_PER_TYPE(u32)) in sparx5_vcap_ingress_add_default_fields()
816 sparx5_vcap_keyset_name(ndev, rule->keyset)); in sparx5_vcap_ingress_add_default_fields()
818 if (admin->vtype == VCAP_TYPE_IS0) in sparx5_vcap_ingress_add_default_fields()
838 vcap_rule_add_key_u32(rule, VCAP_KF_IF_EGR_PORT_NO, port->portno, ~0); in sparx5_vcap_es0_add_default_fields()
839 /* Match untagged frames if there was no VLAN key */ in sparx5_vcap_es0_add_default_fields()
875 switch (admin->vtype) { in sparx5_vcap_add_default_fields()
888 sparx5_vcap_type_err(port->sparx5, admin, __func__); in sparx5_vcap_add_default_fields()
896 memset(admin->cache.keystream, 0, STREAMSIZE); in sparx5_vcap_cache_erase()
897 memset(admin->cache.maskstream, 0, STREAMSIZE); in sparx5_vcap_cache_erase()
898 memset(admin->cache.actionstream, 0, STREAMSIZE); in sparx5_vcap_cache_erase()
899 memset(&admin->cache.counter, 0, sizeof(admin->cache.counter)); in sparx5_vcap_cache_erase()
911 keystr = &admin->cache.keystream[start]; in sparx5_vcap_is0_cache_write()
912 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_is0_cache_write()
913 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_is0_cache_write()
918 /* Avoid 'match-off' by setting value & mask */ in sparx5_vcap_is0_cache_write()
939 spx5_wr(admin->cache.counter, sparx5, in sparx5_vcap_is0_cache_write()
952 keystr = &admin->cache.keystream[start]; in sparx5_vcap_is2_cache_write()
953 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_is2_cache_write()
954 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_is2_cache_write()
959 /* Avoid 'match-off' by setting value & mask */ in sparx5_vcap_is2_cache_write()
980 if (admin->vinst == 0) in sparx5_vcap_is2_cache_write()
981 spx5_wr(admin->cache.counter, sparx5, in sparx5_vcap_is2_cache_write()
984 spx5_wr(admin->cache.counter, sparx5, in sparx5_vcap_is2_cache_write()
986 spx5_wr(admin->cache.sticky, sparx5, in sparx5_vcap_is2_cache_write()
995 mutex_lock(&sparx5->queue_stats_lock); in sparx5_es0_write_esdx_counter()
997 spx5_wr(admin->cache.counter, sparx5, in sparx5_es0_write_esdx_counter()
1000 mutex_unlock(&sparx5->queue_stats_lock); in sparx5_es0_write_esdx_counter()
1012 keystr = &admin->cache.keystream[start]; in sparx5_vcap_es0_cache_write()
1013 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_es0_cache_write()
1014 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_es0_cache_write()
1019 /* Avoid 'match-off' by setting value & mask */ in sparx5_vcap_es0_cache_write()
1039 spx5_wr(admin->cache.counter, sparx5, VCAP_ES0_VCAP_CNT_DAT(0)); in sparx5_vcap_es0_cache_write()
1053 keystr = &admin->cache.keystream[start]; in sparx5_vcap_es2_cache_write()
1054 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_es2_cache_write()
1055 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_es2_cache_write()
1060 /* Avoid 'match-off' by setting value & mask */ in sparx5_vcap_es2_cache_write()
1081 spx5_wr(admin->cache.counter, sparx5, EACL_ES2_CNT(start)); in sparx5_vcap_es2_cache_write()
1082 spx5_wr(admin->cache.sticky, sparx5, VCAP_ES2_VCAP_CNT_DAT(0)); in sparx5_vcap_es2_cache_write()
1094 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_cache_write()
1096 switch (admin->vtype) { in sparx5_vcap_cache_write()
1124 keystr = &admin->cache.keystream[start]; in sparx5_vcap_is0_cache_read()
1125 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_is0_cache_read()
1126 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_is0_cache_read()
1143 admin->cache.counter = in sparx5_vcap_is0_cache_read()
1145 admin->cache.sticky = in sparx5_vcap_is0_cache_read()
1159 keystr = &admin->cache.keystream[start]; in sparx5_vcap_is2_cache_read()
1160 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_is2_cache_read()
1161 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_is2_cache_read()
1179 if (admin->vinst == 0) in sparx5_vcap_is2_cache_read()
1180 admin->cache.counter = in sparx5_vcap_is2_cache_read()
1183 admin->cache.counter = in sparx5_vcap_is2_cache_read()
1185 admin->cache.sticky = in sparx5_vcap_is2_cache_read()
1196 mutex_lock(&sparx5->queue_stats_lock); in sparx5_es0_read_esdx_counter()
1200 mutex_unlock(&sparx5->queue_stats_lock); in sparx5_es0_read_esdx_counter()
1202 admin->cache.counter = counter; in sparx5_es0_read_esdx_counter()
1214 keystr = &admin->cache.keystream[start]; in sparx5_vcap_es0_cache_read()
1215 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_es0_cache_read()
1216 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_es0_cache_read()
1233 admin->cache.counter = in sparx5_vcap_es0_cache_read()
1235 admin->cache.sticky = admin->cache.counter; in sparx5_vcap_es0_cache_read()
1249 keystr = &admin->cache.keystream[start]; in sparx5_vcap_es2_cache_read()
1250 mskstr = &admin->cache.maskstream[start]; in sparx5_vcap_es2_cache_read()
1251 actstr = &admin->cache.actionstream[start]; in sparx5_vcap_es2_cache_read()
1269 admin->cache.counter = in sparx5_vcap_es2_cache_read()
1271 admin->cache.sticky = in sparx5_vcap_es2_cache_read()
1284 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_cache_read()
1286 switch (admin->vtype) { in sparx5_vcap_cache_read()
1311 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_range_init()
1379 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_update()
1381 switch (admin->vtype) { in sparx5_vcap_update()
1463 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_move()
1468 mv_size = count - 1; in sparx5_vcap_move()
1470 mv_num_pos = offset - 1; in sparx5_vcap_move()
1473 mv_num_pos = -offset - 1; in sparx5_vcap_move()
1477 switch (admin->vtype) { in sparx5_vcap_move()
1523 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_is0_set_port_keyset()
1524 int portno = port->portno; in sparx5_vcap_is0_set_port_keyset()
1612 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_is2_set_port_keyset()
1613 int portno = port->portno; in sparx5_vcap_is2_set_port_keyset()
1705 struct sparx5 *sparx5 = port->sparx5; in sparx5_vcap_es2_set_port_keyset()
1706 int portno = port->portno; in sparx5_vcap_es2_set_port_keyset()
1745 switch (admin->vtype) { in sparx5_vcap_set_port_keyset()
1771 sparx5_vcap_type_err(port->sparx5, admin, __func__); in sparx5_vcap_set_port_keyset()
1780 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_vcap_is0_port_key_selection()
1791 for (lookup = 0; lookup < admin->lookups; ++lookup) { in sparx5_vcap_is0_port_key_selection()
1792 for (portno = 0; portno < consts->n_ports; ++portno) { in sparx5_vcap_is0_port_key_selection()
1807 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_vcap_is2_port_key_selection()
1817 for (lookup = 0; lookup < admin->lookups; ++lookup) { in sparx5_vcap_is2_port_key_selection()
1818 for (portno = 0; portno < consts->n_ports; ++portno) { in sparx5_vcap_is2_port_key_selection()
1824 for (portno = 0; portno < consts->n_ports; ++portno) in sparx5_vcap_is2_port_key_selection()
1835 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_vcap_es0_port_key_selection()
1840 for (portno = 0; portno < consts->n_ports; ++portno) in sparx5_vcap_es0_port_key_selection()
1852 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_vcap_es2_port_key_selection()
1859 for (lookup = 0; lookup < admin->lookups; ++lookup) in sparx5_vcap_es2_port_key_selection()
1860 for (portno = 0; portno < consts->n_ports; ++portno) in sparx5_vcap_es2_port_key_selection()
1869 switch (admin->vtype) { in sparx5_vcap_port_key_selection()
1892 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_vcap_port_key_deselection()
1895 switch (admin->vtype) { in sparx5_vcap_port_key_deselection()
1897 for (lookup = 0; lookup < admin->lookups; ++lookup) in sparx5_vcap_port_key_deselection()
1898 for (portno = 0; portno < consts->n_ports; ++portno) in sparx5_vcap_port_key_deselection()
1905 for (portno = 0; portno < consts->n_ports; ++portno) in sparx5_vcap_port_key_deselection()
1916 for (lookup = 0; lookup < admin->lookups; ++lookup) in sparx5_vcap_port_key_deselection()
1917 for (portno = 0; portno < consts->n_ports; ++portno) in sparx5_vcap_port_key_deselection()
1933 mutex_destroy(&admin->lock); in sparx5_vcap_admin_free()
1934 kfree(admin->cache.keystream); in sparx5_vcap_admin_free()
1935 kfree(admin->cache.maskstream); in sparx5_vcap_admin_free()
1936 kfree(admin->cache.actionstream); in sparx5_vcap_admin_free()
1949 return ERR_PTR(-ENOMEM); in sparx5_vcap_admin_alloc()
1950 INIT_LIST_HEAD(&admin->list); in sparx5_vcap_admin_alloc()
1951 INIT_LIST_HEAD(&admin->rules); in sparx5_vcap_admin_alloc()
1952 INIT_LIST_HEAD(&admin->enabled); in sparx5_vcap_admin_alloc()
1953 mutex_init(&admin->lock); in sparx5_vcap_admin_alloc()
1954 admin->vtype = cfg->vtype; in sparx5_vcap_admin_alloc()
1955 admin->vinst = cfg->vinst; in sparx5_vcap_admin_alloc()
1956 admin->ingress = cfg->ingress; in sparx5_vcap_admin_alloc()
1957 admin->lookups = cfg->lookups; in sparx5_vcap_admin_alloc()
1958 admin->lookups_per_instance = cfg->lookups_per_instance; in sparx5_vcap_admin_alloc()
1959 admin->first_cid = cfg->first_cid; in sparx5_vcap_admin_alloc()
1960 admin->last_cid = cfg->last_cid; in sparx5_vcap_admin_alloc()
1961 admin->cache.keystream = in sparx5_vcap_admin_alloc()
1963 admin->cache.maskstream = in sparx5_vcap_admin_alloc()
1965 admin->cache.actionstream = in sparx5_vcap_admin_alloc()
1967 if (!admin->cache.keystream || !admin->cache.maskstream || in sparx5_vcap_admin_alloc()
1968 !admin->cache.actionstream) { in sparx5_vcap_admin_alloc()
1970 return ERR_PTR(-ENOMEM); in sparx5_vcap_admin_alloc()
1982 switch (admin->vtype) { in sparx5_vcap_block_alloc()
1985 /* Super VCAP block mapping and address configuration. Block 0 in sparx5_vcap_block_alloc()
1989 for (idx = cfg->blockno; idx < cfg->blockno + cfg->blocks; in sparx5_vcap_block_alloc()
1993 spx5_wr(VCAP_SUPER_MAP_CORE_MAP_SET(cfg->map_id), in sparx5_vcap_block_alloc()
1996 admin->first_valid_addr = cfg->blockno * SUPER_VCAP_BLK_SIZE; in sparx5_vcap_block_alloc()
1997 admin->last_used_addr = admin->first_valid_addr + in sparx5_vcap_block_alloc()
1998 cfg->blocks * SUPER_VCAP_BLK_SIZE; in sparx5_vcap_block_alloc()
1999 admin->last_valid_addr = admin->last_used_addr - 1; in sparx5_vcap_block_alloc()
2002 admin->first_valid_addr = 0; in sparx5_vcap_block_alloc()
2003 admin->last_used_addr = cfg->count; in sparx5_vcap_block_alloc()
2004 admin->last_valid_addr = cfg->count - 1; in sparx5_vcap_block_alloc()
2014 admin->first_valid_addr = 0; in sparx5_vcap_block_alloc()
2015 admin->last_used_addr = cfg->count; in sparx5_vcap_block_alloc()
2016 admin->last_valid_addr = cfg->count - 1; in sparx5_vcap_block_alloc()
2034 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_vcap_init()
2044 * - Create administrative state for each available VCAP in sparx5_vcap_init()
2045 * - Lists of rules in sparx5_vcap_init()
2046 * - Address information in sparx5_vcap_init()
2047 * - Initialize VCAP blocks in sparx5_vcap_init()
2048 * - Configure port keysets in sparx5_vcap_init()
2052 return -ENOMEM; in sparx5_vcap_init()
2054 sparx5->vcap_ctrl = ctrl; in sparx5_vcap_init()
2056 ctrl->vcaps = consts->vcaps; in sparx5_vcap_init()
2057 ctrl->stats = consts->vcap_stats; in sparx5_vcap_init()
2059 ctrl->ops = &sparx5_vcap_ops; in sparx5_vcap_init()
2061 INIT_LIST_HEAD(&ctrl->list); in sparx5_vcap_init()
2063 cfg = &consts->vcaps_cfg[idx]; in sparx5_vcap_init()
2073 if (cfg->vinst == 0) in sparx5_vcap_init()
2075 list_add_tail(&admin->list, &ctrl->list); in sparx5_vcap_init()
2077 dir = vcap_debugfs(sparx5->dev, sparx5->debugfs_root, ctrl); in sparx5_vcap_init()
2078 for (idx = 0; idx < consts->n_ports; ++idx) in sparx5_vcap_init()
2079 if (sparx5->ports[idx]) in sparx5_vcap_init()
2080 vcap_port_debugfs(sparx5->dev, dir, ctrl, in sparx5_vcap_init()
2081 sparx5->ports[idx]->ndev); in sparx5_vcap_init()
2088 struct vcap_control *ctrl = sparx5->vcap_ctrl; in sparx5_vcap_destroy()
2094 list_for_each_entry_safe(admin, admin_next, &ctrl->list, list) { in sparx5_vcap_destroy()
2097 list_del(&admin->list); in sparx5_vcap_destroy()