Lines Matching +full:speed +full:- +full:map
1 // SPDX-License-Identifier: GPL-2.0+
31 status->an_complete = true; in decode_sgmii_word()
33 status->link = false; in decode_sgmii_word()
39 status->speed = SPEED_10; in decode_sgmii_word()
42 status->speed = SPEED_100; in decode_sgmii_word()
45 status->speed = SPEED_1000; in decode_sgmii_word()
48 status->link = false; in decode_sgmii_word()
52 status->duplex = DUPLEX_FULL; in decode_sgmii_word()
54 status->duplex = DUPLEX_HALF; in decode_sgmii_word()
59 status->link = !(lp_abil & ADVERTISE_RFAULT) && status->link; in decode_cl37_word()
60 status->an_complete = true; in decode_cl37_word()
61 status->duplex = (ADVERTISE_1000XFULL & lp_abil) ? in decode_cl37_word()
66 status->pause = MLO_PAUSE_RX | MLO_PAUSE_TX; in decode_cl37_word()
69 status->pause |= (lp_abil & ADVERTISE_1000XPAUSE) ? in decode_cl37_word()
71 status->pause |= (ld_abil & ADVERTISE_1000XPAUSE) ? in decode_cl37_word()
74 status->pause = MLO_PAUSE_NONE; in decode_cl37_word()
82 u32 portno = port->portno; in sparx5_get_dev2g5_status()
88 status->link_down = DEV2G5_PCS1G_STICKY_LINK_DOWN_STICKY_GET(value); in sparx5_get_dev2g5_status()
89 if (status->link_down) /* Clear the sticky */ in sparx5_get_dev2g5_status()
94 status->link = DEV2G5_PCS1G_LINK_STATUS_LINK_STATUS_GET(value) && in sparx5_get_dev2g5_status()
97 if (port->conf.portmode == PHY_INTERFACE_MODE_1000BASEX) in sparx5_get_dev2g5_status()
98 status->speed = SPEED_1000; in sparx5_get_dev2g5_status()
99 else if (port->conf.portmode == PHY_INTERFACE_MODE_2500BASEX) in sparx5_get_dev2g5_status()
100 status->speed = SPEED_2500; in sparx5_get_dev2g5_status()
102 status->duplex = DUPLEX_FULL; in sparx5_get_dev2g5_status()
110 if (port->conf.portmode == PHY_INTERFACE_MODE_SGMII) { in sparx5_get_dev2g5_status()
125 bool high_speed_dev = sparx5_is_baser(port->conf.portmode); in sparx5_get_sfi_status()
126 u32 portno = port->portno; in sparx5_get_sfi_status()
131 netdev_err(port->ndev, "error: low speed and SFI mode\n"); in sparx5_get_sfi_status()
132 return -EINVAL; in sparx5_get_sfi_status()
142 status->link_down = 1; in sparx5_get_sfi_status()
146 status->link = (value == DEV10G_MAC_TX_MONITOR_STICKY_IDLE_STATE_STICKY); in sparx5_get_sfi_status()
147 status->duplex = DUPLEX_FULL; in sparx5_get_sfi_status()
148 if (port->conf.portmode == PHY_INTERFACE_MODE_5GBASER) in sparx5_get_sfi_status()
149 status->speed = SPEED_5000; in sparx5_get_sfi_status()
150 else if (port->conf.portmode == PHY_INTERFACE_MODE_10GBASER) in sparx5_get_sfi_status()
151 status->speed = SPEED_10000; in sparx5_get_sfi_status()
153 status->speed = SPEED_25000; in sparx5_get_sfi_status()
158 /* Get link status of 1000Base-X/in-band and SFI ports.
165 status->speed = port->conf.speed; in sparx5_get_port_status()
166 if (port->conf.power_down) { in sparx5_get_port_status()
167 status->link = false; in sparx5_get_port_status()
170 switch (port->conf.portmode) { in sparx5_get_port_status()
183 netdev_err(port->ndev, "Status not supported"); in sparx5_get_port_status()
184 return -ENODEV; in sparx5_get_port_status()
195 netdev_err(port->ndev, in sparx5_port_error()
196 "Interface does not support speed: %u: for %s\n", in sparx5_port_error()
197 conf->speed, phy_modes(conf->portmode)); in sparx5_port_error()
200 netdev_err(port->ndev, in sparx5_port_error()
202 phy_modes(conf->portmode)); in sparx5_port_error()
205 netdev_err(port->ndev, in sparx5_port_error()
209 return -EINVAL; in sparx5_port_error()
216 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_port_verify_speed()
218 if ((ops->is_port_2g5(port->portno) && in sparx5_port_verify_speed()
219 conf->speed > SPEED_2500) || in sparx5_port_verify_speed()
220 (ops->is_port_5g(port->portno) && in sparx5_port_verify_speed()
221 conf->speed > SPEED_5000) || in sparx5_port_verify_speed()
222 (ops->is_port_10g(port->portno) && in sparx5_port_verify_speed()
223 conf->speed > SPEED_10000)) in sparx5_port_verify_speed()
226 switch (conf->portmode) { in sparx5_port_verify_speed()
228 return -EINVAL; in sparx5_port_verify_speed()
230 if (conf->speed != SPEED_1000 || in sparx5_port_verify_speed()
231 ops->is_port_2g5(port->portno)) in sparx5_port_verify_speed()
233 if (ops->is_port_2g5(port->portno)) in sparx5_port_verify_speed()
237 if (conf->speed != SPEED_2500 || in sparx5_port_verify_speed()
238 ops->is_port_2g5(port->portno)) in sparx5_port_verify_speed()
242 if (port->portno > 47) in sparx5_port_verify_speed()
246 if (conf->speed != SPEED_1000 && in sparx5_port_verify_speed()
247 conf->speed != SPEED_100 && in sparx5_port_verify_speed()
248 conf->speed != SPEED_10 && in sparx5_port_verify_speed()
249 conf->speed != SPEED_2500) in sparx5_port_verify_speed()
255 if ((conf->speed != SPEED_5000 && in sparx5_port_verify_speed()
256 conf->speed != SPEED_10000 && in sparx5_port_verify_speed()
257 conf->speed != SPEED_25000)) in sparx5_port_verify_speed()
264 if (conf->speed != SPEED_1000 && in sparx5_port_verify_speed()
265 conf->speed != SPEED_100 && in sparx5_port_verify_speed()
266 conf->speed != SPEED_10) in sparx5_port_verify_speed()
279 return sparx5_is_baser(port->conf.portmode) ^ in sparx5_dev_change()
280 sparx5_is_baser(conf->portmode); in sparx5_dev_change()
289 /* Resource == 0: Memory tracked per source (SRC-MEM) in sparx5_port_flush_poll()
290 * Resource == 1: Frame references tracked per source (SRC-REF) in sparx5_port_flush_poll()
291 * Resource == 2: Memory tracked per destination (DST-MEM) in sparx5_port_flush_poll()
292 * Resource == 3: Frame references tracked per destination. (DST-REF) in sparx5_port_flush_poll()
306 "DST-MEM" : "SRC-MEM"; in sparx5_port_flush_poll()
316 dev_err(sparx5->dev, in sparx5_port_flush_poll()
319 return -EINVAL; in sparx5_port_flush_poll()
330 sparx5_port_dev_index(sparx5, port->portno) : port->portno; in sparx5_port_disable()
332 sparx5_to_high_dev(sparx5, port->portno) : TARGET_DEV2G5; in sparx5_port_disable()
334 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_port_disable()
335 u32 spd = port->conf.speed; in sparx5_port_disable()
363 /* 3: Disable traffic being sent to or from switch port->portno */ in sparx5_port_disable()
367 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_disable()
373 HSCH_PORT_MODE(port->portno)); in sparx5_port_disable()
376 spx5_rmw(QSYS_PAUSE_CFG_PAUSE_STOP_SET(0xFFF - 1), in sparx5_port_disable()
379 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_disable()
385 /* 7: Flush the queues associated with the port->portno */ in sparx5_port_disable()
386 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
401 HSCH_PORT_MODE(port->portno)); in sparx5_port_disable()
404 err = sparx5_port_flush_poll(sparx5, port->portno); in sparx5_port_disable()
434 spx5_rmw(HSCH_FLUSH_CTRL_FLUSH_PORT_SET(port->portno) | in sparx5_port_disable()
442 u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); in sparx5_port_disable()
451 if (ops->is_port_25g(port->portno)) in sparx5_port_disable()
462 DEV2G5_PCS1G_CFG(port->portno)); in sparx5_port_disable()
470 u32 portno, u32 speed) in sparx5_port_fifo_sz() argument
472 u32 sys_clk = sparx5_clk_period(sparx5->coreclock); in sparx5_port_fifo_sz()
491 switch (speed) { in sparx5_port_fifo_sz()
534 u32 portno = port->portno; in sparx5_port_mux_set()
537 if (port->conf.portmode == conf->portmode) in sparx5_port_mux_set()
540 switch (conf->portmode) { in sparx5_port_mux_set()
542 inst = (portno - portno % 4) / 4; in sparx5_port_mux_set()
549 /* Affects d0-d3,d8-d11..d40-d43 */ in sparx5_port_mux_set()
569 enum sparx5_port_max_tags max_tags = port->max_vlan_tags; in sparx5_port_max_tags_set()
573 enum sparx5_vlan_port_type vlan_type = port->vlan_type; in sparx5_port_max_tags_set()
575 u32 dev = sparx5_to_high_dev(sparx5, port->portno); in sparx5_port_max_tags_set()
576 u32 tinst = sparx5_port_dev_index(sparx5, port->portno); in sparx5_port_max_tags_set()
578 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_port_max_tags_set()
582 port->custom_etype : in sparx5_port_max_tags_set()
591 DEV2G5_MAC_TAGS_CFG(port->portno)); in sparx5_port_max_tags_set()
593 if (ops->is_port_2g5(port->portno)) in sparx5_port_max_tags_set()
615 int sparx5_port_fwd_urg(struct sparx5 *sparx5, u32 speed) in sparx5_port_fwd_urg() argument
620 switch (speed) { in sparx5_port_fwd_urg()
639 return urg / clk_period_ps - 1; in sparx5_port_fwd_urg()
654 bool fc_obey = conf->pause & MLO_PAUSE_RX ? 1 : 0; in sparx5_port_fc_setup()
655 u32 pause_stop = 0xFFF - 1; /* FC gen disabled */ in sparx5_port_fc_setup()
657 if (conf->pause & MLO_PAUSE_TX) in sparx5_port_fc_setup()
662 spx5_rmw(DSM_MAC_CFG_HDX_BACKPREASSURE_SET(conf->duplex == DUPLEX_HALF), in sparx5_port_fc_setup()
665 DSM_MAC_CFG(port->portno)); in sparx5_port_fc_setup()
671 DSM_RX_PAUSE_CFG(port->portno)); in sparx5_port_fc_setup()
677 QSYS_FWD_PRESSURE(port->portno)); in sparx5_port_fc_setup()
683 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_fc_setup()
690 if (conf->portmode == PHY_INTERFACE_MODE_1000BASEX) /* cl-37 aneg */ in sparx5_get_aneg_word()
691 return (conf->pause_adv | ADVERTISE_LPACK | ADVERTISE_1000XFULL); in sparx5_get_aneg_word()
700 int portmode, err, speed = conf->speed; in sparx5_serdes_set() local
702 if (conf->portmode == PHY_INTERFACE_MODE_QSGMII && in sparx5_serdes_set()
703 ((port->portno % 4) != 0)) { in sparx5_serdes_set()
706 if (sparx5_is_baser(conf->portmode)) { in sparx5_serdes_set()
707 if (conf->portmode == PHY_INTERFACE_MODE_25GBASER) in sparx5_serdes_set()
708 speed = SPEED_25000; in sparx5_serdes_set()
709 else if (conf->portmode == PHY_INTERFACE_MODE_10GBASER) in sparx5_serdes_set()
710 speed = SPEED_10000; in sparx5_serdes_set()
712 speed = SPEED_5000; in sparx5_serdes_set()
715 err = phy_set_media(port->serdes, conf->media); in sparx5_serdes_set()
718 if (speed > 0) { in sparx5_serdes_set()
719 err = phy_set_speed(port->serdes, speed); in sparx5_serdes_set()
723 if (conf->serdes_reset) { in sparx5_serdes_set()
724 err = phy_reset(port->serdes); in sparx5_serdes_set()
730 * For BaseR, the serdes driver supports 10GGBASE-R and speed 5G/10G/25G in sparx5_serdes_set()
732 portmode = conf->portmode; in sparx5_serdes_set()
733 if (sparx5_is_baser(conf->portmode)) in sparx5_serdes_set()
735 err = phy_set_mode_ext(port->serdes, PHY_MODE_ETHERNET, portmode); in sparx5_serdes_set()
738 conf->serdes_reset = false; in sparx5_serdes_set()
749 if (conf->inband) { in sparx5_port_pcs_low_set()
750 if (conf->portmode == PHY_INTERFACE_MODE_SGMII || in sparx5_port_pcs_low_set()
751 conf->portmode == PHY_INTERFACE_MODE_QSGMII) in sparx5_port_pcs_low_set()
752 inband_aneg = true; /* Cisco-SGMII in-band-aneg */ in sparx5_port_pcs_low_set()
753 else if (conf->portmode == PHY_INTERFACE_MODE_1000BASEX && in sparx5_port_pcs_low_set()
754 conf->autoneg) in sparx5_port_pcs_low_set()
755 inband_aneg = true; /* Clause-37 in-band-aneg */ in sparx5_port_pcs_low_set()
759 return -EINVAL; in sparx5_port_pcs_low_set()
768 DEV2G5_PCS1G_MODE_CFG(port->portno)); in sparx5_port_pcs_low_set()
773 DEV2G5_PCS1G_CFG(port->portno)); in sparx5_port_pcs_low_set()
778 /* Enable in-band aneg */ in sparx5_port_pcs_low_set()
784 DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
786 spx5_wr(0, sparx5, DEV2G5_PCS1G_ANEG_CFG(port->portno)); in sparx5_port_pcs_low_set()
797 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_pcs_low_set()
806 u32 clk_spd = conf->portmode == PHY_INTERFACE_MODE_5GBASER ? 1 : 0; in sparx5_port_pcs_high_set()
807 u32 pix = sparx5_port_dev_index(sparx5, port->portno); in sparx5_port_pcs_high_set()
808 u32 dev = sparx5_to_high_dev(sparx5, port->portno); in sparx5_port_pcs_high_set()
809 u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); in sparx5_port_pcs_high_set()
817 /* SFI : No in-band-aneg. Speeds 5G/10G/25G */ in sparx5_port_pcs_high_set()
820 return -EINVAL; in sparx5_port_pcs_high_set()
821 if (conf->portmode == PHY_INTERFACE_MODE_25GBASER) { in sparx5_port_pcs_high_set()
822 /* Enable PCS for 25G device, speed 25G */ in sparx5_port_pcs_high_set()
828 /* Enable PCS for 5G/10G/25G devices, speed 5G/10G */ in sparx5_port_pcs_high_set()
861 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_dev_switch()
864 bt_indx = BIT(ops->get_port_dev_bit(sparx5, port)); in sparx5_dev_switch()
866 if (ops->is_port_5g(port)) { in sparx5_dev_switch()
871 } else if (ops->is_port_10g(port)) { in sparx5_dev_switch()
876 } else if (ops->is_port_25g(port)) { in sparx5_dev_switch()
884 /* Configure speed/duplex dependent registers */
890 bool fdx = conf->duplex == DUPLEX_FULL; in sparx5_port_config_low_set()
891 int spd = conf->speed; in sparx5_port_config_low_set()
905 DEV2G5_MAC_MODE_CFG(port->portno)); in sparx5_port_config_low_set()
912 DEV2G5_MAC_IFG_CFG(port->portno)); in sparx5_port_config_low_set()
918 HSCH_PORT_MODE(port->portno)); in sparx5_port_config_low_set()
924 DEV2G5_MAC_ENA_CFG(port->portno)); in sparx5_port_config_low_set()
926 /* Select speed and take MAC out of reset */ in sparx5_port_config_low_set()
934 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_config_low_set()
946 sparx5, DEV2G5_PHAD_CTRL(port->portno, i)); in sparx5_port_config_low_set()
958 bool high_speed_dev = sparx5_is_baser(conf->portmode); in sparx5_port_pcs_set()
963 sparx5_dev_switch(sparx5, port->portno, high_speed_dev); in sparx5_port_pcs_set()
965 /* Disable the not-in-use device */ in sparx5_port_pcs_set()
970 /* Disable the port before re-configuring */ in sparx5_port_pcs_set()
973 return -EINVAL; in sparx5_port_pcs_set()
981 return -EINVAL; in sparx5_port_pcs_set()
983 if (conf->inband) { in sparx5_port_pcs_set()
988 ASM_PORT_CFG(port->portno)); in sparx5_port_pcs_set()
994 DSM_BUF_CFG(port->portno)); in sparx5_port_pcs_set()
997 port->conf = *conf; in sparx5_port_pcs_set()
1006 bool rgmii = phy_interface_mode_is_rgmii(conf->phy_mode); in sparx5_port_config()
1007 bool high_speed_dev = sparx5_is_baser(conf->portmode); in sparx5_port_config()
1008 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_port_config()
1016 err = ops->port_config_rgmii(port, conf); in sparx5_port_config()
1021 /* high speed device is already configured */ in sparx5_port_config()
1030 if (!is_sparx5(sparx5) && ops->is_port_10g(port->portno) && in sparx5_port_config()
1031 conf->speed < SPEED_10000) in sparx5_port_config()
1035 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_config()
1038 stop_wm = sparx5_port_fifo_sz(sparx5, port->portno, conf->speed); in sparx5_port_config()
1042 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_config()
1045 urgency = sparx5_port_fwd_urg(sparx5, conf->speed); in sparx5_port_config()
1051 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_config()
1054 port->conf = *conf; in sparx5_port_config()
1066 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_port_init()
1067 u32 devhigh = sparx5_to_high_dev(sparx5, port->portno); in sparx5_port_init()
1068 u32 pix = sparx5_port_dev_index(sparx5, port->portno); in sparx5_port_init()
1069 u32 pcs = sparx5_to_pcs_dev(sparx5, port->portno); in sparx5_port_init()
1070 bool sd_pol = port->signd_active_high; in sparx5_port_init()
1071 bool sd_sel = !port->signd_internal; in sparx5_port_init()
1072 bool sd_ena = port->signd_enable; in sparx5_port_init()
1073 u32 pause_stop = 0xFFF - 1; /* FC generate disabled */ in sparx5_port_init()
1082 err = ops->set_port_mux(sparx5, port, conf); in sparx5_port_init()
1094 QSYS_PAUSE_CFG(port->portno)); in sparx5_port_init()
1099 QSYS_ATOP(port->portno)); in sparx5_port_init()
1101 /* Discard pause frame 01-80-C2-00-00-01 */ in sparx5_port_init()
1102 spx5_wr(PAUSE_DISCARD, sparx5, ANA_CL_CAPTURE_BPDU_CFG(port->portno)); in sparx5_port_init()
1107 sparx5, ANA_CL_FILTER_CTRL(port->portno)); in sparx5_port_init()
1109 if (ops->is_port_rgmii(port->portno)) in sparx5_port_init()
1110 return 0; /* RGMII device - nothing more to configure */ in sparx5_port_init()
1121 DEV2G5_MAC_MAXLEN_CFG(port->portno)); in sparx5_port_init()
1128 DEV2G5_PCS1G_SD_CFG(port->portno)); in sparx5_port_init()
1130 if (conf->portmode == PHY_INTERFACE_MODE_QSGMII || in sparx5_port_init()
1131 conf->portmode == PHY_INTERFACE_MODE_SGMII) { in sparx5_port_init()
1136 if (!ops->is_port_2g5(port->portno)) in sparx5_port_init()
1141 DSM_DEV_TX_STOP_WM_CFG(port->portno)); in sparx5_port_init()
1143 sparx5_dev_switch(sparx5, port->portno, false); in sparx5_port_init()
1145 if (conf->portmode == PHY_INTERFACE_MODE_QSGMII) { in sparx5_port_init()
1150 DEV2G5_DEV_RST_CTRL(port->portno)); in sparx5_port_init()
1157 DEV2G5_MAC_IFG_CFG(port->portno)); in sparx5_port_init()
1159 if (ops->is_port_2g5(port->portno)) in sparx5_port_init()
1160 return 0; /* Low speed device only - return */ in sparx5_port_init()
1162 /* Now setup the high speed device */ in sparx5_port_init()
1163 if (conf->portmode == PHY_INTERFACE_MODE_NA) in sparx5_port_init()
1164 conf->portmode = PHY_INTERFACE_MODE_10GBASER; in sparx5_port_init()
1166 if (sparx5_is_baser(conf->portmode)) in sparx5_port_init()
1167 sparx5_dev_switch(sparx5, port->portno, true); in sparx5_port_init()
1182 if (ops->is_port_25g(port->portno)) { in sparx5_port_init()
1195 if (ops->is_port_10g(port->portno)) { in sparx5_port_init()
1196 dev = sparx5_to_high_dev(sparx5, port->portno); in sparx5_port_init()
1197 tinst = sparx5_port_dev_index(sparx5, port->portno); in sparx5_port_init()
1201 DEV10G_PTP_STAMPER_CFG(port->portno)); in sparx5_port_init()
1202 } else if (ops->is_port_5g(port->portno)) { in sparx5_port_init()
1203 dev = sparx5_to_high_dev(sparx5, port->portno); in sparx5_port_init()
1204 tinst = sparx5_port_dev_index(sparx5, port->portno); in sparx5_port_init()
1208 DEV5G_PTP_STAMPER_CFG(port->portno)); in sparx5_port_init()
1217 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_enable()
1223 QFWD_SWITCH_PORT_MODE(port->portno)); in sparx5_port_enable()
1229 sparx5_port_qos_dscp_set(port, &qos->dscp); in sparx5_port_qos_set()
1230 sparx5_port_qos_pcp_set(port, &qos->pcp); in sparx5_port_qos_set()
1231 sparx5_port_qos_pcp_rewr_set(port, &qos->pcp_rewr); in sparx5_port_qos_set()
1232 sparx5_port_qos_dscp_rewr_set(port, &qos->dscp_rewr); in sparx5_port_qos_set()
1242 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_pcp_rewr_set()
1245 /* Use mapping table, with classified QoS as index, to map QoS and DP in sparx5_port_qos_pcp_rewr_set()
1249 if (qos->enable) in sparx5_port_qos_pcp_rewr_set()
1255 port->sparx5, REW_TAG_CTRL(port->portno)); in sparx5_port_qos_pcp_rewr_set()
1257 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_pcp_rewr_set()
1259 pcp = qos->map.map[i]; in sparx5_port_qos_pcp_rewr_set()
1269 * 0:0nd - prio=0 and dp:0 => pcp=0 and dei=0 in sparx5_port_qos_pcp_rewr_set()
1270 * 0:0de - prio=0 and dp:1 => pcp=0 and dei=1 in sparx5_port_qos_pcp_rewr_set()
1275 REW_PCP_MAP_DE1(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1278 REW_DEI_MAP_DE1_DEI_DE1, port->sparx5, in sparx5_port_qos_pcp_rewr_set()
1279 REW_DEI_MAP_DE1(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1283 REW_PCP_MAP_DE0(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1286 REW_DEI_MAP_DE0_DEI_DE0, port->sparx5, in sparx5_port_qos_pcp_rewr_set()
1287 REW_DEI_MAP_DE0(port->portno, i)); in sparx5_port_qos_pcp_rewr_set()
1297 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_pcp_set()
1298 u8 *pcp_itr = qos->map.map; in sparx5_port_qos_pcp_set()
1303 spx5_rmw(ANA_CL_QOS_CFG_PCP_DEI_QOS_ENA_SET(qos->qos_enable) | in sparx5_port_qos_pcp_set()
1304 ANA_CL_QOS_CFG_PCP_DEI_DP_ENA_SET(qos->dp_enable), in sparx5_port_qos_pcp_set()
1306 sparx5, ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_pcp_set()
1308 /* Map each pcp and dei value to priority and dp */ in sparx5_port_qos_pcp_set()
1309 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_pcp_set()
1316 ANA_CL_PCP_DEI_MAP_CFG(port->portno, i)); in sparx5_port_qos_pcp_set()
1326 ANA_CL_QOS_CFG_DSCP_REWR_MODE_SEL, port->sparx5, in sparx5_port_qos_dscp_rewr_mode_set()
1327 ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_dscp_rewr_mode_set()
1333 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_dscp_rewr_set()
1341 if (qos->enable) in sparx5_port_qos_dscp_rewr_set()
1346 REW_DSCP_MAP(port->portno)); in sparx5_port_qos_dscp_rewr_set()
1348 /* On ingress, map each classified QoS class and DP to classified DSCP in sparx5_port_qos_dscp_rewr_set()
1351 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_dscp_rewr_set()
1352 dscp = qos->map.map[i]; in sparx5_port_qos_dscp_rewr_set()
1364 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_dscp_set()
1365 u8 *dscp = qos->map.map; in sparx5_port_qos_dscp_set()
1371 spx5_rmw(ANA_CL_QOS_CFG_DSCP_QOS_ENA_SET(qos->qos_enable) | in sparx5_port_qos_dscp_set()
1372 ANA_CL_QOS_CFG_DSCP_DP_ENA_SET(qos->dp_enable) | in sparx5_port_qos_dscp_set()
1376 ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_dscp_set()
1378 /* Map each dscp value to priority and dp */ in sparx5_port_qos_dscp_set()
1379 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_dscp_set()
1387 /* Set per-dscp trust */ in sparx5_port_qos_dscp_set()
1388 for (i = 0; i < ARRAY_SIZE(qos->map.map); i++) { in sparx5_port_qos_dscp_set()
1389 if (qos->qos_enable) { in sparx5_port_qos_dscp_set()
1402 struct sparx5 *sparx5 = port->sparx5; in sparx5_port_qos_default_set()
1405 spx5_rmw(ANA_CL_QOS_CFG_DEFAULT_QOS_VAL_SET(qos->default_prio) | in sparx5_port_qos_default_set()
1409 sparx5, ANA_CL_QOS_CFG(port->portno)); in sparx5_port_qos_default_set()
1416 sparx5, ANA_CL_VLAN_CTRL(port->portno)); in sparx5_port_qos_default_set()
1423 return sparx5->data->consts->n_ports + port; in sparx5_get_internal_port()