Lines Matching +full:sparx5 +full:- +full:cpu +full:- +full:syscon
1 // SPDX-License-Identifier: GPL-2.0+
2 /* Microchip Sparx5 Switch driver
6 * The Sparx5 Chip Register Model can be browsed at this location:
7 * https://github.com/microchip-ung/sparx-5_reginfo
22 #include <linux/mfd/syscon.h>
215 bool is_sparx5(struct sparx5 *sparx5) in is_sparx5() argument
217 switch (sparx5->target_ct) { in is_sparx5()
234 static void sparx5_init_features(struct sparx5 *sparx5) in sparx5_init_features() argument
236 switch (sparx5->target_ct) { in sparx5_init_features()
256 sparx5->features = (SPX5_FEATURE_PSFP | SPX5_FEATURE_PTP); in sparx5_init_features()
263 bool sparx5_has_feature(struct sparx5 *sparx5, enum sparx5_feature feature) in sparx5_has_feature() argument
265 return sparx5->features & feature; in sparx5_has_feature()
268 static int sparx5_create_targets(struct sparx5 *sparx5) in sparx5_create_targets() argument
270 const struct sparx5_main_io_resource *iomap = sparx5->data->iomap; in sparx5_create_targets()
271 int iomap_size = sparx5->data->iomap_size; in sparx5_create_targets()
272 int ioranges = sparx5->data->ioranges; in sparx5_create_targets()
282 if (idx == io->range) { in sparx5_create_targets()
288 iores[idx] = platform_get_resource(sparx5->pdev, IORESOURCE_MEM, in sparx5_create_targets()
291 dev_err(sparx5->dev, "Invalid resource\n"); in sparx5_create_targets()
292 return -EINVAL; in sparx5_create_targets()
294 iomem[idx] = devm_ioremap(sparx5->dev, in sparx5_create_targets()
295 iores[idx]->start, in sparx5_create_targets()
298 dev_err(sparx5->dev, "Unable to get switch registers: %s\n", in sparx5_create_targets()
299 iores[idx]->name); in sparx5_create_targets()
300 return -ENOMEM; in sparx5_create_targets()
302 begin[idx] = iomem[idx] - iomap[range_id[idx]].offset; in sparx5_create_targets()
307 sparx5->regs[io->id] = begin[io->range] + io->offset; in sparx5_create_targets()
312 static int sparx5_create_port(struct sparx5 *sparx5, in sparx5_create_port() argument
321 ops = sparx5->data->ops; in sparx5_create_port()
323 ndev = sparx5_create_netdev(sparx5, config->portno); in sparx5_create_port()
325 dev_err(sparx5->dev, "Could not create net device: %02u\n", in sparx5_create_port()
326 config->portno); in sparx5_create_port()
330 spx5_port->of_node = config->node; in sparx5_create_port()
331 spx5_port->serdes = config->serdes; in sparx5_create_port()
332 spx5_port->pvid = NULL_VID; in sparx5_create_port()
333 spx5_port->signd_internal = true; in sparx5_create_port()
334 spx5_port->signd_active_high = true; in sparx5_create_port()
335 spx5_port->signd_enable = true; in sparx5_create_port()
336 spx5_port->max_vlan_tags = SPX5_PORT_MAX_TAGS_NONE; in sparx5_create_port()
337 spx5_port->vlan_type = SPX5_VLAN_PORT_TYPE_UNAWARE; in sparx5_create_port()
338 spx5_port->custom_etype = 0x8880; /* Vitesse */ in sparx5_create_port()
339 spx5_port->phylink_pcs.poll = true; in sparx5_create_port()
340 spx5_port->phylink_pcs.ops = &sparx5_phylink_pcs_ops; in sparx5_create_port()
341 spx5_port->is_mrouter = false; in sparx5_create_port()
342 INIT_LIST_HEAD(&spx5_port->tc_templates); in sparx5_create_port()
343 sparx5->ports[config->portno] = spx5_port; in sparx5_create_port()
345 err = sparx5_port_init(sparx5, spx5_port, &config->conf); in sparx5_create_port()
347 dev_err(sparx5->dev, "port init failed\n"); in sparx5_create_port()
350 spx5_port->conf = config->conf; in sparx5_create_port()
353 sparx5_vlan_port_setup(sparx5, spx5_port->portno); in sparx5_create_port()
356 spx5_port->phylink_config.dev = &spx5_port->ndev->dev; in sparx5_create_port()
357 spx5_port->phylink_config.type = PHYLINK_NETDEV; in sparx5_create_port()
358 spx5_port->phylink_config.mac_capabilities = MAC_ASYM_PAUSE | in sparx5_create_port()
362 if (ops->is_port_rgmii(spx5_port->portno)) in sparx5_create_port()
363 phy_interface_set_rgmii(spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
366 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
368 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
370 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
372 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
374 if (spx5_port->conf.bandwidth == SPEED_5000 || in sparx5_create_port()
375 spx5_port->conf.bandwidth == SPEED_10000 || in sparx5_create_port()
376 spx5_port->conf.bandwidth == SPEED_25000) in sparx5_create_port()
378 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
380 if (spx5_port->conf.bandwidth == SPEED_10000 || in sparx5_create_port()
381 spx5_port->conf.bandwidth == SPEED_25000) in sparx5_create_port()
383 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
385 if (spx5_port->conf.bandwidth == SPEED_25000) in sparx5_create_port()
387 spx5_port->phylink_config.supported_interfaces); in sparx5_create_port()
389 phylink = phylink_create(&spx5_port->phylink_config, in sparx5_create_port()
390 of_fwnode_handle(config->node), in sparx5_create_port()
391 config->conf.phy_mode, in sparx5_create_port()
396 spx5_port->phylink = phylink; in sparx5_create_port()
401 static int sparx5_init_ram(struct sparx5 *s5) in sparx5_init_ram()
423 writel(cfg->init_val, cfg->init_reg); in sparx5_init_ram()
425 value = readl(cfg->init_reg); in sparx5_init_ram()
426 if ((value & cfg->init_val) != cfg->init_val) in sparx5_init_ram()
427 pending--; in sparx5_init_ram()
439 dev_err(s5->dev, "Memory initialization error\n"); in sparx5_init_ram()
440 return -EINVAL; in sparx5_init_ram()
445 static int sparx5_init_switchcore(struct sparx5 *sparx5) in sparx5_init_switchcore() argument
452 sparx5, in sparx5_init_switchcore()
457 sparx5, in sparx5_init_switchcore()
461 value = spx5_rd(sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
463 err = sparx5_init_ram(sparx5); in sparx5_init_switchcore()
469 spx5_wr(ANA_AC_STAT_RESET_RESET_SET(1), sparx5, ANA_AC_STAT_RESET); in sparx5_init_switchcore()
470 spx5_wr(ASM_STAT_CFG_STAT_CNT_CLR_SHOT_SET(1), sparx5, ASM_STAT_CFG); in sparx5_init_switchcore()
472 /* Enable switch-core and queue system */ in sparx5_init_switchcore()
473 spx5_wr(HSCH_RESET_CFG_CORE_ENA_SET(1), sparx5, HSCH_RESET_CFG); in sparx5_init_switchcore()
478 static int sparx5_init_coreclock(struct sparx5 *sparx5) in sparx5_init_coreclock() argument
480 enum sparx5_core_clockfreq freq = sparx5->coreclock; in sparx5_init_coreclock()
487 switch (sparx5->target_ct) { in sparx5_init_coreclock()
489 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
491 else if (sparx5->coreclock != SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
497 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
499 else if (sparx5->coreclock != SPX5_CORE_CLOCK_500MHZ) in sparx5_init_coreclock()
504 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
506 else if (sparx5->coreclock != SPX5_CORE_CLOCK_625MHZ) in sparx5_init_coreclock()
510 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
516 if (sparx5->coreclock == SPX5_CORE_CLOCK_DEFAULT) in sparx5_init_coreclock()
518 else if (sparx5->coreclock == SPX5_CORE_CLOCK_250MHZ) in sparx5_init_coreclock()
536 dev_err(sparx5->dev, "Target (%#04x) not supported\n", in sparx5_init_coreclock()
537 sparx5->target_ct); in sparx5_init_coreclock()
538 return -ENODEV; in sparx5_init_coreclock()
541 if (is_sparx5(sparx5)) { in sparx5_init_coreclock()
556 dev_err(sparx5->dev, in sparx5_init_coreclock()
558 sparx5->coreclock, sparx5->target_ct); in sparx5_init_coreclock()
559 return -EINVAL; in sparx5_init_coreclock()
575 sparx5, CLKGEN_LCPLL1_CORE_CLK_CFG); in sparx5_init_coreclock()
581 sparx5->coreclock = freq; in sparx5_init_coreclock()
584 if (is_sparx5(sparx5)) in sparx5_init_coreclock()
587 sparx5, in sparx5_init_coreclock()
592 sparx5, in sparx5_init_coreclock()
597 sparx5, in sparx5_init_coreclock()
602 sparx5, in sparx5_init_coreclock()
605 for (idx = 0; idx < sparx5->data->consts->n_sio_clks; idx++) in sparx5_init_coreclock()
608 sparx5, in sparx5_init_coreclock()
614 sparx5, in sparx5_init_coreclock()
619 sparx5, in sparx5_init_coreclock()
625 static u32 qlim_wm(struct sparx5 *sparx5, int fraction) in qlim_wm() argument
627 return (sparx5->data->consts->buf_size / SPX5_BUFFER_CELL_SZ - 100) * in qlim_wm()
631 static int sparx5_qlim_set(struct sparx5 *sparx5) in sparx5_qlim_set() argument
633 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_qlim_set()
638 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
640 consts->qres_max_prio_idx + in sparx5_qlim_set()
644 spx5_wr(0xFFF, sparx5, in sparx5_qlim_set()
646 consts->qres_max_colour_idx + in sparx5_qlim_set()
651 spx5_wr(qlim_wm(sparx5, 80), sparx5, XQS_QLIMIT_SHR_QLIM_CFG(0)); in sparx5_qlim_set()
652 spx5_wr(qlim_wm(sparx5, 90), sparx5, XQS_QLIMIT_SHR_CTOP_CFG(0)); in sparx5_qlim_set()
653 spx5_wr(qlim_wm(sparx5, 95), sparx5, XQS_QLIMIT_SHR_ATOP_CFG(0)); in sparx5_qlim_set()
654 spx5_wr(qlim_wm(sparx5, 100), sparx5, XQS_QLIMIT_SHR_TOP_CFG(0)); in sparx5_qlim_set()
662 static void sparx5_board_init(struct sparx5 *sparx5) in sparx5_board_init() argument
666 if (!sparx5->sd_sgpio_remapping) in sparx5_board_init()
672 sparx5, in sparx5_board_init()
676 for (idx = 0; idx < sparx5->data->consts->n_ports; idx++) in sparx5_board_init()
677 if (sparx5->ports[idx]) in sparx5_board_init()
678 if (sparx5->ports[idx]->conf.sd_sgpio != ~0) in sparx5_board_init()
679 spx5_wr(sparx5->ports[idx]->conf.sd_sgpio, in sparx5_board_init()
680 sparx5, in sparx5_board_init()
684 static int sparx5_start(struct sparx5 *sparx5) in sparx5_start() argument
687 const struct sparx5_consts *consts = sparx5->data->consts; in sparx5_start()
688 const struct sparx5_ops *ops = sparx5->data->ops; in sparx5_start()
694 for (idx = 0; idx < consts->n_own_upsids; idx++) { in sparx5_start()
695 spx5_wr(idx, sparx5, ANA_AC_OWN_UPSID(idx)); in sparx5_start()
696 spx5_wr(idx, sparx5, ANA_CL_OWN_UPSID(idx)); in sparx5_start()
697 spx5_wr(idx, sparx5, ANA_L2_OWN_UPSID(idx)); in sparx5_start()
698 spx5_wr(idx, sparx5, REW_OWN_UPSID(idx)); in sparx5_start()
701 /* Enable CPU ports */ in sparx5_start()
702 for (idx = consts->n_ports; idx < consts->n_ports_all; idx++) in sparx5_start()
705 sparx5, in sparx5_start()
709 sparx5_update_fwd(sparx5); in sparx5_start()
711 /* CPU copy CPU pgids */ in sparx5_start()
712 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, in sparx5_start()
713 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_CPU))); in sparx5_start()
714 spx5_wr(ANA_AC_PGID_MISC_CFG_PGID_CPU_COPY_ENA_SET(1), sparx5, in sparx5_start()
715 ANA_AC_PGID_MISC_CFG(sparx5_get_pgid(sparx5, PGID_BCAST))); in sparx5_start()
718 for (idx = sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_0); in sparx5_start()
719 idx <= sparx5_get_internal_port(sparx5, SPX5_PORT_CPU_1); idx++) in sparx5_start()
722 sparx5, ANA_CL_FILTER_CTRL(idx)); in sparx5_start()
725 sparx5_mact_init(sparx5); in sparx5_start()
728 sparx5_pgid_init(sparx5); in sparx5_start()
731 sparx5_vlan_init(sparx5); in sparx5_start()
733 /* Add host mode BC address (points only to CPU) */ in sparx5_start()
734 sparx5_mact_learn(sparx5, sparx5_get_pgid(sparx5, PGID_CPU), broadcast, in sparx5_start()
738 sparx5_qlim_set(sparx5); in sparx5_start()
740 err = sparx5_config_auto_calendar(sparx5); in sparx5_start()
744 err = sparx5_config_dsm_calendar(sparx5); in sparx5_start()
749 err = sparx_stats_init(sparx5); in sparx5_start()
754 mutex_init(&sparx5->mact_lock); in sparx5_start()
755 INIT_LIST_HEAD(&sparx5->mact_entries); in sparx5_start()
756 snprintf(queue_name, sizeof(queue_name), "%s-mact", in sparx5_start()
757 dev_name(sparx5->dev)); in sparx5_start()
758 sparx5->mact_queue = create_singlethread_workqueue(queue_name); in sparx5_start()
759 if (!sparx5->mact_queue) in sparx5_start()
760 return -ENOMEM; in sparx5_start()
762 INIT_DELAYED_WORK(&sparx5->mact_work, sparx5_mact_pull_work); in sparx5_start()
763 queue_delayed_work(sparx5->mact_queue, &sparx5->mact_work, in sparx5_start()
766 mutex_init(&sparx5->mdb_lock); in sparx5_start()
767 INIT_LIST_HEAD(&sparx5->mdb_entries); in sparx5_start()
769 err = sparx5_register_netdevs(sparx5); in sparx5_start()
773 sparx5_board_init(sparx5); in sparx5_start()
774 err = sparx5_register_notifier_blocks(sparx5); in sparx5_start()
778 err = sparx5_vcap_init(sparx5); in sparx5_start()
780 sparx5_unregister_notifier_blocks(sparx5); in sparx5_start()
785 err = -ENXIO; in sparx5_start()
786 if (sparx5->fdma_irq >= 0) { in sparx5_start()
787 if (GCB_CHIP_ID_REV_ID_GET(sparx5->chip_id) > 0 || in sparx5_start()
788 !is_sparx5(sparx5)) in sparx5_start()
789 err = devm_request_irq(sparx5->dev, in sparx5_start()
790 sparx5->fdma_irq, in sparx5_start()
793 "sparx5-fdma", sparx5); in sparx5_start()
795 err = ops->fdma_init(sparx5); in sparx5_start()
797 sparx5_fdma_start(sparx5); in sparx5_start()
800 sparx5->fdma_irq = -ENXIO; in sparx5_start()
802 sparx5->fdma_irq = -ENXIO; in sparx5_start()
804 if (err && sparx5->xtr_irq >= 0) { in sparx5_start()
805 err = devm_request_irq(sparx5->dev, sparx5->xtr_irq, in sparx5_start()
807 "sparx5-xtr", sparx5); in sparx5_start()
809 err = sparx5_manual_injection_mode(sparx5); in sparx5_start()
811 sparx5->xtr_irq = -ENXIO; in sparx5_start()
813 sparx5->xtr_irq = -ENXIO; in sparx5_start()
816 if (sparx5->ptp_irq >= 0 && in sparx5_start()
817 sparx5_has_feature(sparx5, SPX5_FEATURE_PTP)) { in sparx5_start()
818 err = devm_request_threaded_irq(sparx5->dev, sparx5->ptp_irq, in sparx5_start()
819 NULL, ops->ptp_irq_handler, in sparx5_start()
820 IRQF_ONESHOT, "sparx5-ptp", in sparx5_start()
821 sparx5); in sparx5_start()
823 sparx5->ptp_irq = -ENXIO; in sparx5_start()
825 sparx5->ptp = 1; in sparx5_start()
831 static void sparx5_cleanup_ports(struct sparx5 *sparx5) in sparx5_cleanup_ports() argument
833 sparx5_unregister_netdevs(sparx5); in sparx5_cleanup_ports()
834 sparx5_destroy_netdevs(sparx5); in sparx5_cleanup_ports()
840 struct device_node *np = pdev->dev.of_node; in mchp_sparx5_probe()
844 struct sparx5 *sparx5; in mchp_sparx5_probe() local
847 if (!np && !pdev->dev.platform_data) in mchp_sparx5_probe()
848 return -ENODEV; in mchp_sparx5_probe()
850 sparx5 = devm_kzalloc(&pdev->dev, sizeof(*sparx5), GFP_KERNEL); in mchp_sparx5_probe()
851 if (!sparx5) in mchp_sparx5_probe()
852 return -ENOMEM; in mchp_sparx5_probe()
854 platform_set_drvdata(pdev, sparx5); in mchp_sparx5_probe()
855 sparx5->pdev = pdev; in mchp_sparx5_probe()
856 sparx5->dev = &pdev->dev; in mchp_sparx5_probe()
857 spin_lock_init(&sparx5->tx_lock); in mchp_sparx5_probe()
859 sparx5->data = device_get_match_data(sparx5->dev); in mchp_sparx5_probe()
860 if (!sparx5->data) in mchp_sparx5_probe()
861 return -EINVAL; in mchp_sparx5_probe()
863 regs = sparx5->data->regs; in mchp_sparx5_probe()
864 ops = sparx5->data->ops; in mchp_sparx5_probe()
867 reset = devm_reset_control_get_optional_shared(&pdev->dev, "switch"); in mchp_sparx5_probe()
869 return dev_err_probe(&pdev->dev, PTR_ERR(reset), in mchp_sparx5_probe()
874 sparx5->coreclock = SPX5_CORE_CLOCK_DEFAULT; in mchp_sparx5_probe()
876 sparx5->debugfs_root = debugfs_create_dir("sparx5", NULL); in mchp_sparx5_probe()
878 ports = of_get_child_by_name(np, "ethernet-ports"); in mchp_sparx5_probe()
880 dev_err(sparx5->dev, "no ethernet-ports child node found\n"); in mchp_sparx5_probe()
881 return -ENODEV; in mchp_sparx5_probe()
883 sparx5->port_count = of_get_child_count(ports); in mchp_sparx5_probe()
885 configs = kcalloc(sparx5->port_count, in mchp_sparx5_probe()
888 err = -ENOMEM; in mchp_sparx5_probe()
899 dev_err(sparx5->dev, "port reg property error\n"); in mchp_sparx5_probe()
903 conf = &config->conf; in mchp_sparx5_probe()
904 conf->speed = SPEED_UNKNOWN; in mchp_sparx5_probe()
905 conf->bandwidth = SPEED_UNKNOWN; in mchp_sparx5_probe()
906 err = of_get_phy_mode(portnp, &conf->phy_mode); in mchp_sparx5_probe()
908 dev_err(sparx5->dev, "port %u: missing phy-mode\n", in mchp_sparx5_probe()
913 &conf->bandwidth); in mchp_sparx5_probe()
915 dev_err(sparx5->dev, "port %u: missing bandwidth\n", in mchp_sparx5_probe()
919 err = of_property_read_u32(portnp, "microchip,sd-sgpio", &conf->sd_sgpio); in mchp_sparx5_probe()
921 conf->sd_sgpio = ~0; in mchp_sparx5_probe()
923 sparx5->sd_sgpio_remapping = true; in mchp_sparx5_probe()
925 if (!ops->is_port_rgmii(portno)) { in mchp_sparx5_probe()
926 serdes = devm_of_phy_get(sparx5->dev, portnp, NULL); in mchp_sparx5_probe()
928 err = dev_err_probe(sparx5->dev, in mchp_sparx5_probe()
936 config->portno = portno; in mchp_sparx5_probe()
937 config->node = portnp; in mchp_sparx5_probe()
938 config->serdes = serdes; in mchp_sparx5_probe()
940 conf->media = PHY_MEDIA_DAC; in mchp_sparx5_probe()
941 conf->serdes_reset = true; in mchp_sparx5_probe()
942 conf->portmode = conf->phy_mode; in mchp_sparx5_probe()
943 conf->power_down = true; in mchp_sparx5_probe()
947 err = sparx5_create_targets(sparx5); in mchp_sparx5_probe()
951 if (of_get_mac_address(np, sparx5->base_mac)) { in mchp_sparx5_probe()
952 dev_info(sparx5->dev, "MAC addr was not set, use random MAC\n"); in mchp_sparx5_probe()
953 eth_random_addr(sparx5->base_mac); in mchp_sparx5_probe()
954 sparx5->base_mac[5] = 0; in mchp_sparx5_probe()
957 sparx5->fdma_irq = platform_get_irq_byname(sparx5->pdev, "fdma"); in mchp_sparx5_probe()
958 sparx5->xtr_irq = platform_get_irq_byname(sparx5->pdev, "xtr"); in mchp_sparx5_probe()
959 sparx5->ptp_irq = platform_get_irq_byname(sparx5->pdev, "ptp"); in mchp_sparx5_probe()
961 /* Read chip ID to check CPU interface */ in mchp_sparx5_probe()
962 sparx5->chip_id = spx5_rd(sparx5, GCB_CHIP_ID); in mchp_sparx5_probe()
964 sparx5->target_ct = (enum spx5_target_chiptype) in mchp_sparx5_probe()
965 GCB_CHIP_ID_PART_ID_GET(sparx5->chip_id); in mchp_sparx5_probe()
968 sparx5_init_features(sparx5); in mchp_sparx5_probe()
971 err = sparx5_init_switchcore(sparx5); in mchp_sparx5_probe()
973 dev_err(sparx5->dev, "Switchcore initialization error\n"); in mchp_sparx5_probe()
977 /* Initialize the LC-PLL (core clock) and set affected registers */ in mchp_sparx5_probe()
978 err = sparx5_init_coreclock(sparx5); in mchp_sparx5_probe()
980 dev_err(sparx5->dev, "LC-PLL initialization error\n"); in mchp_sparx5_probe()
984 for (idx = 0; idx < sparx5->port_count; ++idx) { in mchp_sparx5_probe()
986 if (!config->node) in mchp_sparx5_probe()
989 err = sparx5_create_port(sparx5, config); in mchp_sparx5_probe()
991 dev_err(sparx5->dev, "port create error\n"); in mchp_sparx5_probe()
996 err = sparx5_start(sparx5); in mchp_sparx5_probe()
998 dev_err(sparx5->dev, "Start failed\n"); in mchp_sparx5_probe()
1002 err = sparx5_qos_init(sparx5); in mchp_sparx5_probe()
1004 dev_err(sparx5->dev, "Failed to initialize QoS\n"); in mchp_sparx5_probe()
1008 err = sparx5_ptp_init(sparx5); in mchp_sparx5_probe()
1010 dev_err(sparx5->dev, "PTP failed\n"); in mchp_sparx5_probe()
1014 INIT_LIST_HEAD(&sparx5->mall_entries); in mchp_sparx5_probe()
1019 sparx5_cleanup_ports(sparx5); in mchp_sparx5_probe()
1020 if (sparx5->mact_queue) in mchp_sparx5_probe()
1021 destroy_workqueue(sparx5->mact_queue); in mchp_sparx5_probe()
1031 struct sparx5 *sparx5 = platform_get_drvdata(pdev); in mchp_sparx5_remove() local
1032 const struct sparx5_ops *ops = sparx5->data->ops; in mchp_sparx5_remove()
1034 debugfs_remove_recursive(sparx5->debugfs_root); in mchp_sparx5_remove()
1035 if (sparx5->xtr_irq) { in mchp_sparx5_remove()
1036 disable_irq(sparx5->xtr_irq); in mchp_sparx5_remove()
1037 sparx5->xtr_irq = -ENXIO; in mchp_sparx5_remove()
1039 if (sparx5->fdma_irq) { in mchp_sparx5_remove()
1040 disable_irq(sparx5->fdma_irq); in mchp_sparx5_remove()
1041 sparx5->fdma_irq = -ENXIO; in mchp_sparx5_remove()
1043 sparx5_ptp_deinit(sparx5); in mchp_sparx5_remove()
1044 ops->fdma_deinit(sparx5); in mchp_sparx5_remove()
1045 sparx5_cleanup_ports(sparx5); in mchp_sparx5_remove()
1046 sparx5_vcap_destroy(sparx5); in mchp_sparx5_remove()
1048 sparx5_unregister_notifier_blocks(sparx5); in mchp_sparx5_remove()
1049 destroy_workqueue(sparx5->mact_queue); in mchp_sparx5_remove()
1115 { .compatible = "microchip,sparx5-switch", .data = &sparx5_desc },
1117 { .compatible = "microchip,lan9691-switch", .data = &lan969x_desc },
1127 .name = "sparx5-switch",
1134 MODULE_DESCRIPTION("Microchip Sparx5 switch driver");