Lines Matching +full:hw +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0
37 dev_err(rvu->dev, "Failed to setup lmt map table mapping!!\n"); in lmtst_map_table_ops()
38 return -ENOMEM; in lmtst_map_table_ops()
80 dev_err(rvu->dev, "%s Requested Null address for transulation\n", __func__); in rvu_get_lmtaddr()
81 return -EINVAL; in rvu_get_lmtaddr()
84 mutex_lock(&rvu->rsrc_lock); in rvu_get_lmtaddr()
93 dev_err(rvu->dev, "%s LMTLINE iova transulation failed\n", __func__); in rvu_get_lmtaddr()
98 dev_err(rvu->dev, "%s LMTLINE iova transulation failed err:%llx\n", __func__, val); in rvu_get_lmtaddr()
99 err = -EIO; in rvu_get_lmtaddr()
109 mutex_unlock(&rvu->rsrc_lock); in rvu_get_lmtaddr()
124 dev_err(rvu->dev, in rvu_update_lmtaddr()
134 if (!pfvf->lmt_base_addr) in rvu_update_lmtaddr()
135 pfvf->lmt_base_addr = val; in rvu_update_lmtaddr()
140 dev_err(rvu->dev, in rvu_update_lmtaddr()
152 struct rvu_pfvf *pfvf = rvu_get_pfvf(rvu, req->hdr.pcifunc); in rvu_mbox_handler_lmtst_tbl_setup()
162 if (req->use_local_lmt_region) { in rvu_mbox_handler_lmtst_tbl_setup()
163 err = rvu_get_lmtaddr(rvu, req->hdr.pcifunc, in rvu_mbox_handler_lmtst_tbl_setup()
164 req->lmt_iova, &lmt_addr); in rvu_mbox_handler_lmtst_tbl_setup()
169 err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, lmt_addr); in rvu_mbox_handler_lmtst_tbl_setup()
180 if (req->base_pcifunc) { in rvu_mbox_handler_lmtst_tbl_setup()
184 pri_tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->base_pcifunc); in rvu_mbox_handler_lmtst_tbl_setup()
190 dev_err(rvu->dev, in rvu_mbox_handler_lmtst_tbl_setup()
199 err = rvu_update_lmtaddr(rvu, req->hdr.pcifunc, val); in rvu_mbox_handler_lmtst_tbl_setup()
208 if (req->sch_ena || req->dis_sched_early_comp || req->dis_line_pref) { in rvu_mbox_handler_lmtst_tbl_setup()
209 tbl_idx = rvu_get_lmtst_tbl_index(rvu, req->hdr.pcifunc); in rvu_mbox_handler_lmtst_tbl_setup()
213 dev_err(rvu->dev, in rvu_mbox_handler_lmtst_tbl_setup()
223 if (!pfvf->lmt_map_ent_w1) in rvu_mbox_handler_lmtst_tbl_setup()
224 pfvf->lmt_map_ent_w1 = val; in rvu_mbox_handler_lmtst_tbl_setup()
227 if (req->dis_sched_early_comp) in rvu_mbox_handler_lmtst_tbl_setup()
228 val |= (req->dis_sched_early_comp << in rvu_mbox_handler_lmtst_tbl_setup()
231 if (req->sch_ena) in rvu_mbox_handler_lmtst_tbl_setup()
232 val |= (req->sch_ena << APR_LMT_MAP_ENT_SCH_ENA_SHIFT) | in rvu_mbox_handler_lmtst_tbl_setup()
233 req->ssow_pf_func; in rvu_mbox_handler_lmtst_tbl_setup()
235 if (req->dis_line_pref) in rvu_mbox_handler_lmtst_tbl_setup()
236 val |= (req->dis_line_pref << in rvu_mbox_handler_lmtst_tbl_setup()
242 dev_err(rvu->dev, in rvu_mbox_handler_lmtst_tbl_setup()
263 if (pfvf->lmt_base_addr || pfvf->lmt_map_ent_w1) { in rvu_reset_lmt_map_tbl()
269 if (pfvf->lmt_base_addr) { in rvu_reset_lmt_map_tbl()
271 &pfvf->lmt_base_addr, in rvu_reset_lmt_map_tbl()
274 dev_err(rvu->dev, in rvu_reset_lmt_map_tbl()
277 pfvf->lmt_base_addr = 0; in rvu_reset_lmt_map_tbl()
282 if (pfvf->lmt_map_ent_w1) { in rvu_reset_lmt_map_tbl()
285 &pfvf->lmt_map_ent_w1, in rvu_reset_lmt_map_tbl()
288 dev_err(rvu->dev, in rvu_reset_lmt_map_tbl()
291 pfvf->lmt_map_ent_w1 = 0; in rvu_reset_lmt_map_tbl()
300 struct rvu_hwinfo *hw = rvu->hw; in rvu_set_channels_base() local
311 hw->cgx = (nix_const >> 12) & 0xFULL; in rvu_set_channels_base()
312 hw->lmac_per_cgx = (nix_const >> 8) & 0xFULL; in rvu_set_channels_base()
313 hw->cgx_links = hw->cgx * hw->lmac_per_cgx; in rvu_set_channels_base()
314 hw->lbk_links = (nix_const >> 24) & 0xFULL; in rvu_set_channels_base()
315 hw->cpt_links = (nix_const >> 44) & 0xFULL; in rvu_set_channels_base()
316 hw->sdp_links = 1; in rvu_set_channels_base()
318 hw->cgx_chan_base = NIX_CHAN_CGX_LMAC_CHX(0, 0, 0); in rvu_set_channels_base()
319 hw->lbk_chan_base = NIX_CHAN_LBK_CHX(0, 0); in rvu_set_channels_base()
320 hw->sdp_chan_base = NIX_CHAN_SDP_CH_START; in rvu_set_channels_base()
322 /* No Programmable channels */ in rvu_set_channels_base()
326 hw->cap.programmable_chans = true; in rvu_set_channels_base()
328 /* If programmable channels are present then configure in rvu_set_channels_base()
329 * channels such that all channel numbers are contiguous in rvu_set_channels_base()
330 * leaving no holes. This way the new CPT channels can be in rvu_set_channels_base()
333 * of a block must be multiple of number of channels in rvu_set_channels_base()
341 sdp_chan_base = hw->lbk_chan_base + hw->lbk_links * nr_lbk_chans; in rvu_set_channels_base()
342 /* Round up base channel to multiple of number of channels */ in rvu_set_channels_base()
343 hw->sdp_chan_base = ALIGN(sdp_chan_base, nr_sdp_chans); in rvu_set_channels_base()
345 cgx_chan_base = hw->sdp_chan_base + hw->sdp_links * nr_sdp_chans; in rvu_set_channels_base()
346 hw->cgx_chan_base = ALIGN(cgx_chan_base, nr_cgx_chans); in rvu_set_channels_base()
348 cpt_chan_base = hw->cgx_chan_base + hw->cgx_links * nr_cgx_chans; in rvu_set_channels_base()
349 hw->cpt_chan_base = ALIGN(cpt_chan_base, nr_cpt_chans); in rvu_set_channels_base()
351 /* Out of 4096 channels start CPT from 2048 so in rvu_set_channels_base()
352 * that MSB for CPT channels is always set in rvu_set_channels_base()
355 hw->cpt_chan_base = NIX_CHAN_CPT_CH_START; in rvu_set_channels_base()
357 dev_err(rvu->dev, in rvu_set_channels_base()
358 "CPT channels could not fit in the range 2048-4095\n"); in rvu_set_channels_base()
359 return -EINVAL; in rvu_set_channels_base()
370 struct rvu_hwinfo *hw = rvu->hw; in __rvu_lbk_set_chans() local
378 cfg |= FIELD_PREP(LBK_LINK_CFG_BASE_MASK, hw->lbk_chan_base); in __rvu_lbk_set_chans()
395 * LBK0 - source NIX0 and destination NIX1 in rvu_lbk_set_channels()
396 * LBK1 - source NIX0 and destination NIX1 in rvu_lbk_set_channels()
397 * LBK2 - source NIX1 and destination NIX0 in rvu_lbk_set_channels()
398 * LBK3 - source NIX1 and destination NIX1 in rvu_lbk_set_channels()
456 struct rvu_hwinfo *hw = rvu->hw; in __rvu_nix_set_channels() local
466 start = hw->cgx_chan_base; in __rvu_nix_set_channels()
467 for (link = 0; link < hw->cgx_links; link++, nix_link++) { in __rvu_nix_set_channels()
476 start = hw->lbk_chan_base; in __rvu_nix_set_channels()
477 for (link = 0; link < hw->lbk_links; link++, nix_link++) { in __rvu_nix_set_channels()
486 start = hw->sdp_chan_base; in __rvu_nix_set_channels()
487 for (link = 0; link < hw->sdp_links; link++, nix_link++) { in __rvu_nix_set_channels()
496 start = hw->cpt_chan_base; in __rvu_nix_set_channels()
497 for (link = 0; link < hw->cpt_links; link++, nix_link++) { in __rvu_nix_set_channels()
525 /* There is no read-only constant register to read in __rvu_rpm_set_channels()
526 * the number of channels for LMAC and it is always 16. in __rvu_rpm_set_channels()
535 struct rvu_hwinfo *hw = rvu->hw; in rvu_rpm_set_channels() local
536 u16 base = hw->cgx_chan_base; in rvu_rpm_set_channels()
539 for (cgx = 0; cgx < rvu->cgx_cnt_max; cgx++) { in rvu_rpm_set_channels()
540 for (lmac = 0; lmac < hw->lmac_per_cgx; lmac++) { in rvu_rpm_set_channels()
549 struct rvu_hwinfo *hw = rvu->hw; in rvu_program_channels() local
551 if (!hw->cap.programmable_chans) in rvu_program_channels()
561 int blkaddr = nix_hw->blkaddr; in rvu_nix_block_cn10k_init()