1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright(c) 1999 - 2018 Intel Corporation. */
10  * ixgbe_dcb_config_rx_arbiter_82598 - Config Rx data arbiter
14  * @prio_type: priority type indexed by traffic class
21 	u32    reg           = 0;  in ixgbe_dcb_config_rx_arbiter_82598()
22 	u32    credit_refill = 0;  in ixgbe_dcb_config_rx_arbiter_82598()
23 	u32    credit_max    = 0;  in ixgbe_dcb_config_rx_arbiter_82598()
24 	u8     i             = 0;  in ixgbe_dcb_config_rx_arbiter_82598()
40 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_rx_arbiter_82598()
63 	return 0;  in ixgbe_dcb_config_rx_arbiter_82598()
67  * ixgbe_dcb_config_tx_desc_arbiter_82598 - Config Tx Desc. arbiter
71  * @bwg_id: bandwidth grouping indexed by traffic class
72  * @prio_type: priority type indexed by traffic class
89 	reg |= (0x4 << IXGBE_DPMCS_MTSOS_SHIFT);  in ixgbe_dcb_config_tx_desc_arbiter_82598()
94 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_tx_desc_arbiter_82598()
109 	return 0;  in ixgbe_dcb_config_tx_desc_arbiter_82598()
113  * ixgbe_dcb_config_tx_data_arbiter_82598 - Config Tx data arbiter
117  * @bwg_id: bandwidth grouping indexed by traffic class
118  * @prio_type: priority type indexed by traffic class
137 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_tx_data_arbiter_82598()
156 	return 0;  in ixgbe_dcb_config_tx_data_arbiter_82598()
160  * ixgbe_dcb_config_pfc_82598 - Config priority flow control
187 	for (i = 0; i < MAX_TRAFFIC_CLASS; i++) {  in ixgbe_dcb_config_pfc_82598()
189 			IXGBE_WRITE_REG(hw, IXGBE_FCRTL(i), 0);  in ixgbe_dcb_config_pfc_82598()
190 			IXGBE_WRITE_REG(hw, IXGBE_FCRTH(i), 0);  in ixgbe_dcb_config_pfc_82598()
194 		fcrtl = (hw->fc.low_water[i] << 10) | IXGBE_FCRTL_XONE;  in ixgbe_dcb_config_pfc_82598()
195 		reg = (hw->fc.high_water[i] << 10) | IXGBE_FCRTH_FCEN;  in ixgbe_dcb_config_pfc_82598()
201 	reg = hw->fc.pause_time * 0x00010001;  in ixgbe_dcb_config_pfc_82598()
202 	for (i = 0; i < (MAX_TRAFFIC_CLASS / 2); i++)  in ixgbe_dcb_config_pfc_82598()
206 	IXGBE_WRITE_REG(hw, IXGBE_FCRTV, hw->fc.pause_time / 2);  in ixgbe_dcb_config_pfc_82598()
209 	return 0;  in ixgbe_dcb_config_pfc_82598()
213  * ixgbe_dcb_config_tc_stats_82598 - Configure traffic class statistics
221 	u32 reg = 0;  in ixgbe_dcb_config_tc_stats_82598()
222 	u8  i   = 0;  in ixgbe_dcb_config_tc_stats_82598()
223 	u8  j   = 0;  in ixgbe_dcb_config_tc_stats_82598()
225 	/* Receive Queues stats setting -  8 queues per statistics reg */  in ixgbe_dcb_config_tc_stats_82598()
226 	for (i = 0, j = 0; i < 15 && j < 8; i = i + 2, j++) {  in ixgbe_dcb_config_tc_stats_82598()
228 		reg |= ((0x1010101) * j);  in ixgbe_dcb_config_tc_stats_82598()
231 		reg |= ((0x1010101) * j);  in ixgbe_dcb_config_tc_stats_82598()
234 	/* Transmit Queues stats setting -  4 queues per statistics reg */  in ixgbe_dcb_config_tc_stats_82598()
235 	for (i = 0; i < 8; i++) {  in ixgbe_dcb_config_tc_stats_82598()
237 		reg |= ((0x1010101) * i);  in ixgbe_dcb_config_tc_stats_82598()
241 	return 0;  in ixgbe_dcb_config_tc_stats_82598()
245  * ixgbe_dcb_hw_config_82598 - Config and enable DCB
250  * @bwg_id: bandwidth grouping indexed by traffic class
251  * @prio_type: priority type indexed by traffic class
266 	return 0;  in ixgbe_dcb_hw_config_82598()