Lines Matching +full:tx +full:- +full:output +full:- +full:config
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright(c) 2007 - 2018 Intel Corporation. */
62 /* Interrupt acknowledge Auto-mask */
118 #define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
119 #define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
184 #define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
186 #define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
254 /* Constants used to intrepret the masked PCI-X bus speed. */
271 /* 1000/H is not supported, nor spec-compliant. */
305 #define E1000_TCTL_EN 0x00000002 /* enable tx */
309 #define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
318 /* DMA Coalescing BMC-to-OS Watchdog Enable */
321 #define E1000_DMCTXTH_DMCTTHR_MASK 0x00000FFF /* DMA Coal Tx Threshold */
405 #define E1000_EICR_TX_QUEUE0 0x00000100 /* Tx Queue 0 Interrupt */
406 #define E1000_EICR_TX_QUEUE1 0x00000200 /* Tx Queue 1 Interrupt */
407 #define E1000_EICR_TX_QUEUE2 0x00000400 /* Tx Queue 2 Interrupt */
408 #define E1000_EICR_TX_QUEUE3 0x00000800 /* Tx Queue 3 Interrupt */
460 /* Transmit Config Word */
501 /* Loop limit on how long we wait for auto-negotiation to complete */
516 #define E1000_TSYNCTXCTL_VALID 0x00000001 /* tx timestamp valid */
517 #define E1000_TSYNCTXCTL_ENABLED 0x00000010 /* enable tx timestampping */
590 #define TS_SDP0_SEL_TT0 (0u << 6) /* Target time 0 is output on SDP0. */
591 #define TS_SDP0_SEL_TT1 (1u << 6) /* Target time 1 is output on SDP0. */
592 #define TS_SDP0_SEL_FC0 (2u << 6) /* Freq clock 0 is output on SDP0. */
593 #define TS_SDP0_SEL_FC1 (3u << 6) /* Freq clock 1 is output on SDP0. */
595 #define TS_SDP1_SEL_TT0 (0u << 9) /* Target time 0 is output on SDP1. */
596 #define TS_SDP1_SEL_TT1 (1u << 9) /* Target time 1 is output on SDP1. */
597 #define TS_SDP1_SEL_FC0 (2u << 9) /* Freq clock 0 is output on SDP1. */
598 #define TS_SDP1_SEL_FC1 (3u << 9) /* Freq clock 1 is output on SDP1. */
600 #define TS_SDP2_SEL_TT0 (0u << 12) /* Target time 0 is output on SDP2. */
601 #define TS_SDP2_SEL_TT1 (1u << 12) /* Target time 1 is output on SDP2. */
602 #define TS_SDP2_SEL_FC0 (2u << 12) /* Freq clock 0 is output on SDP2. */
603 #define TS_SDP2_SEL_FC1 (3u << 12) /* Freq clock 1 is output on SDP2. */
605 #define TS_SDP3_SEL_TT0 (0u << 15) /* Target time 0 is output on SDP3. */
606 #define TS_SDP3_SEL_TT1 (1u << 15) /* Target time 1 is output on SDP3. */
607 #define TS_SDP3_SEL_FC0 (2u << 15) /* Freq clock 0 is output on SDP3. */
608 #define TS_SDP3_SEL_FC1 (3u << 15) /* Freq clock 1 is output on SDP3. */
668 #define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
669 #define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
679 /* 1000BASE-T Control Register */
684 #define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
685 /* 0=Automatic Master/Slave config */
687 /* 1000BASE-T Status Register */
700 #define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
701 #define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
752 #define NVM_ID_LED_SETTINGS 0x0004 /* SERDES output amplitude */
803 #define E1000_NVM_CFG_DONE_PORT_0 0x040000 /* MNG config cycle done */
832 /* NVM Commands - Microwire */
834 /* NVM Commands - SPI */
838 #define NVM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = address bit-8 */
866 /* PCI/PCI-X/PCI-EX Config space */
871 #define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
904 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
908 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
909 * 0=Normal 10BASE-T Rx Threshold
911 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
919 * 1 = 50-80M
920 * 2 = 80-110M
921 * 3 = 110-140M
934 * within 1ms in 1000BASE-T
948 /* Intel i347-AT4 Registers */
957 /* i347-AT4 Extended PHY Specific Control Register */
973 /* i347-AT4 PHY Cable Diagnostics Control */
1003 #define E1000_EEER_TX_LPI_EN 0x00010000 /* EEE Tx LPI Enable */
1023 #define E1000_PCS_STATUS_TX_LPI_IND 0x0200 /* Tx in LPI state */
1036 /* Tx Rate-Scheduler Config fields */
1047 /* TX Qav Control fields */
1053 /* Fetch Time Delta - bits 31:16
1068 /* TX Qav Credit Control fields */