Lines Matching +full:quad +full:- +full:precision
1 // SPDX-License-Identifier: GPL-2.0
25 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
27 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
29 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, 0, },
30 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, 0, },
35 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
40 { "CVL-SDP22", ZL_REF0P, DPLL_PIN_TYPE_INT_OSCILLATOR,
42 { "CVL-SDP20", ZL_REF0N, DPLL_PIN_TYPE_INT_OSCILLATOR,
44 { "C827_0-RCLKA", ZL_REF1P, DPLL_PIN_TYPE_MUX, },
45 { "C827_0-RCLKB", ZL_REF1N, DPLL_PIN_TYPE_MUX, },
46 { "C827_1-RCLKA", ZL_REF2P, DPLL_PIN_TYPE_MUX, },
47 { "C827_1-RCLKB", ZL_REF2N, DPLL_PIN_TYPE_MUX, },
52 { "GNSS-1PPS", ZL_REF4P, DPLL_PIN_TYPE_GNSS,
57 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
59 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
61 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
62 { "MAC-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, },
63 { "CVL-SDP21", ZL_OUT4, DPLL_PIN_TYPE_EXT,
65 { "CVL-SDP23", ZL_OUT5, DPLL_PIN_TYPE_EXT,
70 { "REF-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
72 { "REF-SMA2/U.FL2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
74 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
75 { "PHY2-CLK", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
76 { "MAC-CLK", ZL_OUT4, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
77 { "CVL-SDP21", ZL_OUT5, DPLL_PIN_TYPE_EXT,
79 { "CVL-SDP23", ZL_OUT6, DPLL_PIN_TYPE_EXT,
98 { "1588-TIME_SYNC", SI_OUT0, DPLL_PIN_TYPE_EXT,
100 { "PHY-CLK", SI_OUT1, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
101 { "10MHZ-SMA2", SI_OUT2, DPLL_PIN_TYPE_EXT,
103 { "PPS-SMA1", SI_OUT3, DPLL_PIN_TYPE_EXT,
124 { "PPS-SMA1", ZL_OUT0, DPLL_PIN_TYPE_EXT,
126 { "10MHZ-SMA2", ZL_OUT1, DPLL_PIN_TYPE_EXT,
128 { "PHY-CLK", ZL_OUT2, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
129 { "1588-TIME_REF", ZL_OUT3, DPLL_PIN_TYPE_SYNCE_ETH_PORT, 0 },
130 { "CPK-TIME_SYNC", ZL_OUT4, DPLL_PIN_TYPE_EXT,
136 * for the Precision Time Protocol.
141 * +---------------+ +---------------+ +---------------+
143 * +---------------+ +---------------+ +---------------+
149 * +---------------+ +---------------+
151 * +---------------+ +---------------+
162 * - 823.4375 MHz
163 * - 783.36 MHz
164 * - 796.875 MHz
165 * - 816 MHz
166 * - 830.078125 MHz
167 * - 783.36 MHz
183 * - E822 based devices have additional support for fine grained Vernier
185 * - The layout of timestamp data in the PHY register blocks is different
186 * - The way timer synchronization commands are issued is different.
198 * ice_get_ptp_src_clock_index - determine source clock index
206 return hw->func_caps.ts_func_info.tmr_index_assoc; in ice_get_ptp_src_clock_index()
210 * ice_ptp_read_src_incval - Read source timer increment value
229 * ice_read_cgu_reg_e82x - Read a CGU register
261 * ice_write_cgu_reg_e82x - Write a CGU register
292 * ice_clk_freq_str - Convert time_ref_freq to string
318 * ice_clk_src_str - Convert time_ref_src to string
336 * ice_cfg_cgu_pll_e82x - Configure the Clock Generation Unit
345 * * %0 - success
346 * * %-EINVAL - input parameters are incorrect
347 * * %-EBUSY - failed to lock TS PLL
348 * * %other - CGU read/write failure
364 return -EINVAL; in ice_cfg_cgu_pll_e82x()
370 return -EINVAL; in ice_cfg_cgu_pll_e82x()
377 return -EINVAL; in ice_cfg_cgu_pll_e82x()
393 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e82x()
467 return -EBUSY; in ice_cfg_cgu_pll_e82x()
471 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e82x()
481 * ice_cfg_cgu_pll_e825c - Configure the Clock Generation Unit for E825-C
490 * * %0 - success
491 * * %-EINVAL - input parameters are incorrect
492 * * %-EBUSY - failed to lock TS PLL
493 * * %other - CGU read/write failure
511 return -EINVAL; in ice_cfg_cgu_pll_e825c()
517 return -EINVAL; in ice_cfg_cgu_pll_e825c()
524 return -EINVAL; in ice_cfg_cgu_pll_e825c()
548 ice_debug(hw, ICE_DBG_PTP, "Current CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e825c()
649 return -EBUSY; in ice_cfg_cgu_pll_e825c()
653 ice_debug(hw, ICE_DBG_PTP, "New CGU configuration -- %s, clk_src %s, clk_freq %s, PLL %s\n", in ice_cfg_cgu_pll_e825c()
665 * ice_cgu_cfg_pps_out - Configure 1PPS output from CGU
686 * ice_cfg_cgu_pll_dis_sticky_bits_e82x - disable TS PLL sticky bits
713 * ice_cfg_cgu_pll_dis_sticky_bits_e825c - disable TS PLL sticky bits for E825-C
736 * ice_init_cgu_e82x - Initialize CGU with settings from firmware
745 struct ice_ts_func_info *ts_info = &hw->func_caps.ts_func_info; in ice_init_cgu_e82x()
749 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) in ice_init_cgu_e82x()
759 if (hw->mac_type == ICE_MAC_GENERIC_3K_E825) in ice_init_cgu_e82x()
760 err = ice_cfg_cgu_pll_e825c(hw, ts_info->time_ref, in ice_init_cgu_e82x()
761 (enum ice_clk_src)ts_info->clk_src); in ice_init_cgu_e82x()
763 err = ice_cfg_cgu_pll_e82x(hw, ts_info->time_ref, in ice_init_cgu_e82x()
764 (enum ice_clk_src)ts_info->clk_src); in ice_init_cgu_e82x()
770 * ice_ptp_tmr_cmd_to_src_reg - Convert to source timer command value
811 * ice_ptp_tmr_cmd_to_port_reg- Convert to port timer command value
830 switch (hw->mac_type) { in ice_ptp_tmr_cmd_to_port_reg()
869 * ice_ptp_src_cmd - Prepare source timer for a timer command
883 * ice_ptp_exec_tmr_cmd - Execute all prepared timer commands
894 guard(spinlock)(&pf->adapter->ptp_gltsyn_time_lock); in ice_ptp_exec_tmr_cmd()
900 * ice_ptp_cfg_sync_delay - Configure PHC to PHY synchronization delay
916 * ice_ptp_get_dest_dev_e825 - get destination PHY for given port number
928 if (port >= hw->ptp.ports_per_phy) in ice_ptp_get_dest_dev_e825()
935 * ice_write_phy_eth56g - Write a PHY port register
963 * ice_read_phy_eth56g - Read a PHY port register
992 * ice_phy_res_address_eth56g - Calculate a PHY port register address
1000 * * %0 - success
1001 * * %EINVAL - invalid port number or resource type
1009 return -EINVAL; in ice_phy_res_address_eth56g()
1012 lane %= hw->ptp.ports_per_phy; in ice_phy_res_address_eth56g()
1020 * ice_write_port_eth56g - Write a PHY port register
1028 * * %0 - success
1029 * * %EINVAL - invalid port number or resource type
1030 * * %other - failed to write to PHY
1038 if (port >= hw->ptp.num_lports) in ice_write_port_eth56g()
1039 return -EINVAL; in ice_write_port_eth56g()
1049 * ice_read_port_eth56g - Read a PHY port register
1057 * * %0 - success
1058 * * %EINVAL - invalid port number or resource type
1059 * * %other - failed to read from PHY
1067 if (port >= hw->ptp.num_lports) in ice_read_port_eth56g()
1068 return -EINVAL; in ice_read_port_eth56g()
1078 * ice_write_ptp_reg_eth56g - Write a PHY port register
1085 * * %0 - success
1086 * * %EINVAL - invalid port number or resource type
1087 * * %other - failed to write to PHY
1096 * ice_write_mac_reg_eth56g - Write a MAC PHY port register
1104 * * %0 - success
1105 * * %EINVAL - invalid port number or resource type
1106 * * %other - failed to write to PHY
1115 * ice_write_xpcs_reg_eth56g - Write a PHY port register
1122 * * %0 - success
1123 * * %EINVAL - invalid port number or resource type
1124 * * %other - failed to write to PHY
1134 * ice_read_ptp_reg_eth56g - Read a PHY port register
1141 * * %0 - success
1142 * * %EINVAL - invalid port number or resource type
1143 * * %other - failed to read from PHY
1152 * ice_read_mac_reg_eth56g - Read a PHY port register
1159 * * %0 - success
1160 * * %EINVAL - invalid port number or resource type
1161 * * %other - failed to read from PHY
1170 * ice_read_gpcs_reg_eth56g - Read a PHY port register
1177 * * %0 - success
1178 * * %EINVAL - invalid port number or resource type
1179 * * %other - failed to read from PHY
1188 * ice_read_port_mem_eth56g - Read a PHY port memory location
1195 * * %0 - success
1196 * * %EINVAL - invalid port number or resource type
1197 * * %other - failed to read from PHY
1206 * ice_write_port_mem_eth56g - Write a PHY port memory location
1213 * * %0 - success
1214 * * %EINVAL - invalid port number or resource type
1215 * * %other - failed to write to PHY
1224 * ice_write_quad_ptp_reg_eth56g - Write a PHY quad register
1231 * * %0 - success
1232 * * %EIO - invalid port number or resource type
1233 * * %other - failed to write to PHY
1240 if (port >= hw->ptp.num_lports) in ice_write_quad_ptp_reg_eth56g()
1241 return -EIO; in ice_write_quad_ptp_reg_eth56g()
1249 * ice_read_quad_ptp_reg_eth56g - Read a PHY quad register
1256 * * %0 - success
1257 * * %EIO - invalid port number or resource type
1258 * * %other - failed to read from PHY
1265 if (port >= hw->ptp.num_lports) in ice_read_quad_ptp_reg_eth56g()
1266 return -EIO; in ice_read_quad_ptp_reg_eth56g()
1274 * ice_is_64b_phy_reg_eth56g - Check if this is a 64bit PHY register
1313 * ice_is_40b_phy_reg_eth56g - Check if this is a 40bit PHY register
1341 * ice_read_64b_phy_reg_eth56g - Read a 64bit value from PHY registers
1353 * * %0 - success
1354 * * %EINVAL - not a 64 bit register
1355 * * %other - failed to read from PHY
1365 return -EINVAL; in ice_read_64b_phy_reg_eth56g()
1387 * ice_read_64b_ptp_reg_eth56g - Read a 64bit value from PHY registers
1398 * * %0 - success
1399 * * %EINVAL - not a 64 bit register
1400 * * %other - failed to read from PHY
1410 * ice_write_40b_phy_reg_eth56g - Write a 40b value to the PHY
1422 * * %0 - success
1423 * * %EINVAL - not a 40 bit register
1424 * * %other - failed to write to PHY
1435 return -EINVAL; in ice_write_40b_phy_reg_eth56g()
1458 * ice_write_40b_ptp_reg_eth56g - Write a 40b value to the PHY
1469 * * %0 - success
1470 * * %EINVAL - not a 40 bit register
1471 * * %other - failed to write to PHY
1481 * ice_write_64b_phy_reg_eth56g - Write a 64bit value to PHY registers
1492 * * %0 - success
1493 * * %EINVAL - not a 64 bit register
1494 * * %other - failed to write to PHY
1505 return -EINVAL; in ice_write_64b_phy_reg_eth56g()
1528 * ice_write_64b_ptp_reg_eth56g - Write a 64bit value to PHY registers
1538 * * %0 - success
1539 * * %EINVAL - not a 64 bit register
1540 * * %other - failed to write to PHY
1550 * ice_read_ptp_tstamp_eth56g - Read a PHY timestamp out of the port memory
1560 * * %0 - success
1561 * * %other - failed to read from PHY
1597 * ice_clear_ptp_tstamp_eth56g - Clear a timestamp from the quad block
1599 * @port: the quad to read from
1614 * * %0 - success
1615 * * %other - failed to write to PHY
1645 * ice_ptp_reset_ts_memory_eth56g - Clear all timestamps from the port block
1652 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_reset_ts_memory_eth56g()
1661 * ice_ptp_prep_port_time_eth56g - Prepare one PHY port with initial time
1669 * * %0 - success
1670 * * %other - failed to write to PHY
1689 * ice_ptp_prep_phy_time_eth56g - Prepare PHY port with initial time
1699 * * %0 - success
1700 * * %other - failed to write to PHY
1712 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_time_eth56g()
1727 * ice_ptp_prep_port_adj_eth56g - Prepare a single port for time adjust
1737 * including the lower sub-nanosecond portion of the port timer.
1742 * * %0 - success
1743 * * %other - failed to write to PHY
1784 * ice_ptp_prep_phy_adj_eth56g - Prep PHY ports for a time adjustment
1793 * * %0 - success
1794 * * %other - failed to write to PHY
1801 /* The port clock supports adjustment of the sub-nanosecond portion of in ice_ptp_prep_phy_adj_eth56g()
1808 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_adj_eth56g()
1820 * ice_ptp_prep_phy_incval_eth56g - Prepare PHY ports for time adjustment
1829 * * %0 - success
1830 * * %other - failed to write to PHY
1836 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_incval_eth56g()
1852 * ice_ptp_read_port_capture_eth56g - Read a port's local time capture
1861 * * %0 - success
1862 * * %other - failed to read from PHY
1895 * ice_ptp_write_port_cmd_eth56g - Prepare a single PHY port for a timer command
1903 * * %0 - success
1904 * * %other - failed to write to PHY
1932 * ice_phy_get_speed_eth56g - Get link speed based on PHY link type
1940 u16 speed = ice_get_link_speed_based_on_phy_type(li->phy_type_low, in ice_phy_get_speed_eth56g()
1941 li->phy_type_high); in ice_phy_get_speed_eth56g()
1955 switch (li->phy_type_low) { in ice_phy_get_speed_eth56g()
1967 if (li->phy_type_high || in ice_phy_get_speed_eth56g()
1968 li->phy_type_low == ICE_PHY_TYPE_LOW_100GBASE_SR2) in ice_phy_get_speed_eth56g()
1978 * ice_phy_cfg_parpcs_eth56g - Configure TUs per PAR/PCS clock cycle
1986 * * %0 - success
1987 * * %other - PHY read/write failed
2002 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { in ice_phy_cfg_parpcs_eth56g()
2049 * ice_phy_cfg_ptp_1step_eth56g - Configure 1-step PTP settings
2054 * * %0 - success
2055 * * %other - PHY read/write failed
2064 enable = hw->ptp.phy.eth56g.onestep_ena; in ice_phy_cfg_ptp_1step_eth56g()
2065 peer_delay = hw->ptp.phy.eth56g.peer_delay; in ice_phy_cfg_ptp_1step_eth56g()
2066 sfd_ena = hw->ptp.phy.eth56g.sfd_ena; in ice_phy_cfg_ptp_1step_eth56g()
2106 switch (ice_phy_get_speed_eth56g(&hw->port_info->phy.link_info)) { in ice_phy_cfg_ptp_1step_eth56g()
2123 * mul_u32_u32_fx_q9 - Multiply two u32 fixed point Q9 values
2135 * add_u32_u32_fx - Add two u32 fixed point values and discard overflow
2147 * ice_ptp_calc_bitslip_eth56g - Calculate bitslip value
2151 * @fc: FC-FEC enabled
2152 * @rs: RS-FEC enabled
2190 bitslip = (u32)((s32)bitslip * -1 + 20); in ice_ptp_calc_bitslip_eth56g()
2198 * ice_ptp_calc_deskew_eth56g - Calculate deskew value
2202 * @rs: RS-FEC enabled
2233 deskew_f <<= ICE_ETH56G_MAC_CFG_FRAC_W - PHY_REG_DESKEW_0_RLEVEL_FRAC_W; in ice_ptp_calc_deskew_eth56g()
2238 * ice_phy_set_offsets_eth56g - Set Tx/Rx offset values
2243 * @fc: FC-FEC enabled
2244 * @rs: RS-FEC enabled
2247 * * %0 - success
2248 * * %other - failed to write to PHY
2258 onestep = hw->ptp.phy.eth56g.onestep_ena; in ice_phy_set_offsets_eth56g()
2259 sfd = hw->ptp.phy.eth56g.sfd_ena; in ice_phy_set_offsets_eth56g()
2260 bs_ds = cfg->rx_offset.bs_ds; in ice_phy_set_offsets_eth56g()
2263 rx_offset = cfg->rx_offset.fc; in ice_phy_set_offsets_eth56g()
2265 rx_offset = cfg->rx_offset.rs; in ice_phy_set_offsets_eth56g()
2267 rx_offset = cfg->rx_offset.no_fec; in ice_phy_set_offsets_eth56g()
2269 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.serdes); in ice_phy_set_offsets_eth56g()
2271 rx_offset = add_u32_u32_fx(rx_offset, cfg->rx_offset.sfd); in ice_phy_set_offsets_eth56g()
2283 tx_offset = cfg->tx_offset.fc; in ice_phy_set_offsets_eth56g()
2285 tx_offset = cfg->tx_offset.rs; in ice_phy_set_offsets_eth56g()
2287 tx_offset = cfg->tx_offset.no_fec; in ice_phy_set_offsets_eth56g()
2288 tx_offset += cfg->tx_offset.serdes + cfg->tx_offset.sfd * sfd + in ice_phy_set_offsets_eth56g()
2289 cfg->tx_offset.onestep * onestep; in ice_phy_set_offsets_eth56g()
2296 * ice_phy_cfg_mac_eth56g - Configure MAC for PTP
2301 * * %0 - success
2302 * * %other - failed to write to PHY
2315 onestep = hw->ptp.phy.eth56g.onestep_ena; in ice_phy_cfg_mac_eth56g()
2316 li = &hw->port_info->phy.link_info; in ice_phy_cfg_mac_eth56g()
2318 if (!!(li->an_info & ICE_AQ_FEC_EN)) { in ice_phy_cfg_mac_eth56g()
2322 fc = !!(li->fec_info & ICE_AQ_LINK_25G_KR_FEC_EN); in ice_phy_cfg_mac_eth56g()
2323 rs = !!(li->fec_info & ~ICE_AQ_LINK_25G_KR_FEC_EN); in ice_phy_cfg_mac_eth56g()
2337 cfg->tx_mode.def + rs * cfg->tx_mode.rs) | in ice_phy_cfg_mac_eth56g()
2338 FIELD_PREP(PHY_MAC_TSU_CFG_TX_MII_MK_DLY_M, cfg->tx_mk_dly) | in ice_phy_cfg_mac_eth56g()
2340 cfg->tx_cw_dly.def + in ice_phy_cfg_mac_eth56g()
2341 onestep * cfg->tx_cw_dly.onestep) | in ice_phy_cfg_mac_eth56g()
2343 cfg->rx_mode.def + rs * cfg->rx_mode.rs) | in ice_phy_cfg_mac_eth56g()
2345 cfg->rx_mk_dly.def + rs * cfg->rx_mk_dly.rs) | in ice_phy_cfg_mac_eth56g()
2347 cfg->rx_cw_dly.def + rs * cfg->rx_cw_dly.rs) | in ice_phy_cfg_mac_eth56g()
2348 FIELD_PREP(PHY_MAC_TSU_CFG_BLKS_PER_CLK_M, cfg->blks_per_clk); in ice_phy_cfg_mac_eth56g()
2354 cfg->blktime); in ice_phy_cfg_mac_eth56g()
2365 val = cfg->mktime; in ice_phy_cfg_mac_eth56g()
2371 * ice_phy_cfg_intr_eth56g - Configure TX timestamp interrupt
2380 * * %0 - success
2381 * * %other - PHY read/write failed
2404 * ice_read_phy_and_phc_time_eth56g - Simultaneously capture PHC and PHY time
2414 * * %0 - success
2415 * * %other - PHY read/write failed
2462 * ice_sync_phy_timer_eth56g - Synchronize the PHY timer with PHC timer
2474 * * %0 - success
2475 * * %-EBUSY- failed to acquire PTP semaphore
2476 * * %other - PHY read/write failed
2485 return -EBUSY; in ice_sync_phy_timer_eth56g()
2502 difference = phc_time - phy_time; in ice_sync_phy_timer_eth56g()
2515 /* Re-capture the timer values to flush the command registers and in ice_sync_phy_timer_eth56g()
2532 * ice_stop_phy_timer_eth56g - Stop the PHY clock timer
2538 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2542 * * %0 - success
2543 * * %other - failed to write to PHY
2563 * ice_start_phy_timer_eth56g - Start the PHY clock timer
2568 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
2572 * * %0 - success
2573 * * %other - PHY read/write failed
2634 * ice_sb_access_ena_eth56g - Enable SB devices (PHY and others) access
2653 * ice_ptp_init_phc_e825 - Perform E825 specific PHC initialization
2656 * Perform E825-specific PTP hardware clock initialization steps.
2669 * ice_ptp_read_tx_hwtstamp_status_eth56g - Get TX timestamp status
2677 * * %0 - success
2678 * * %other - failed to read from PHY
2682 const struct ice_eth56g_params *params = &hw->ptp.phy.eth56g; in ice_ptp_read_tx_hwtstamp_status_eth56g()
2686 mask = (1 << hw->ptp.ports_per_phy) - 1; in ice_ptp_read_tx_hwtstamp_status_eth56g()
2689 for (phy = 0; phy < params->num_phys; phy++) { in ice_ptp_read_tx_hwtstamp_status_eth56g()
2696 *ts_status |= (status & mask) << (phy * hw->ptp.ports_per_phy); in ice_ptp_read_tx_hwtstamp_status_eth56g()
2705 * ice_get_phy_tx_tstamp_ready_eth56g - Read the Tx memory status register
2715 * * %0 - success
2716 * * %other - failed to read from PHY
2735 * ice_ptp_init_phy_e825 - initialize PHY parameters
2740 struct ice_ptp_hw *ptp = &hw->ptp; in ice_ptp_init_phy_e825()
2743 params = &ptp->phy.eth56g; in ice_ptp_init_phy_e825()
2744 params->onestep_ena = false; in ice_ptp_init_phy_e825()
2745 params->peer_delay = 0; in ice_ptp_init_phy_e825()
2746 params->sfd_ena = false; in ice_ptp_init_phy_e825()
2747 params->num_phys = 2; in ice_ptp_init_phy_e825()
2748 ptp->ports_per_phy = 4; in ice_ptp_init_phy_e825()
2749 ptp->num_lports = params->num_phys * ptp->ports_per_phy; in ice_ptp_init_phy_e825()
2760 * ice_fill_phy_msg_e82x - Fill message data for a PHY register access
2772 phy_port = port % hw->ptp.ports_per_phy; in ice_fill_phy_msg_e82x()
2774 ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy); in ice_fill_phy_msg_e82x()
2777 msg->msg_addr_low = P_Q0_L(P_0_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2778 msg->msg_addr_high = P_Q0_H(P_0_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2780 msg->msg_addr_low = P_Q1_L(P_4_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2781 msg->msg_addr_high = P_Q1_H(P_4_BASE + offset, phy_port); in ice_fill_phy_msg_e82x()
2784 msg->dest_dev = rmn_0; in ice_fill_phy_msg_e82x()
2788 * ice_is_64b_phy_reg_e82x - Check if this is a 64bit PHY register
2841 * ice_is_40b_phy_reg_e82x - Check if this is a 40bit PHY register
2886 * ice_read_phy_reg_e82x - Read a PHY register
2916 * ice_read_64b_phy_reg_e82x - Read a 64bit value from PHY registers
2940 return -EINVAL; in ice_read_64b_phy_reg_e82x()
2963 * ice_write_phy_reg_e82x - Write a PHY register
2992 * ice_write_40b_phy_reg_e82x - Write a 40b value to the PHY
3014 return -EINVAL; in ice_write_40b_phy_reg_e82x()
3037 * ice_write_64b_phy_reg_e82x - Write a 64bit value to PHY registers
3061 return -EINVAL; in ice_write_64b_phy_reg_e82x()
3085 * ice_fill_quad_msg_e82x - Fill message data for quad register access
3088 * @quad: the quad to access
3091 * Fill a message buffer for accessing a register in a quad shared between
3095 * * %0 - OK
3096 * * %-EINVAL - invalid quad number
3099 struct ice_sbq_msg_input *msg, u8 quad, in ice_fill_quad_msg_e82x() argument
3104 if (quad >= ICE_GET_QUAD_NUM(hw->ptp.num_lports)) in ice_fill_quad_msg_e82x()
3105 return -EINVAL; in ice_fill_quad_msg_e82x()
3107 msg->dest_dev = rmn_0; in ice_fill_quad_msg_e82x()
3109 if (!(quad % ICE_GET_QUAD_NUM(hw->ptp.ports_per_phy))) in ice_fill_quad_msg_e82x()
3114 msg->msg_addr_low = lower_16_bits(addr); in ice_fill_quad_msg_e82x()
3115 msg->msg_addr_high = upper_16_bits(addr); in ice_fill_quad_msg_e82x()
3121 * ice_read_quad_reg_e82x - Read a PHY quad register
3123 * @quad: quad to read from
3124 * @offset: quad register offset to read
3125 * @val: on return, the contents read from the quad
3127 * Read a quad register over the device sideband queue. Quad registers are
3131 ice_read_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 *val) in ice_read_quad_reg_e82x() argument
3136 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); in ice_read_quad_reg_e82x()
3155 * ice_write_quad_reg_e82x - Write a PHY quad register
3157 * @quad: quad to write to
3158 * @offset: quad register offset to write
3161 * Write a quad register over the device sideband queue. Quad registers are
3165 ice_write_quad_reg_e82x(struct ice_hw *hw, u8 quad, u16 offset, u32 val) in ice_write_quad_reg_e82x() argument
3170 err = ice_fill_quad_msg_e82x(hw, &msg, quad, offset); in ice_write_quad_reg_e82x()
3188 * ice_read_phy_tstamp_e82x - Read a PHY timestamp out of the quad block
3190 * @quad: the quad to read from
3195 * quad memory block that is shared between the internal PHYs of the E822
3199 ice_read_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx, u64 *tstamp) in ice_read_phy_tstamp_e82x() argument
3208 err = ice_read_quad_reg_e82x(hw, quad, lo_addr, &lo); in ice_read_phy_tstamp_e82x()
3215 err = ice_read_quad_reg_e82x(hw, quad, hi_addr, &hi); in ice_read_phy_tstamp_e82x()
3233 * ice_clear_phy_tstamp_e82x - Clear a timestamp from the quad block
3235 * @quad: the quad to read from
3238 * Read the timestamp out of the quad to clear its timestamp status bit from
3239 * the PHY quad block that is shared between the internal PHYs of the E822
3242 * Note that unlike E810, software cannot directly write to the quad memory
3244 * to determine which timestamps are valid. Reading a timestamp auto-clears
3255 ice_clear_phy_tstamp_e82x(struct ice_hw *hw, u8 quad, u8 idx) in ice_clear_phy_tstamp_e82x() argument
3260 err = ice_read_phy_tstamp_e82x(hw, quad, idx, &unused_tstamp); in ice_clear_phy_tstamp_e82x()
3262 ice_debug(hw, ICE_DBG_PTP, "Failed to read the timestamp register for quad %u, idx %u, err %d\n", in ice_clear_phy_tstamp_e82x()
3263 quad, idx, err); in ice_clear_phy_tstamp_e82x()
3271 * ice_ptp_reset_ts_memory_quad_e82x - Clear all timestamps from the quad block
3273 * @quad: the quad to read from
3275 * Clear all timestamps from the PHY quad block that is shared between the
3278 void ice_ptp_reset_ts_memory_quad_e82x(struct ice_hw *hw, u8 quad) in ice_ptp_reset_ts_memory_quad_e82x() argument
3280 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, Q_REG_TS_CTRL_M); in ice_ptp_reset_ts_memory_quad_e82x()
3281 ice_write_quad_reg_e82x(hw, quad, Q_REG_TS_CTRL, ~(u32)Q_REG_TS_CTRL_M); in ice_ptp_reset_ts_memory_quad_e82x()
3285 * ice_ptp_reset_ts_memory_e82x - Clear all timestamps from all quad blocks
3290 unsigned int quad; in ice_ptp_reset_ts_memory_e82x() local
3292 for (quad = 0; quad < ICE_GET_QUAD_NUM(hw->ptp.num_lports); quad++) in ice_ptp_reset_ts_memory_e82x()
3293 ice_ptp_reset_ts_memory_quad_e82x(hw, quad); in ice_ptp_reset_ts_memory_e82x()
3297 * ice_ptp_set_vernier_wl - Set the window length for vernier calibration
3306 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_set_vernier_wl()
3322 * ice_ptp_init_phc_e82x - Perform E822 specific PHC initialization
3349 * ice_ptp_prep_phy_time_e82x - Prepare PHY port with initial time
3370 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_time_e82x()
3396 * ice_ptp_prep_port_adj_e82x - Prepare a single port for time adjust
3406 * including the lower sub-nanosecond portion of the port timer.
3450 * ice_ptp_prep_phy_adj_e82x - Prep PHY ports for a time adjustment
3464 /* The port clock supports adjustment of the sub-nanosecond portion of in ice_ptp_prep_phy_adj_e82x()
3471 cycles = -(((s64)-adj) << 32); in ice_ptp_prep_phy_adj_e82x()
3473 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_adj_e82x()
3485 * ice_ptp_prep_phy_incval_e82x - Prepare PHY ports for time adjustment
3499 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_prep_phy_incval_e82x()
3516 * ice_ptp_read_port_capture - Read a port's local time capture
3557 * ice_ptp_write_port_cmd_e82x - Prepare a single PHY port for a timer command
3568 * * %0 - success
3569 * * %other - failed to write to PHY
3600 * a port. This calibration increases the precision of the timestamps on the
3605 * ice_phy_get_speed_and_fec_e82x - Get link speed and FEC based on serdes mode
3608 * @link_out: if non-NULL, holds link speed on success
3609 * @fec_out: if non-NULL, holds FEC algorithm on success
3648 return -EIO; in ice_phy_get_speed_and_fec_e82x()
3668 return -EIO; in ice_phy_get_speed_and_fec_e82x()
3681 * ice_phy_cfg_lane_e82x - Configure PHY quad for single/multi-lane timestamp
3683 * @port: to configure the quad for
3690 u8 quad; in ice_phy_cfg_lane_e82x() local
3699 quad = ICE_GET_QUAD_NUM(port); in ice_phy_cfg_lane_e82x()
3701 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); in ice_phy_cfg_lane_e82x()
3713 err = ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); in ice_phy_cfg_lane_e82x()
3722 * ice_phy_cfg_uix_e82x - Configure Serdes UI to TU conversion for E822
3748 * -------+--------------+--------------+-------------
3752 * precision, we can take use the following equation:
3764 * a divide by 390,625,000. This does lose some precision, but avoids
3807 * ice_phy_cfg_parpcs_e82x - Configure TUs per PAR/PCS clock cycle
3816 * - Tx/Rx PAR/PCS markers
3819 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3822 * - Tx/Rx PAR/PCS markers
3823 * - Rx Deskew PAR/PCS markers
3826 * - Tx/Rx Reed Solomon gearbox PAR/PCS markers
3827 * - Rx Deskew PAR/PCS markers
3828 * - Tx PAR/PCS markers
3836 * -------+-------+--------
3969 * ice_calc_fixed_tx_offset_e82x - Calculated Fixed Tx offset for a port
4000 * ice_phy_cfg_tx_offset_e82x - Configure total Tx timestamp offset
4019 * Returns zero on success, -EBUSY if the hardware vernier offset
4049 return -EBUSY; in ice_phy_cfg_tx_offset_e82x()
4076 * multi-lane link speeds with RS-FEC. The lanes will always be in ice_phy_cfg_tx_offset_e82x()
4110 * ice_phy_calc_pmd_adj_e82x - Calculate PMD adjustment for Rx
4161 * For RS-FEC, if align is < 17 then we must also add 1.6 * 32/33. in ice_phy_calc_pmd_adj_e82x()
4212 /* Finally, for 25G-RS and 50G-RS, a further adjustment for the Rx in ice_phy_calc_pmd_adj_e82x()
4222 ice_debug(hw, ICE_DBG_PTP, "Failed to read 25G-RS Rx cycle count, err %d\n", in ice_phy_calc_pmd_adj_e82x()
4229 mult = (4 - rx_cycle) * 40; in ice_phy_calc_pmd_adj_e82x()
4244 ice_debug(hw, ICE_DBG_PTP, "Failed to read 50G-RS Rx cycle count, err %d\n", in ice_phy_calc_pmd_adj_e82x()
4268 * ice_calc_fixed_rx_offset_e82x - Calculated the fixed Rx offset for a port
4299 * ice_phy_cfg_rx_offset_e82x - Configure total Rx timestamp offset
4306 * well as adjusting for multi-lane alignment delay.
4322 * Returns zero on success, -EBUSY if the hardware vernier offset
4352 return -EBUSY; in ice_phy_cfg_rx_offset_e82x()
4371 /* For Rx, all multi-lane link speeds include a second Vernier in ice_phy_cfg_rx_offset_e82x()
4392 /* For RS-FEC, this adjustment adds delay, but for other modes, it in ice_phy_cfg_rx_offset_e82x()
4398 total_offset -= pmd; in ice_phy_cfg_rx_offset_e82x()
4420 * ice_ptp_clear_phy_offset_ready_e82x - Clear PHY TX_/RX_OFFSET_READY registers
4432 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_clear_phy_offset_ready_e82x()
4454 * ice_read_phy_and_phc_time_e82x - Simultaneously capture PHC and PHY time
4511 * ice_sync_phy_timer_e82x - Synchronize the PHY timer with PHC timer
4529 return -EBUSY; in ice_sync_phy_timer_e82x()
4544 difference = phc_time - phy_time; in ice_sync_phy_timer_e82x()
4560 /* Re-capture the timer values to flush the command registers and in ice_sync_phy_timer_e82x()
4582 * ice_stop_phy_timer_e82x - Stop the PHY clock timer
4588 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4632 * ice_start_phy_timer_e82x - Start the PHY clock timer
4637 * re-calibrate Tx and Rx timestamping offsets whenever the clock time is
4729 * ice_get_phy_tx_tstamp_ready_e82x - Read Tx memory status register
4731 * @quad: the timestamp quad to read from
4739 ice_get_phy_tx_tstamp_ready_e82x(struct ice_hw *hw, u8 quad, u64 *tstamp_ready) in ice_get_phy_tx_tstamp_ready_e82x() argument
4744 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_U, &hi); in ice_get_phy_tx_tstamp_ready_e82x()
4746 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_U for quad %u, err %d\n", in ice_get_phy_tx_tstamp_ready_e82x()
4747 quad, err); in ice_get_phy_tx_tstamp_ready_e82x()
4751 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEMORY_STATUS_L, &lo); in ice_get_phy_tx_tstamp_ready_e82x()
4753 ice_debug(hw, ICE_DBG_PTP, "Failed to read TX_MEMORY_STATUS_L for quad %u, err %d\n", in ice_get_phy_tx_tstamp_ready_e82x()
4754 quad, err); in ice_get_phy_tx_tstamp_ready_e82x()
4764 * ice_phy_cfg_intr_e82x - Configure TX timestamp interrupt
4766 * @quad: the timestamp quad
4770 * Configure TX timestamp interrupt for the specified quad
4772 * Return: 0 on success, other error codes when failed to read/write quad
4775 int ice_phy_cfg_intr_e82x(struct ice_hw *hw, u8 quad, bool ena, u8 threshold) in ice_phy_cfg_intr_e82x() argument
4780 err = ice_read_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, &val); in ice_phy_cfg_intr_e82x()
4791 return ice_write_quad_reg_e82x(hw, quad, Q_REG_TX_MEM_GBL_CFG, val); in ice_phy_cfg_intr_e82x()
4795 * ice_ptp_init_phy_e82x - initialize PHY parameters
4800 ptp->num_lports = 8; in ice_ptp_init_phy_e82x()
4801 ptp->ports_per_phy = 8; in ice_ptp_init_phy_e82x()
4811 * ice_read_phy_reg_e810 - Read register from external PHY on E810
4841 * ice_write_phy_reg_e810 - Write register on external PHY on E810
4870 * ice_read_phy_tstamp_ll_e810 - Read a PHY timestamp registers through the FW
4883 struct ice_e810_params *params = &hw->ptp.phy.e810; in ice_read_phy_tstamp_ll_e810()
4888 spin_lock_irqsave(¶ms->atqbal_wq.lock, flags); in ice_read_phy_tstamp_ll_e810()
4890 /* Wait for any pending in-progress low latency interrupt */ in ice_read_phy_tstamp_ll_e810()
4891 err = wait_event_interruptible_locked_irq(params->atqbal_wq, in ice_read_phy_tstamp_ll_e810()
4892 !(params->atqbal_flags & in ice_read_phy_tstamp_ll_e810()
4895 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); in ice_read_phy_tstamp_ll_e810()
4910 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); in ice_read_phy_tstamp_ll_e810()
4920 spin_unlock_irqrestore(¶ms->atqbal_wq.lock, flags); in ice_read_phy_tstamp_ll_e810()
4926 * ice_read_phy_tstamp_sbq_e810 - Read a PHY timestamp registers through the sbq
4966 * ice_read_phy_tstamp_e810 - Read a PHY timestamp out of the external PHY
4982 if (hw->dev_caps.ts_dev_info.ts_ll_read) in ice_read_phy_tstamp_e810()
5000 * ice_clear_phy_tstamp_e810 - Clear a timestamp from the external PHY
5045 * ice_ptp_init_phc_e810 - Perform E810 specific PHC initialization
5048 * Perform E810-specific PTP hardware clock initialization steps.
5059 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_phc_e810()
5070 * ice_ptp_prep_phy_time_e810 - Prepare PHY port with initial time
5086 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_time_e810()
5105 * ice_ptp_prep_phy_adj_ll_e810 - Prep PHY ports for a time adjustment
5112 * Return: 0 on success, -EBUSY on timeout
5116 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_adj_ll_e810()
5117 struct ice_e810_params *params = &hw->ptp.phy.e810; in ice_ptp_prep_phy_adj_ll_e810()
5121 spin_lock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_adj_ll_e810()
5123 /* Wait for any pending in-progress low latency interrupt */ in ice_ptp_prep_phy_adj_ll_e810()
5124 err = wait_event_interruptible_locked_irq(params->atqbal_wq, in ice_ptp_prep_phy_adj_ll_e810()
5125 !(params->atqbal_flags & in ice_ptp_prep_phy_adj_ll_e810()
5128 spin_unlock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_adj_ll_e810()
5144 spin_unlock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_adj_ll_e810()
5148 spin_unlock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_adj_ll_e810()
5154 * ice_ptp_prep_phy_adj_e810 - Prep PHY port for a time adjustment
5171 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) in ice_ptp_prep_phy_adj_e810()
5174 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_adj_e810()
5177 * nanoseconds. Sub-nanosecond adjustment is not supported. in ice_ptp_prep_phy_adj_e810()
5197 * ice_ptp_prep_phy_incval_ll_e810 - Prep PHY ports increment value change
5204 * Return: 0 on success, -EBUSY on timeout
5208 const u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_incval_ll_e810()
5209 struct ice_e810_params *params = &hw->ptp.phy.e810; in ice_ptp_prep_phy_incval_ll_e810()
5213 spin_lock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_incval_ll_e810()
5215 /* Wait for any pending in-progress low latency interrupt */ in ice_ptp_prep_phy_incval_ll_e810()
5216 err = wait_event_interruptible_locked_irq(params->atqbal_wq, in ice_ptp_prep_phy_incval_ll_e810()
5217 !(params->atqbal_flags & in ice_ptp_prep_phy_incval_ll_e810()
5220 spin_unlock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_incval_ll_e810()
5237 spin_unlock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_incval_ll_e810()
5241 spin_unlock_irq(¶ms->atqbal_wq.lock); in ice_ptp_prep_phy_incval_ll_e810()
5247 * ice_ptp_prep_phy_incval_e810 - Prep PHY port increment value change
5261 if (hw->dev_caps.ts_dev_info.ll_phy_tmr_update) in ice_ptp_prep_phy_incval_e810()
5264 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_prep_phy_incval_e810()
5286 * ice_ptp_port_cmd_e810 - Prepare all external PHYs for a timer command
5301 * ice_get_phy_tx_tstamp_ready_e810 - Read Tx memory status register
5327 * Read the SMA controller state. It is connected to pins 3-7 of Port 1 of the
5328 * PCA9575 expander, so only bits 3-7 in data are valid.
5360 * Write the data to the SMA controller. It is connected to pins 3-7 of Port 1
5361 * of the PCA9575 expander, so only bits 3-7 in data are valid.
5387 * ice_ptp_read_sdp_ac - read SDP available connections section from NVM
5415 err = -EINVAL; in ice_ptp_read_sdp_ac()
5447 * ice_ptp_init_phy_e810 - initialize PHY parameters
5452 ptp->num_lports = 8; in ice_ptp_init_phy_e810()
5453 ptp->ports_per_phy = 4; in ice_ptp_init_phy_e810()
5455 init_waitqueue_head(&ptp->phy.e810.atqbal_wq); in ice_ptp_init_phy_e810()
5465 * ice_ptp_init_phc_e830 - Perform E830 specific PHC initialization
5468 * Perform E830-specific PTP hardware clock initialization steps.
5476 * ice_ptp_write_direct_incval_e830 - Prep PHY port increment value change
5487 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_write_direct_incval_e830()
5494 * ice_ptp_write_direct_phc_time_e830 - Prepare PHY port with initial time
5508 u8 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_write_direct_phc_time_e830()
5516 * ice_ptp_port_cmd_e830 - Prepare all external PHYs for a timer command
5533 * ice_read_phy_tstamp_e830 - Read a PHY timestamp out of the external PHY
5557 * ice_get_phy_tx_tstamp_ready_e830 - Read Tx memory status register
5571 * ice_ptp_init_phy_e830 - initialize PHY parameters
5576 ptp->num_lports = 8; in ice_ptp_init_phy_e830()
5577 ptp->ports_per_phy = 4; in ice_ptp_init_phy_e830()
5587 * ice_ptp_lock - Acquire PTP global semaphore register lock
5609 hw_lock = rd32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id)); in ice_ptp_lock()
5624 * ice_ptp_unlock - Release PTP global semaphore register lock
5632 wr32(hw, PFTSYN_SEM + (PFTSYN_SEM_BYTES * hw->pf_id), 0); in ice_ptp_unlock()
5636 * ice_ptp_init_hw - Initialize hw based on device type
5644 struct ice_ptp_hw *ptp = &hw->ptp; in ice_ptp_init_hw()
5646 switch (hw->mac_type) { in ice_ptp_init_hw()
5665 * ice_ptp_write_port_cmd - Prepare a single PHY port for a timer command
5672 * ensure non-modified ports get properly initialized to ICE_PTP_NOP.
5675 * * %0 - success
5676 * %-EBUSY - PHY type not supported
5677 * * %other - failed to write port command
5682 switch (hw->mac_type) { in ice_ptp_write_port_cmd()
5688 return -EOPNOTSUPP; in ice_ptp_write_port_cmd()
5693 * ice_ptp_one_port_cmd - Program one PHY port for a timer command
5703 * * %0 - success
5704 * * %other - failed to write port command
5711 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_one_port_cmd()
5730 * ice_ptp_port_cmd - Prepare PHY ports for a timer sync command
5739 * * %0 - success
5740 * * %other - failed to write port command
5747 switch (hw->mac_type) { in ice_ptp_port_cmd()
5757 for (port = 0; port < hw->ptp.num_lports; port++) { in ice_ptp_port_cmd()
5769 * ice_ptp_tmr_cmd - Prepare and trigger a timer sync command
5802 * ice_ptp_init_time - Initialize device time to provided value
5819 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_time()
5823 if (hw->mac_type == ICE_MAC_E830) { in ice_ptp_init_time()
5834 switch (hw->mac_type) { in ice_ptp_init_time()
5846 err = -EOPNOTSUPP; in ice_ptp_init_time()
5856 * ice_ptp_write_incval - Program PHC with new increment value
5860 * Program the PHC with a new increment value. This requires a three-step
5874 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_write_incval()
5877 if (hw->mac_type == ICE_MAC_E830) { in ice_ptp_write_incval()
5886 switch (hw->mac_type) { in ice_ptp_write_incval()
5897 err = -EOPNOTSUPP; in ice_ptp_write_incval()
5907 * ice_ptp_write_incval_locked - Program new incval while holding semaphore
5918 return -EBUSY; in ice_ptp_write_incval_locked()
5928 * ice_ptp_adj_clock - Adjust PHC clock time atomically
5933 * nanoseconds. This requires a three-step process:
5945 tmr_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_adj_clock()
5955 switch (hw->mac_type) { in ice_ptp_adj_clock()
5969 err = -EOPNOTSUPP; in ice_ptp_adj_clock()
5979 * ice_read_phy_tstamp - Read a PHY timestamp from the timestamo block
5986 * the block is the quad to read from. For E810 devices, the block is the
5991 switch (hw->mac_type) { in ice_read_phy_tstamp()
6002 return -EOPNOTSUPP; in ice_read_phy_tstamp()
6007 * ice_clear_phy_tstamp - Clear a timestamp from the timestamp block
6016 * For E822 devices, the block number is the PHY quad to clear from. For E810
6024 switch (hw->mac_type) { in ice_clear_phy_tstamp()
6032 return -EOPNOTSUPP; in ice_clear_phy_tstamp()
6037 * ice_get_pf_c827_idx - find and return the C827 index for the current pf
6041 * * 0 - success
6042 * * negative - failure
6052 if (hw->mac_type != ICE_MAC_E810) in ice_get_pf_c827_idx()
6053 return -ENODEV; in ice_get_pf_c827_idx()
6055 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) { in ice_get_pf_c827_idx()
6069 return -ENOENT; in ice_get_pf_c827_idx()
6076 return -EIO; in ice_get_pf_c827_idx()
6082 * ice_ptp_reset_ts_memory - Reset timestamp memory for all blocks
6087 switch (hw->mac_type) { in ice_ptp_reset_ts_memory()
6101 * ice_ptp_init_phc - Initialize PTP hardware clock
6108 u8 src_idx = hw->func_caps.ts_func_info.tmr_index_owned; in ice_ptp_init_phc()
6116 switch (hw->mac_type) { in ice_ptp_init_phc()
6127 return -EOPNOTSUPP; in ice_ptp_init_phc()
6132 * ice_get_phy_tx_tstamp_ready - Read PHY Tx memory status indication
6144 switch (hw->mac_type) { in ice_get_phy_tx_tstamp_ready()
6158 return -EOPNOTSUPP; in ice_get_phy_tx_tstamp_ready()
6163 * ice_cgu_get_pin_desc_e823 - get pin description array
6175 if (hw->cgu_part_number == in ice_cgu_get_pin_desc_e823()
6184 } else if (hw->cgu_part_number == in ice_cgu_get_pin_desc_e823()
6202 * ice_cgu_get_pin_desc - get pin description array
6214 switch (hw->device_id) { in ice_cgu_get_pin_desc()
6253 * ice_cgu_get_num_pins - get pin description array size
6272 * ice_cgu_get_pin_type - get pin's type
6296 * ice_cgu_get_pin_freq_supp - get pin's supported frequency
6324 * ice_cgu_get_pin_name - get pin's name
6350 * ice_get_cgu_state - get the state of the DPLL
6360 * This function will read the state of the DPLL(dpll_idx). Non-null
6394 * it would never return to FREERUN. This aligns to ITU-T G.781 in ice_get_cgu_state()
6416 * ice_get_cgu_rclk_pin_info - get info on available recovered clock pins
6425 * * 0 - success, information is valid
6426 * * negative - failure, information is not valid
6433 switch (hw->device_id) { in ice_get_cgu_rclk_pin_info()
6456 if (hw->cgu_part_number == in ice_get_cgu_rclk_pin_info()
6459 else if (hw->cgu_part_number == in ice_get_cgu_rclk_pin_info()
6463 ret = -ENODEV; in ice_get_cgu_rclk_pin_info()
6467 ret = -ENODEV; in ice_get_cgu_rclk_pin_info()
6475 * ice_cgu_get_output_pin_state_caps - get output pin state capabilities
6481 * * 0 - success, state capabilities were modified
6482 * * negative - failure, capabilities were not modified
6489 switch (hw->device_id) { in ice_cgu_get_output_pin_state_caps()
6508 if (hw->cgu_part_number == in ice_cgu_get_output_pin_state_caps()
6512 else if (hw->cgu_part_number == in ice_cgu_get_output_pin_state_caps()
6518 return -EINVAL; in ice_cgu_get_output_pin_state_caps()