Lines Matching +full:30 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (c) 2018-2023, Intel Corporation. */
4 /* Machine-generated file */
27 #define PF_FW_ARQLEN_ARQVFE_M BIT(28)
28 #define PF_FW_ARQLEN_ARQOVFL_M BIT(29)
29 #define PF_FW_ARQLEN_ARQCRIT_M BIT(30)
30 #define PF_FW_ARQLEN_ARQENABLE_M BIT(31)
38 #define PF_FW_ATQLEN_ATQVFE_M BIT(28)
39 #define PF_FW_ATQLEN_ATQOVFL_M BIT(29)
40 #define PF_FW_ATQLEN_ATQCRIT_M BIT(30)
43 #define PF_FW_ATQLEN_ATQENABLE_M BIT(31)
51 #define PF_MBX_ARQLEN_ARQCRIT_M BIT(30)
52 #define PF_MBX_ARQLEN_ARQENABLE_M BIT(31)
60 #define PF_MBX_ATQLEN_ATQCRIT_M BIT(30)
61 #define PF_MBX_ATQLEN_ATQENABLE_M BIT(31)
78 #define PF_SB_ARQLEN_ARQVFE_M BIT(28)
80 #define PF_SB_ARQLEN_ARQOVFL_M BIT(29)
81 #define PF_SB_ARQLEN_ARQCRIT_S 30
82 #define PF_SB_ARQLEN_ARQCRIT_M BIT(30)
84 #define PF_SB_ARQLEN_ARQENABLE_M BIT(31)
101 #define PF_SB_ATQLEN_ATQVFE_M BIT(28)
103 #define PF_SB_ATQLEN_ATQOVFL_M BIT(29)
104 #define PF_SB_ATQLEN_ATQCRIT_S 30
105 #define PF_SB_ATQLEN_ATQCRIT_M BIT(30)
107 #define PF_SB_ATQLEN_ATQENABLE_M BIT(31)
127 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_S 30
128 #define GLFLXP_RXDID_FLX_WRD_0_RXDID_OPCODE_M ICE_M(0x3, 30)
132 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_S 30
133 #define GLFLXP_RXDID_FLX_WRD_1_RXDID_OPCODE_M ICE_M(0x3, 30)
137 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_S 30
138 #define GLFLXP_RXDID_FLX_WRD_2_RXDID_OPCODE_M ICE_M(0x3, 30)
142 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_S 30
143 #define GLFLXP_RXDID_FLX_WRD_3_RXDID_OPCODE_M ICE_M(0x3, 30)
149 #define QRXFLXP_CNTXT_TS_M BIT(11)
154 #define GLGEN_GPIO_CTL_PIN_DIR_M BIT(4)
165 #define GLGEN_RTRIG_CORER_M BIT(0)
166 #define GLGEN_RTRIG_GLOBR_M BIT(1)
169 #define GLGEN_SWITCH_MODE_CONFIG_25X4_QUAD_M BIT(2)
172 #define PFGEN_CTRL_PFSWR_M BIT(0)
177 #define VPGEN_VFRSTAT_VFRD_M BIT(0)
179 #define VPGEN_VFRTRIG_VFSWR_M BIT(0)
181 #define GLINT_CTL_DIS_AUTOMASK_M BIT(0)
193 #define GLINT_DYN_CTL_INTENA_M BIT(0)
194 #define GLINT_DYN_CTL_CLEARPBA_M BIT(1)
195 #define GLINT_DYN_CTL_SWINT_TRIG_M BIT(2)
200 #define GLINT_DYN_CTL_SW_ITR_INDX_ENA_M BIT(24)
203 #define GLINT_DYN_CTL_WB_ON_ITR_M BIT(30)
204 #define GLINT_DYN_CTL_INTENA_MSK_M BIT(31)
207 #define GLINT_RATE_INTRL_ENA_M BIT(6)
214 #define GLINT_VECT2FUNC_IS_PF_M BIT(16)
221 #define PFINT_FW_CTL_CAUSE_ENA_M BIT(30)
226 #define PFINT_MBX_CTL_CAUSE_ENA_M BIT(30)
228 #define PFINT_OICR_TSYN_TX_M BIT(11)
229 #define PFINT_OICR_TSYN_EVNT_M BIT(12)
230 #define PFINT_OICR_ECC_ERR_M BIT(16)
231 #define PFINT_OICR_MAL_DETECT_M BIT(19)
232 #define PFINT_OICR_GRST_M BIT(20)
233 #define PFINT_OICR_PCI_EXCEPTION_M BIT(21)
234 #define PFINT_OICR_HMC_ERR_M BIT(26)
235 #define PFINT_OICR_PE_PUSH_M BIT(27)
236 #define PFINT_OICR_PE_CRITERR_M BIT(28)
237 #define PFINT_OICR_VFLR_M BIT(29)
238 #define PFINT_OICR_SWINT_M BIT(31)
243 #define PFINT_OICR_CTL_CAUSE_ENA_M BIT(30)
247 #define PFINT_SB_CTL_CAUSE_ENA_M BIT(30)
254 #define QINT_RQCTL_CAUSE_ENA_M BIT(30)
260 #define QINT_TQCTL_CAUSE_ENA_M BIT(30)
266 #define VPINT_ALLOC_VALID_M BIT(31)
272 #define VPINT_ALLOC_PCI_VALID_M BIT(31)
274 #define VPINT_MBX_CTL_CAUSE_ENA_M BIT(30)
280 #define QRX_CTRL_QENA_REQ_M BIT(0)
282 #define QRX_CTRL_QENA_STAT_M BIT(2)
294 #define VPLAN_RXQ_MAPENA_RX_ENA_M BIT(0)
301 #define VPLAN_TXQ_MAPENA_TX_ENA_M BIT(0)
308 #define GL_MDCK_TX_TDPU_RCU_ANTISPOOF_ITR_DIS_M BIT(1)
318 #define GL_MDET_RX_VALID_M BIT(31)
328 #define GL_MDET_TX_PQM_VALID_M BIT(31)
330 ((hw)->mac_type == ICE_MAC_E830 ? E830_GL_MDET_TX_TCLAN : \
342 #define GL_MDET_TX_TCLAN_VALID_M BIT(31)
344 #define PF_MDET_RX_VALID_M BIT(0)
346 #define PF_MDET_TX_PQM_VALID_M BIT(0)
348 ((hw)->mac_type == ICE_MAC_E830 ? E830_PF_MDET_TX_TCLAN : \
352 #define PF_MDET_TX_TCLAN_VALID_M BIT(0)
354 #define VP_MDET_RX_VALID_M BIT(0)
356 #define VP_MDET_TX_PQM_VALID_M BIT(0)
358 #define VP_MDET_TX_TCLAN_VALID_M BIT(0)
360 #define VP_MDET_TX_TDPU_VALID_M BIT(0)
364 #define GL_MNG_FWSM_FW_LOADING_M BIT(30)
366 #define GLNVM_FLA_LOCKED_M BIT(6)
371 #define GLNVM_ULD_PCIER_DONE_M BIT(0)
372 #define GLNVM_ULD_PCIER_DONE_1_M BIT(1)
373 #define GLNVM_ULD_CORER_DONE_M BIT(3)
374 #define GLNVM_ULD_GLOBR_DONE_M BIT(4)
375 #define GLNVM_ULD_POR_DONE_M BIT(5)
376 #define GLNVM_ULD_POR_DONE_1_M BIT(8)
377 #define GLNVM_ULD_PCIER_DONE_2_M BIT(9)
378 #define GLNVM_ULD_PE_DONE_M BIT(10)
380 #define GLPCI_CNF2_CACHELINE_SIZE_M BIT(1)
388 #define GL_PWR_MODE_CTL_CAR_MAX_BW_S 30
389 #define GL_PWR_MODE_CTL_CAR_MAX_BW_M ICE_M(0x3, 30)
394 #define E800_GLQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
401 #define E800_GLQF_FD_SIZE_FD_BSIZE_M GENMASK(30, 16)
424 #define GLQF_HSYMM_ENABLE_BIT BIT(7)
427 #define E800_PFQF_FD_CNT_FD_BCNT_M GENMASK(30, 16)
430 #define PFQF_FD_ENA_FD_ENA_M BIT(0)
488 #define GLHH_ART_CTL_ACTIVE_M BIT(0)
492 #define GLTSYN_AUX_IN_0_INT_ENA_M BIT(4)
494 #define GLTSYN_AUX_OUT_0_OUT_ENA_M BIT(0)
500 #define GLTSYN_ENA_TSYN_ENA_M BIT(0)
513 #define GLTSYN_STAT_EVENT0_M BIT(0)
514 #define GLTSYN_STAT_EVENT1_M BIT(1)
515 #define GLTSYN_STAT_EVENT2_M BIT(2)
523 #define PFHH_SEM_BUSY_M BIT(0)
525 #define PFTSYN_SEM_BUSY_M BIT(0)
536 #define PFPM_APM_APME_M BIT(0)
538 #define PFPM_WUFC_MAG_M BIT(1)
540 #define PFPM_WUS_LNKC_M BIT(0)
541 #define PFPM_WUS_MAG_M BIT(1)
542 #define PFPM_WUS_MNG_M BIT(3)
543 #define PFPM_WUS_FW_RST_WK_M BIT(31)
553 #define E830_GLPTM_ART_CTL_ACTIVE_M BIT(0)
559 #define E830_PFPTM_SEM_BUSY_M BIT(0)
561 #define VFINT_DYN_CTLN_CLEARPBA_M BIT(1)