Lines Matching +full:quad +full:- +full:sgmii
1 // SPDX-License-Identifier: GPL-2.0
2 /* Copyright (c) 2018-2023, Intel Corporation. */
90 * ice_dump_phy_type - helper function to dump phy_type
117 * ice_set_mac_type - Sets MAC type
125 if (hw->vendor_id != PCI_VENDOR_ID_INTEL) in ice_set_mac_type()
126 return -ENODEV; in ice_set_mac_type()
128 switch (hw->device_id) { in ice_set_mac_type()
135 hw->mac_type = ICE_MAC_E810; in ice_set_mac_type()
156 hw->mac_type = ICE_MAC_GENERIC; in ice_set_mac_type()
162 hw->mac_type = ICE_MAC_GENERIC_3K_E825; in ice_set_mac_type()
174 hw->mac_type = ICE_MAC_E830; in ice_set_mac_type()
177 hw->mac_type = ICE_MAC_UNKNOWN; in ice_set_mac_type()
181 ice_debug(hw, ICE_DBG_INIT, "mac_type: %d\n", hw->mac_type); in ice_set_mac_type()
186 * ice_is_generic_mac - check if device's mac_type is generic
193 return (hw->mac_type == ICE_MAC_GENERIC || in ice_is_generic_mac()
194 hw->mac_type == ICE_MAC_GENERIC_3K_E825); in ice_is_generic_mac()
198 * ice_is_pf_c827 - check if pf contains c827 phy
210 if (hw->mac_type != ICE_MAC_E810) in ice_is_pf_c827()
213 if (hw->device_id != ICE_DEV_ID_E810C_QSFP) in ice_is_pf_c827()
234 * ice_clear_pf_cfg - Clear PF configuration
250 * ice_aq_manage_mac_read - manage MAC address read command
278 return -EINVAL; in ice_aq_manage_mac_read()
287 flags = le16_to_cpu(cmd->flags) & ICE_AQC_MAN_MAC_READ_M; in ice_aq_manage_mac_read()
291 return -EIO; in ice_aq_manage_mac_read()
295 for (i = 0; i < cmd->num_addr; i++) in ice_aq_manage_mac_read()
297 ether_addr_copy(hw->port_info->mac.lan_addr, in ice_aq_manage_mac_read()
299 ether_addr_copy(hw->port_info->mac.perm_addr, in ice_aq_manage_mac_read()
308 * ice_aq_get_phy_caps - returns PHY capabilities
332 return -EINVAL; in ice_aq_get_phy_caps()
333 hw = pi->hw; in ice_aq_get_phy_caps()
337 return -EINVAL; in ice_aq_get_phy_caps()
342 cmd->param0 |= cpu_to_le16(ICE_AQC_GET_PHY_RQM); in ice_aq_get_phy_caps()
344 cmd->param0 |= cpu_to_le16(report_mode); in ice_aq_get_phy_caps()
366 ice_dump_phy_type(hw, le64_to_cpu(pcaps->phy_type_low), in ice_aq_get_phy_caps()
367 le64_to_cpu(pcaps->phy_type_high), prefix); in ice_aq_get_phy_caps()
371 ice_debug(hw, ICE_DBG_LINK, "%s: caps = 0x%x\n", prefix, pcaps->caps); in ice_aq_get_phy_caps()
373 pcaps->low_power_ctrl_an); in ice_aq_get_phy_caps()
375 pcaps->eee_cap); in ice_aq_get_phy_caps()
377 pcaps->eeer_value); in ice_aq_get_phy_caps()
379 pcaps->link_fec_options); in ice_aq_get_phy_caps()
381 prefix, pcaps->module_compliance_enforcement); in ice_aq_get_phy_caps()
383 prefix, pcaps->extended_compliance_code); in ice_aq_get_phy_caps()
385 pcaps->module_type[0]); in ice_aq_get_phy_caps()
387 pcaps->module_type[1]); in ice_aq_get_phy_caps()
389 pcaps->module_type[2]); in ice_aq_get_phy_caps()
392 pi->phy.phy_type_low = le64_to_cpu(pcaps->phy_type_low); in ice_aq_get_phy_caps()
393 pi->phy.phy_type_high = le64_to_cpu(pcaps->phy_type_high); in ice_aq_get_phy_caps()
394 memcpy(pi->phy.link_info.module_type, &pcaps->module_type, in ice_aq_get_phy_caps()
395 sizeof(pi->phy.link_info.module_type)); in ice_aq_get_phy_caps()
402 * ice_aq_get_link_topo_handle - get link topology node return status
411 * connection type is backplane or BASE-T.
424 cmd->addr.topo_params.node_type_ctx = in ice_aq_get_link_topo_handle()
429 cmd->addr.topo_params.node_type_ctx |= in ice_aq_get_link_topo_handle()
432 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); in ice_aq_get_link_topo_handle()
454 return -EINTR; in ice_aq_get_netlist_node()
471 * @node_handle: output parameter if node found - optional
475 * If node_handle is non-NULL it will be modified on function exit. It is only
476 * valid if the function returns zero, and should be ignored on any non-zero
481 * * -ENOENT if no handle was found,
509 return -ENOENT; in ice_find_netlist_node()
517 * media type is backplane or BASE-T.
523 * connection type is backplane or BASE-T. in ice_is_media_cage_present()
531 * ice_get_media_type - Gets media type
541 hw_link_info = &pi->phy.link_info; in ice_get_media_type()
542 if (hw_link_info->phy_type_low && hw_link_info->phy_type_high) in ice_get_media_type()
546 if (hw_link_info->phy_type_low) { in ice_get_media_type()
547 /* 1G SGMII is a special case where some DA cable PHYs in ice_get_media_type()
549 * be since SGMII is meant to be between a MAC and a PHY in ice_get_media_type()
552 if (hw_link_info->phy_type_low == ICE_PHY_TYPE_LOW_1G_SGMII && in ice_get_media_type()
553 (hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == in ice_get_media_type()
555 hw_link_info->module_type[ICE_AQC_MOD_TYPE_IDENT] == in ice_get_media_type()
559 switch (hw_link_info->phy_type_low) { in ice_get_media_type()
631 switch (hw_link_info->phy_type_high) { in ice_get_media_type()
656 switch (hw->mac_type) { in ice_get_link_status_datalen()
669 * @link: pointer to link status structure - optional
690 return -EINVAL; in ice_aq_get_link_info()
691 hw = pi->hw; in ice_aq_get_link_info()
692 li_old = &pi->phy.link_info_old; in ice_aq_get_link_info()
693 hw_media_type = &pi->phy.media_type; in ice_aq_get_link_info()
694 li = &pi->phy.link_info; in ice_aq_get_link_info()
695 hw_fc_info = &pi->fc; in ice_aq_get_link_info()
700 resp->cmd_flags = cpu_to_le16(cmd_flags); in ice_aq_get_link_info()
701 resp->lport_num = pi->lport; in ice_aq_get_link_info()
712 li->link_speed = le16_to_cpu(link_data.link_speed); in ice_aq_get_link_info()
713 li->phy_type_low = le64_to_cpu(link_data.phy_type_low); in ice_aq_get_link_info()
714 li->phy_type_high = le64_to_cpu(link_data.phy_type_high); in ice_aq_get_link_info()
716 li->link_info = link_data.link_info; in ice_aq_get_link_info()
717 li->link_cfg_err = link_data.link_cfg_err; in ice_aq_get_link_info()
718 li->an_info = link_data.an_info; in ice_aq_get_link_info()
719 li->ext_info = link_data.ext_info; in ice_aq_get_link_info()
720 li->max_frame_size = le16_to_cpu(link_data.max_frame_size); in ice_aq_get_link_info()
721 li->fec_info = link_data.cfg & ICE_AQ_FEC_MASK; in ice_aq_get_link_info()
722 li->topo_media_conflict = link_data.topo_media_conflict; in ice_aq_get_link_info()
723 li->pacing = link_data.cfg & (ICE_AQ_CFG_PACING_M | in ice_aq_get_link_info()
730 hw_fc_info->current_mode = ICE_FC_FULL; in ice_aq_get_link_info()
732 hw_fc_info->current_mode = ICE_FC_TX_PAUSE; in ice_aq_get_link_info()
734 hw_fc_info->current_mode = ICE_FC_RX_PAUSE; in ice_aq_get_link_info()
736 hw_fc_info->current_mode = ICE_FC_NONE; in ice_aq_get_link_info()
738 li->lse_ena = !!(resp->cmd_flags & cpu_to_le16(ICE_AQ_LSE_IS_ENABLED)); in ice_aq_get_link_info()
741 ice_debug(hw, ICE_DBG_LINK, " link_speed = 0x%x\n", li->link_speed); in ice_aq_get_link_info()
743 (unsigned long long)li->phy_type_low); in ice_aq_get_link_info()
745 (unsigned long long)li->phy_type_high); in ice_aq_get_link_info()
747 ice_debug(hw, ICE_DBG_LINK, " link_info = 0x%x\n", li->link_info); in ice_aq_get_link_info()
748 ice_debug(hw, ICE_DBG_LINK, " link_cfg_err = 0x%x\n", li->link_cfg_err); in ice_aq_get_link_info()
749 ice_debug(hw, ICE_DBG_LINK, " an_info = 0x%x\n", li->an_info); in ice_aq_get_link_info()
750 ice_debug(hw, ICE_DBG_LINK, " ext_info = 0x%x\n", li->ext_info); in ice_aq_get_link_info()
751 ice_debug(hw, ICE_DBG_LINK, " fec_info = 0x%x\n", li->fec_info); in ice_aq_get_link_info()
752 ice_debug(hw, ICE_DBG_LINK, " lse_ena = 0x%x\n", li->lse_ena); in ice_aq_get_link_info()
754 li->max_frame_size); in ice_aq_get_link_info()
755 ice_debug(hw, ICE_DBG_LINK, " pacing = 0x%x\n", li->pacing); in ice_aq_get_link_info()
762 pi->phy.get_link_info = false; in ice_aq_get_link_info()
791 if (hw->mac_type == ICE_MAC_E830) { in ice_fill_tx_timer_and_fc_thresh()
794 cmd->tx_tmr_value = in ice_fill_tx_timer_and_fc_thresh()
804 cmd->tx_tmr_value = in ice_fill_tx_timer_and_fc_thresh()
813 cmd->fc_refresh_threshold = le16_encode_bits(val, fc_thres_m); in ice_fill_tx_timer_and_fc_thresh()
833 return -EINVAL; in ice_aq_set_mac_cfg()
837 cmd->max_frame_size = cpu_to_le16(max_frame_size); in ice_aq_set_mac_cfg()
845 * ice_init_fltr_mgmt_struct - initializes filter management list and locks
853 hw->switch_info = devm_kzalloc(ice_hw_to_dev(hw), in ice_init_fltr_mgmt_struct()
854 sizeof(*hw->switch_info), GFP_KERNEL); in ice_init_fltr_mgmt_struct()
855 sw = hw->switch_info; in ice_init_fltr_mgmt_struct()
858 return -ENOMEM; in ice_init_fltr_mgmt_struct()
860 INIT_LIST_HEAD(&sw->vsi_list_map_head); in ice_init_fltr_mgmt_struct()
861 sw->prof_res_bm_init = 0; in ice_init_fltr_mgmt_struct()
864 sw->recp_cnt = ICE_SW_LKUP_LAST; in ice_init_fltr_mgmt_struct()
868 devm_kfree(ice_hw_to_dev(hw), hw->switch_info); in ice_init_fltr_mgmt_struct()
875 * ice_cleanup_fltr_mgmt_struct - cleanup filter management list and locks
880 struct ice_switch_info *sw = hw->switch_info; in ice_cleanup_fltr_mgmt_struct()
886 list_for_each_entry_safe(v_pos_map, v_tmp_map, &sw->vsi_list_map_head, in ice_cleanup_fltr_mgmt_struct()
888 list_del(&v_pos_map->list_entry); in ice_cleanup_fltr_mgmt_struct()
891 recps = sw->recp_list; in ice_cleanup_fltr_mgmt_struct()
903 list_del(&lst_itr->list_entry); in ice_cleanup_fltr_mgmt_struct()
904 devm_kfree(ice_hw_to_dev(hw), lst_itr->lkups); in ice_cleanup_fltr_mgmt_struct()
914 list_del(&lst_itr->list_entry); in ice_cleanup_fltr_mgmt_struct()
920 devm_kfree(ice_hw_to_dev(hw), sw->recp_list); in ice_cleanup_fltr_mgmt_struct()
929 * bandwidth according to the device's configuration during power-on.
940 hw->itr_gran = ICE_ITR_GRAN_ABOVE_25; in ice_get_itr_intrl_gran()
941 hw->intrl_gran = ICE_INTRL_GRAN_ABOVE_25; in ice_get_itr_intrl_gran()
944 hw->itr_gran = ICE_ITR_GRAN_MAX_25; in ice_get_itr_intrl_gran()
945 hw->intrl_gran = ICE_INTRL_GRAN_MAX_25; in ice_get_itr_intrl_gran()
951 * ice_wait_for_fw - wait for full FW readiness
955 * Return: 0 on success, -ETIMEDOUT on timeout.
974 return -ETIMEDOUT; in ice_wait_for_fw()
978 * ice_init_hw - main hardware initialization routine
993 hw->pf_id = FIELD_GET(PF_FUNC_RID_FUNC_NUM_M, rd32(hw, PF_FUNC_RID)); in ice_init_hw()
1016 INIT_LIST_HEAD(&hw->fdir_list_head); in ice_init_hw()
1028 if (!hw->port_info) in ice_init_hw()
1029 hw->port_info = devm_kzalloc(ice_hw_to_dev(hw), in ice_init_hw()
1030 sizeof(*hw->port_info), in ice_init_hw()
1032 if (!hw->port_info) { in ice_init_hw()
1033 status = -ENOMEM; in ice_init_hw()
1037 hw->port_info->local_fwd_mode = ICE_LOCAL_FWD_MODE_ENABLED; in ice_init_hw()
1039 hw->port_info->hw = hw; in ice_init_hw()
1046 hw->evb_veb = true; in ice_init_hw()
1049 xa_init_flags(&hw->port_info->sched_node_ids, XA_FLAGS_ALLOC); in ice_init_hw()
1060 status = ice_sched_init_port(hw->port_info); in ice_init_hw()
1066 status = -ENOMEM; in ice_init_hw()
1071 status = ice_aq_get_phy_caps(hw->port_info, false, in ice_init_hw()
1079 status = ice_aq_get_link_info(hw->port_info, false, NULL, NULL); in ice_init_hw()
1084 if (!hw->sw_entry_point_layer) { in ice_init_hw()
1086 status = -EIO; in ice_init_hw()
1089 INIT_LIST_HEAD(&hw->agg_list); in ice_init_hw()
1091 if (!hw->max_burst_size) in ice_init_hw()
1103 status = -ENOMEM; in ice_init_hw()
1117 status = ice_alloc_fd_res_cntr(hw, &hw->fd_ctr_base); in ice_init_hw()
1123 mutex_init(&hw->tnl_lock); in ice_init_hw()
1144 devm_kfree(ice_hw_to_dev(hw), hw->port_info); in ice_init_hw()
1151 * ice_deinit_hw - unroll initialization operations done by ice_init_hw
1160 ice_free_fd_res_cntr(hw, hw->fd_ctr_base); in ice_deinit_hw()
1167 mutex_destroy(&hw->tnl_lock); in ice_deinit_hw()
1177 * ice_check_reset - Check to see if a global reset is complete
1200 return -EIO; in ice_check_reset()
1211 uld_mask = ICE_RESET_DONE_MASK | (hw->func_caps.common_cap.rdma ? in ice_check_reset()
1227 return -EIO; in ice_check_reset()
1234 * ice_pf_reset - Reset the PF
1253 return -EIO; in ice_pf_reset()
1278 return -EIO; in ice_pf_reset()
1285 * ice_reset - Perform different types of reset
1312 return -EINVAL; in ice_reset()
1324 * ice_copy_rxq_ctx_to_hw - Copy packed Rx queue context to HW registers
1344 PACKED_FIELD((lsb) + (width) - 1, (lsb), struct struct_name, struct_field)
1372 * ice_pack_rxq_ctx - Pack Rx queue context into a HW buffer
1376 * Pack the Rx queue context from the CPU-friendly unpacked buffer into its
1377 * bit-packed HW layout.
1387 * ice_write_rxq_ctx - Write Rx Queue context to hardware
1395 * Return: 0 on success, or -EINVAL if the Rx queue index is invalid.
1403 return -EINVAL; in ice_write_rxq_ctx()
1444 * ice_pack_txq_ctx - Pack Tx queue context into a HW buffer
1448 * Pack the Tx queue context from the CPU-friendly unpacked buffer into its
1449 * bit-packed HW layout.
1460 * ice_sbq_send_cmd - send Sideband Queue command to Sideband Queue
1476 * ice_sbq_rw_reg - Fill Sideband Queue command
1490 msg.dest_dev = in->dest_dev; in ice_sbq_rw_reg()
1491 msg.opcode = in->opcode; in ice_sbq_rw_reg()
1494 msg.msg_addr_low = cpu_to_le16(in->msg_addr_low); in ice_sbq_rw_reg()
1495 msg.msg_addr_high = cpu_to_le32(in->msg_addr_high); in ice_sbq_rw_reg()
1497 if (in->opcode) in ice_sbq_rw_reg()
1498 msg.data = cpu_to_le32(in->data); in ice_sbq_rw_reg()
1503 msg_len -= sizeof(msg.data); in ice_sbq_rw_reg()
1509 if (!status && !in->opcode) in ice_sbq_rw_reg()
1510 in->data = le32_to_cpu in ice_sbq_rw_reg()
1511 (((struct ice_sbq_msg_cmpl *)&msg)->data); in ice_sbq_rw_reg()
1544 * ice_sq_send_cmd_retry - send command to Control Queue (ATQ)
1566 opcode = le16_to_cpu(desc->opcode); in ice_sq_send_cmd_retry()
1581 hw->adminq.sq_last_status != ICE_AQ_RC_EBUSY) in ice_sq_send_cmd_retry()
1594 * ice_aq_send_cmd - send FW Admin Queue command to FW Admin Queue
1607 struct ice_aqc_req_res *cmd = &desc->params.res_owner; in ice_aq_send_cmd()
1621 switch (le16_to_cpu(desc->opcode)) { in ice_aq_send_cmd()
1638 if (le16_to_cpu(cmd->res_id) == ICE_AQC_RES_ID_GLBL_LOCK) in ice_aq_send_cmd()
1647 status = ice_sq_send_cmd_retry(hw, &hw->adminq, desc, buf, buf_size, cd); in ice_aq_send_cmd()
1674 hw->fw_branch = resp->fw_branch; in ice_aq_get_fw_ver()
1675 hw->fw_maj_ver = resp->fw_major; in ice_aq_get_fw_ver()
1676 hw->fw_min_ver = resp->fw_minor; in ice_aq_get_fw_ver()
1677 hw->fw_patch = resp->fw_patch; in ice_aq_get_fw_ver()
1678 hw->fw_build = le32_to_cpu(resp->fw_build); in ice_aq_get_fw_ver()
1679 hw->api_branch = resp->api_branch; in ice_aq_get_fw_ver()
1680 hw->api_maj_ver = resp->api_major; in ice_aq_get_fw_ver()
1681 hw->api_min_ver = resp->api_minor; in ice_aq_get_fw_ver()
1682 hw->api_patch = resp->api_patch; in ice_aq_get_fw_ver()
1707 return -EINVAL; in ice_aq_send_driver_ver()
1712 cmd->major_ver = dv->major_ver; in ice_aq_send_driver_ver()
1713 cmd->minor_ver = dv->minor_ver; in ice_aq_send_driver_ver()
1714 cmd->build_ver = dv->build_ver; in ice_aq_send_driver_ver()
1715 cmd->subbuild_ver = dv->subbuild_ver; in ice_aq_send_driver_ver()
1718 while (len < sizeof(dv->driver_string) && in ice_aq_send_driver_ver()
1719 isascii(dv->driver_string[len]) && dv->driver_string[len]) in ice_aq_send_driver_ver()
1722 return ice_aq_send_cmd(hw, &desc, dv->driver_string, len, cd); in ice_aq_send_driver_ver()
1743 cmd->driver_unloading = ICE_AQC_DRIVER_UNLOADING; in ice_aq_q_shutdown()
1760 * 1) 0 - acquired lock, and can perform download package
1761 * 2) -EIO - did not get lock, driver should fail to load
1762 * 3) -EALREADY - did not get lock, but another driver has
1787 cmd_resp->res_id = cpu_to_le16(res); in ice_aq_req_res()
1788 cmd_resp->access_type = cpu_to_le16(access); in ice_aq_req_res()
1789 cmd_resp->res_number = cpu_to_le32(sdp_number); in ice_aq_req_res()
1790 cmd_resp->timeout = cpu_to_le32(*timeout); in ice_aq_req_res()
1807 if (le16_to_cpu(cmd_resp->status) == ICE_AQ_RES_GLBL_SUCCESS) { in ice_aq_req_res()
1808 *timeout = le32_to_cpu(cmd_resp->timeout); in ice_aq_req_res()
1810 } else if (le16_to_cpu(cmd_resp->status) == in ice_aq_req_res()
1812 *timeout = le32_to_cpu(cmd_resp->timeout); in ice_aq_req_res()
1813 return -EIO; in ice_aq_req_res()
1814 } else if (le16_to_cpu(cmd_resp->status) == in ice_aq_req_res()
1816 return -EALREADY; in ice_aq_req_res()
1821 return -EIO; in ice_aq_req_res()
1828 if (!status || hw->adminq.sq_last_status == ICE_AQ_RC_EBUSY) in ice_aq_req_res()
1829 *timeout = le32_to_cpu(cmd_resp->timeout); in ice_aq_req_res()
1854 cmd->res_id = cpu_to_le16(res); in ice_aq_release_res()
1855 cmd->res_number = cpu_to_le32(sdp_number); in ice_aq_release_res()
1880 /* A return code of -EALREADY means that another driver has in ice_acquire_res()
1885 if (status == -EALREADY) in ice_acquire_res()
1895 timeout = (timeout > delay) ? timeout - delay : 0; in ice_acquire_res()
1898 if (status == -EALREADY) in ice_acquire_res()
1906 if (status && status != -EALREADY) in ice_acquire_res()
1910 if (status == -EALREADY) { in ice_acquire_res()
1914 ice_debug(hw, ICE_DBG_RES, "Warning: -EALREADY not expected\n"); in ice_acquire_res()
1937 if (status != -EIO) in ice_release_res()
1944 * ice_aq_alloc_free_res - command to allocate/free resources
1962 return -EINVAL; in ice_aq_alloc_free_res()
1968 cmd->num_entries = cpu_to_le16(1); in ice_aq_alloc_free_res()
1974 * ice_alloc_hw_res - allocate resource
1991 return -ENOMEM; in ice_alloc_hw_res()
1994 buf->num_elems = cpu_to_le16(num); in ice_alloc_hw_res()
1995 buf->res_type = cpu_to_le16(type | ICE_AQC_RES_TYPE_FLAG_DEDICATED | in ice_alloc_hw_res()
1998 buf->res_type |= cpu_to_le16(ICE_AQC_RES_TYPE_FLAG_SCAN_BOTTOM); in ice_alloc_hw_res()
2004 memcpy(res, buf->elem, sizeof(*buf->elem) * num); in ice_alloc_hw_res()
2012 * ice_free_hw_res - free allocated HW resource
2027 return -ENOMEM; in ice_free_hw_res()
2030 buf->num_elems = cpu_to_le16(num); in ice_free_hw_res()
2031 buf->res_type = cpu_to_le16(type); in ice_free_hw_res()
2032 memcpy(buf->elem, res, sizeof(*buf->elem) * num); in ice_free_hw_res()
2043 * ice_get_num_per_func - determine number of resources per PF
2056 funcs = hweight8(hw->dev_caps.common_cap.valid_functions & in ice_get_num_per_func()
2066 * ice_parse_common_caps - parse common device/function capabilities
2082 u32 logical_id = le32_to_cpu(elem->logical_id); in ice_parse_common_caps()
2083 u32 phys_id = le32_to_cpu(elem->phys_id); in ice_parse_common_caps()
2084 u32 number = le32_to_cpu(elem->number); in ice_parse_common_caps()
2085 u16 cap = le16_to_cpu(elem->cap); in ice_parse_common_caps()
2090 caps->valid_functions = number; in ice_parse_common_caps()
2092 caps->valid_functions); in ice_parse_common_caps()
2095 caps->sr_iov_1_1 = (number == 1); in ice_parse_common_caps()
2097 caps->sr_iov_1_1); in ice_parse_common_caps()
2100 caps->dcb = (number == 1); in ice_parse_common_caps()
2101 caps->active_tc_bitmap = logical_id; in ice_parse_common_caps()
2102 caps->maxtc = phys_id; in ice_parse_common_caps()
2103 ice_debug(hw, ICE_DBG_INIT, "%s: dcb = %d\n", prefix, caps->dcb); in ice_parse_common_caps()
2105 caps->active_tc_bitmap); in ice_parse_common_caps()
2106 ice_debug(hw, ICE_DBG_INIT, "%s: maxtc = %d\n", prefix, caps->maxtc); in ice_parse_common_caps()
2109 caps->rss_table_size = number; in ice_parse_common_caps()
2110 caps->rss_table_entry_width = logical_id; in ice_parse_common_caps()
2112 caps->rss_table_size); in ice_parse_common_caps()
2114 caps->rss_table_entry_width); in ice_parse_common_caps()
2117 caps->num_rxq = number; in ice_parse_common_caps()
2118 caps->rxq_first_id = phys_id; in ice_parse_common_caps()
2120 caps->num_rxq); in ice_parse_common_caps()
2122 caps->rxq_first_id); in ice_parse_common_caps()
2125 caps->num_txq = number; in ice_parse_common_caps()
2126 caps->txq_first_id = phys_id; in ice_parse_common_caps()
2128 caps->num_txq); in ice_parse_common_caps()
2130 caps->txq_first_id); in ice_parse_common_caps()
2133 caps->num_msix_vectors = number; in ice_parse_common_caps()
2134 caps->msix_vector_first_id = phys_id; in ice_parse_common_caps()
2136 caps->num_msix_vectors); in ice_parse_common_caps()
2138 caps->msix_vector_first_id); in ice_parse_common_caps()
2141 caps->nvm_update_pending_nvm = true; in ice_parse_common_caps()
2145 caps->nvm_update_pending_orom = true; in ice_parse_common_caps()
2149 caps->nvm_update_pending_netlist = true; in ice_parse_common_caps()
2153 caps->nvm_unified_update = in ice_parse_common_caps()
2157 caps->nvm_unified_update); in ice_parse_common_caps()
2161 caps->rdma = (number == 1); in ice_parse_common_caps()
2162 ice_debug(hw, ICE_DBG_INIT, "%s: rdma = %d\n", prefix, caps->rdma); in ice_parse_common_caps()
2165 caps->max_mtu = number; in ice_parse_common_caps()
2167 prefix, caps->max_mtu); in ice_parse_common_caps()
2170 caps->pcie_reset_avoidance = (number > 0); in ice_parse_common_caps()
2173 caps->pcie_reset_avoidance); in ice_parse_common_caps()
2176 caps->reset_restrict_support = (number == 1); in ice_parse_common_caps()
2179 caps->reset_restrict_support); in ice_parse_common_caps()
2182 caps->roce_lag = !!(number & ICE_AQC_BIT_ROCEV2_LAG); in ice_parse_common_caps()
2184 prefix, caps->roce_lag); in ice_parse_common_caps()
2185 caps->sriov_lag = !!(number & ICE_AQC_BIT_SRIOV_LAG); in ice_parse_common_caps()
2187 prefix, caps->sriov_lag); in ice_parse_common_caps()
2190 caps->tx_sched_topo_comp_mode_en = (number == 1); in ice_parse_common_caps()
2201 * ice_recalc_port_limited_caps - Recalculate port limited capabilities
2205 * Re-calculate the capabilities that are dependent on the number of physical
2215 if (hw->dev_caps.num_funcs > 4) { in ice_recalc_port_limited_caps()
2217 caps->maxtc = 4; in ice_recalc_port_limited_caps()
2219 caps->maxtc); in ice_recalc_port_limited_caps()
2220 if (caps->rdma) { in ice_recalc_port_limited_caps()
2222 caps->rdma = 0; in ice_recalc_port_limited_caps()
2228 if (caps == &hw->dev_caps.common_cap) in ice_recalc_port_limited_caps()
2234 * ice_parse_vf_func_caps - Parse ICE_AQC_CAPS_VF function caps
2245 u32 logical_id = le32_to_cpu(cap->logical_id); in ice_parse_vf_func_caps()
2246 u32 number = le32_to_cpu(cap->number); in ice_parse_vf_func_caps()
2248 func_p->num_allocd_vfs = number; in ice_parse_vf_func_caps()
2249 func_p->vf_base_id = logical_id; in ice_parse_vf_func_caps()
2251 func_p->num_allocd_vfs); in ice_parse_vf_func_caps()
2253 func_p->vf_base_id); in ice_parse_vf_func_caps()
2257 * ice_parse_vsi_func_caps - Parse ICE_AQC_CAPS_VSI function caps
2268 func_p->guar_num_vsi = ice_get_num_per_func(hw, ICE_MAX_VSI); in ice_parse_vsi_func_caps()
2270 le32_to_cpu(cap->number)); in ice_parse_vsi_func_caps()
2272 func_p->guar_num_vsi); in ice_parse_vsi_func_caps()
2276 * ice_parse_1588_func_caps - Parse ICE_AQC_CAPS_1588 function caps
2287 struct ice_ts_func_info *info = &func_p->ts_func_info; in ice_parse_1588_func_caps()
2288 u32 number = le32_to_cpu(cap->number); in ice_parse_1588_func_caps()
2290 info->ena = ((number & ICE_TS_FUNC_ENA_M) != 0); in ice_parse_1588_func_caps()
2291 func_p->common_cap.ieee_1588 = info->ena; in ice_parse_1588_func_caps()
2293 info->src_tmr_owned = ((number & ICE_TS_SRC_TMR_OWND_M) != 0); in ice_parse_1588_func_caps()
2294 info->tmr_ena = ((number & ICE_TS_TMR_ENA_M) != 0); in ice_parse_1588_func_caps()
2295 info->tmr_index_owned = ((number & ICE_TS_TMR_IDX_OWND_M) != 0); in ice_parse_1588_func_caps()
2296 info->tmr_index_assoc = ((number & ICE_TS_TMR_IDX_ASSOC_M) != 0); in ice_parse_1588_func_caps()
2298 if (hw->mac_type != ICE_MAC_GENERIC_3K_E825) { in ice_parse_1588_func_caps()
2299 info->clk_freq = FIELD_GET(ICE_TS_CLK_FREQ_M, number); in ice_parse_1588_func_caps()
2300 info->clk_src = ((number & ICE_TS_CLK_SRC_M) != 0); in ice_parse_1588_func_caps()
2302 info->clk_freq = ICE_TIME_REF_FREQ_156_250; in ice_parse_1588_func_caps()
2303 info->clk_src = ICE_CLK_SRC_TCXO; in ice_parse_1588_func_caps()
2306 if (info->clk_freq < NUM_ICE_TIME_REF_FREQ) { in ice_parse_1588_func_caps()
2307 info->time_ref = (enum ice_time_ref_freq)info->clk_freq; in ice_parse_1588_func_caps()
2310 * default to avoid out-of-bounds look ups of frequency in ice_parse_1588_func_caps()
2314 info->clk_freq); in ice_parse_1588_func_caps()
2315 info->time_ref = ICE_TIME_REF_FREQ_25_000; in ice_parse_1588_func_caps()
2319 func_p->common_cap.ieee_1588); in ice_parse_1588_func_caps()
2321 info->src_tmr_owned); in ice_parse_1588_func_caps()
2323 info->tmr_ena); in ice_parse_1588_func_caps()
2325 info->tmr_index_owned); in ice_parse_1588_func_caps()
2327 info->tmr_index_assoc); in ice_parse_1588_func_caps()
2329 info->clk_freq); in ice_parse_1588_func_caps()
2331 info->clk_src); in ice_parse_1588_func_caps()
2335 * ice_parse_fdir_func_caps - Parse ICE_AQC_CAPS_FD function caps
2347 switch (hw->mac_type) { in ice_parse_fdir_func_caps()
2357 func_p->fd_fltr_guar = ice_get_num_per_func(hw, gsize); in ice_parse_fdir_func_caps()
2358 func_p->fd_fltr_best_effort = bsize; in ice_parse_fdir_func_caps()
2361 func_p->fd_fltr_guar); in ice_parse_fdir_func_caps()
2363 func_p->fd_fltr_best_effort); in ice_parse_fdir_func_caps()
2367 * ice_parse_func_caps - Parse function capabilities
2395 found = ice_parse_common_caps(hw, &func_p->common_cap, in ice_parse_func_caps()
2420 ice_recalc_port_limited_caps(hw, &func_p->common_cap); in ice_parse_func_caps()
2424 * ice_func_id_to_logical_id - map from function id to logical pf id
2443 * ice_parse_valid_functions_cap - Parse ICE_AQC_CAPS_VALID_FUNCTIONS caps
2454 u32 number = le32_to_cpu(cap->number); in ice_parse_valid_functions_cap()
2456 dev_p->num_funcs = hweight32(number); in ice_parse_valid_functions_cap()
2458 dev_p->num_funcs); in ice_parse_valid_functions_cap()
2460 hw->logical_pf_id = ice_func_id_to_logical_id(number, hw->pf_id); in ice_parse_valid_functions_cap()
2464 * ice_parse_vf_dev_caps - Parse ICE_AQC_CAPS_VF device caps
2475 u32 number = le32_to_cpu(cap->number); in ice_parse_vf_dev_caps()
2477 dev_p->num_vfs_exposed = number; in ice_parse_vf_dev_caps()
2479 dev_p->num_vfs_exposed); in ice_parse_vf_dev_caps()
2483 * ice_parse_vsi_dev_caps - Parse ICE_AQC_CAPS_VSI device caps
2494 u32 number = le32_to_cpu(cap->number); in ice_parse_vsi_dev_caps()
2496 dev_p->num_vsi_allocd_to_host = number; in ice_parse_vsi_dev_caps()
2498 dev_p->num_vsi_allocd_to_host); in ice_parse_vsi_dev_caps()
2502 * ice_parse_1588_dev_caps - Parse ICE_AQC_CAPS_1588 device caps
2513 struct ice_ts_dev_info *info = &dev_p->ts_dev_info; in ice_parse_1588_dev_caps()
2514 u32 logical_id = le32_to_cpu(cap->logical_id); in ice_parse_1588_dev_caps()
2515 u32 phys_id = le32_to_cpu(cap->phys_id); in ice_parse_1588_dev_caps()
2516 u32 number = le32_to_cpu(cap->number); in ice_parse_1588_dev_caps()
2518 info->ena = ((number & ICE_TS_DEV_ENA_M) != 0); in ice_parse_1588_dev_caps()
2519 dev_p->common_cap.ieee_1588 = info->ena; in ice_parse_1588_dev_caps()
2521 info->tmr0_owner = number & ICE_TS_TMR0_OWNR_M; in ice_parse_1588_dev_caps()
2522 info->tmr0_owned = ((number & ICE_TS_TMR0_OWND_M) != 0); in ice_parse_1588_dev_caps()
2523 info->tmr0_ena = ((number & ICE_TS_TMR0_ENA_M) != 0); in ice_parse_1588_dev_caps()
2525 info->tmr1_owner = FIELD_GET(ICE_TS_TMR1_OWNR_M, number); in ice_parse_1588_dev_caps()
2526 info->tmr1_owned = ((number & ICE_TS_TMR1_OWND_M) != 0); in ice_parse_1588_dev_caps()
2527 info->tmr1_ena = ((number & ICE_TS_TMR1_ENA_M) != 0); in ice_parse_1588_dev_caps()
2529 info->ts_ll_read = ((number & ICE_TS_LL_TX_TS_READ_M) != 0); in ice_parse_1588_dev_caps()
2530 info->ts_ll_int_read = ((number & ICE_TS_LL_TX_TS_INT_READ_M) != 0); in ice_parse_1588_dev_caps()
2531 info->ll_phy_tmr_update = ((number & ICE_TS_LL_PHY_TMR_UPDATE_M) != 0); in ice_parse_1588_dev_caps()
2533 info->ena_ports = logical_id; in ice_parse_1588_dev_caps()
2534 info->tmr_own_map = phys_id; in ice_parse_1588_dev_caps()
2537 dev_p->common_cap.ieee_1588); in ice_parse_1588_dev_caps()
2539 info->tmr0_owner); in ice_parse_1588_dev_caps()
2541 info->tmr0_owned); in ice_parse_1588_dev_caps()
2543 info->tmr0_ena); in ice_parse_1588_dev_caps()
2545 info->tmr1_owner); in ice_parse_1588_dev_caps()
2547 info->tmr1_owned); in ice_parse_1588_dev_caps()
2549 info->tmr1_ena); in ice_parse_1588_dev_caps()
2551 info->ts_ll_read); in ice_parse_1588_dev_caps()
2553 info->ts_ll_int_read); in ice_parse_1588_dev_caps()
2555 info->ll_phy_tmr_update); in ice_parse_1588_dev_caps()
2557 info->ena_ports); in ice_parse_1588_dev_caps()
2559 info->tmr_own_map); in ice_parse_1588_dev_caps()
2563 * ice_parse_fdir_dev_caps - Parse ICE_AQC_CAPS_FD device caps
2574 u32 number = le32_to_cpu(cap->number); in ice_parse_fdir_dev_caps()
2576 dev_p->num_flow_director_fltr = number; in ice_parse_fdir_dev_caps()
2578 dev_p->num_flow_director_fltr); in ice_parse_fdir_dev_caps()
2582 * ice_parse_sensor_reading_cap - Parse ICE_AQC_CAPS_SENSOR_READING cap
2594 dev_p->supported_sensors = le32_to_cpu(cap->number); in ice_parse_sensor_reading_cap()
2598 dev_p->supported_sensors); in ice_parse_sensor_reading_cap()
2602 * ice_parse_nac_topo_dev_caps - Parse ICE_AQC_CAPS_NAC_TOPOLOGY cap
2613 dev_p->nac_topo.mode = le32_to_cpu(cap->number); in ice_parse_nac_topo_dev_caps()
2614 dev_p->nac_topo.id = le32_to_cpu(cap->phys_id) & ICE_NAC_TOPO_ID_M; in ice_parse_nac_topo_dev_caps()
2618 (dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M) ? in ice_parse_nac_topo_dev_caps()
2619 "primary" : "secondary", dev_p->nac_topo.id); in ice_parse_nac_topo_dev_caps()
2622 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_PRIMARY_M)); in ice_parse_nac_topo_dev_caps()
2624 !!(dev_p->nac_topo.mode & ICE_NAC_TOPO_DUAL_M)); in ice_parse_nac_topo_dev_caps()
2626 dev_p->nac_topo.id); in ice_parse_nac_topo_dev_caps()
2630 * ice_parse_dev_caps - Parse device capabilities
2658 found = ice_parse_common_caps(hw, &dev_p->common_cap, in ice_parse_dev_caps()
2692 ice_recalc_port_limited_caps(hw, &dev_p->common_cap); in ice_parse_dev_caps()
2732 * ice_is_cgu_in_netlist - check for CGU presence
2738 * * true - cgu is present
2739 * * false - cgu is not present
2747 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_ZL30632_80032; in ice_is_cgu_in_netlist()
2754 hw->cgu_part_number = ICE_AQC_GET_LINK_TOPO_NODE_NR_SI5383_5384; in ice_is_cgu_in_netlist()
2778 * ice_aq_list_caps - query function/device capabilities
2808 return -EINVAL; in ice_aq_list_caps()
2814 *cap_count = le32_to_cpu(cmd->count); in ice_aq_list_caps()
2820 * ice_discover_dev_caps - Read and extract device capabilities
2836 return -ENOMEM; in ice_discover_dev_caps()
2854 * ice_discover_func_caps - Read and extract function capabilities
2870 return -ENOMEM; in ice_discover_func_caps()
2888 * ice_set_safe_mode_caps - Override dev/func capabilities when in safe mode
2893 struct ice_hw_func_caps *func_caps = &hw->func_caps; in ice_set_safe_mode_caps()
2894 struct ice_hw_dev_caps *dev_caps = &hw->dev_caps; in ice_set_safe_mode_caps()
2899 cached_caps = func_caps->common_cap; in ice_set_safe_mode_caps()
2905 func_caps->common_cap.name = cached_caps.name in ice_set_safe_mode_caps()
2919 func_caps->common_cap.num_rxq = 1; in ice_set_safe_mode_caps()
2920 func_caps->common_cap.num_txq = 1; in ice_set_safe_mode_caps()
2923 func_caps->common_cap.num_msix_vectors = 2; in ice_set_safe_mode_caps()
2924 func_caps->guar_num_vsi = 1; in ice_set_safe_mode_caps()
2927 cached_caps = dev_caps->common_cap; in ice_set_safe_mode_caps()
2928 num_funcs = dev_caps->num_funcs; in ice_set_safe_mode_caps()
2934 dev_caps->common_cap.name = cached_caps.name in ice_set_safe_mode_caps()
2946 dev_caps->num_funcs = num_funcs; in ice_set_safe_mode_caps()
2949 dev_caps->common_cap.num_rxq = num_funcs; in ice_set_safe_mode_caps()
2950 dev_caps->common_cap.num_txq = num_funcs; in ice_set_safe_mode_caps()
2953 dev_caps->common_cap.num_msix_vectors = 2 * num_funcs; in ice_set_safe_mode_caps()
2957 * ice_get_caps - get info about the HW
2964 status = ice_discover_dev_caps(hw, &hw->dev_caps); in ice_get_caps()
2968 return ice_discover_func_caps(hw, &hw->func_caps); in ice_get_caps()
2972 * ice_aq_manage_mac_write - manage MAC address write command
2990 cmd->flags = flags; in ice_aq_manage_mac_write()
2991 ether_addr_copy(cmd->mac_addr, mac_addr); in ice_aq_manage_mac_write()
3013 * ice_clear_pxe_mode - clear pxe operations mode
3017 * like descriptor fetch/write-back mode.
3021 if (ice_check_sq_alive(hw, &hw->adminq)) in ice_clear_pxe_mode()
3026 * ice_aq_set_port_params - set physical port parameters.
3039 struct ice_hw *hw = pi->hw; in ice_aq_set_port_params()
3048 cmd->cmd_flags = cpu_to_le16(cmd_flags); in ice_aq_set_port_params()
3050 cmd->local_fwd_mode = pi->local_fwd_mode | in ice_aq_set_port_params()
3065 switch (hw->device_id) { in ice_is_100m_speed_supported()
3077 * ice_get_link_speed_based_on_phy_type - returns link speed
3228 * [ice_aqc_get_link_status->link_speed]. Caller can pass in
3284 return -EINVAL; in ice_aq_set_phy_cfg()
3286 /* Ensure that only valid bits of cfg->caps can be turned on. */ in ice_aq_set_phy_cfg()
3287 if (cfg->caps & ~ICE_AQ_PHY_ENA_VALID_MASK) { in ice_aq_set_phy_cfg()
3288 ice_debug(hw, ICE_DBG_PHY, "Invalid bit is set in ice_aqc_set_phy_cfg_data->caps : 0x%x\n", in ice_aq_set_phy_cfg()
3289 cfg->caps); in ice_aq_set_phy_cfg()
3291 cfg->caps &= ICE_AQ_PHY_ENA_VALID_MASK; in ice_aq_set_phy_cfg()
3295 desc.params.set_phy.lport_num = pi->lport; in ice_aq_set_phy_cfg()
3300 (unsigned long long)le64_to_cpu(cfg->phy_type_low)); in ice_aq_set_phy_cfg()
3302 (unsigned long long)le64_to_cpu(cfg->phy_type_high)); in ice_aq_set_phy_cfg()
3303 ice_debug(hw, ICE_DBG_LINK, " caps = 0x%x\n", cfg->caps); in ice_aq_set_phy_cfg()
3305 cfg->low_power_ctrl_an); in ice_aq_set_phy_cfg()
3306 ice_debug(hw, ICE_DBG_LINK, " eee_cap = 0x%x\n", cfg->eee_cap); in ice_aq_set_phy_cfg()
3307 ice_debug(hw, ICE_DBG_LINK, " eeer_value = 0x%x\n", cfg->eeer_value); in ice_aq_set_phy_cfg()
3309 cfg->link_fec_opt); in ice_aq_set_phy_cfg()
3312 if (hw->adminq.sq_last_status == ICE_AQ_RC_EMODE) in ice_aq_set_phy_cfg()
3316 pi->phy.curr_user_phy_cfg = *cfg; in ice_aq_set_phy_cfg()
3322 * ice_update_link_info - update status of the HW network link
3331 return -EINVAL; in ice_update_link_info()
3333 li = &pi->phy.link_info; in ice_update_link_info()
3339 if (li->link_info & ICE_AQ_MEDIA_AVAILABLE) { in ice_update_link_info()
3344 return -ENOMEM; in ice_update_link_info()
3354 * ice_aq_get_phy_equalization - function to read serdes equaliser
3360 * @output: pointer to the caller-supplied buffer to return serdes equaliser
3362 * Return: non-zero status on error and 0 on success.
3381 cmd->activity_id = cpu_to_le16(ICE_AQC_ACT_ID_DNL); in ice_aq_get_phy_equalization()
3405 * ice_aq_get_fec_stats - reads fec stats from phy
3408 * @pcs_port: represents the pcs port number part of above pcs quad
3410 * @output: pointer to the caller-supplied buffer to return requested fec stats
3412 * Return: non-zero status on error and 0 on success.
3423 return -EINVAL; in ice_aq_get_fec_stats()
3432 return -EINVAL; in ice_aq_get_fec_stats()
3465 pi->phy.curr_user_fc_req = cache_data.data.curr_user_fc_req; in ice_cache_phy_user_req()
3468 pi->phy.curr_user_speed_req = in ice_cache_phy_user_req()
3472 pi->phy.curr_user_fec_req = cache_data.data.curr_user_fec_req; in ice_cache_phy_user_req()
3527 * ice_cfg_phy_fc - Configure PHY FC data based on FC mode
3540 return -EINVAL; in ice_cfg_phy_fc()
3558 cfg->caps &= ~(ICE_AQC_PHY_EN_TX_LINK_PAUSE | in ice_cfg_phy_fc()
3562 cfg->caps |= pause_mask; in ice_cfg_phy_fc()
3588 return -EINVAL; in ice_set_fc()
3591 hw = pi->hw; in ice_set_fc()
3595 return -ENOMEM; in ice_set_fc()
3608 status = ice_cfg_phy_fc(pi, &cfg, pi->fc.req_mode); in ice_set_fc()
3613 if (cfg.caps != pcaps->caps) { in ice_set_fc()
3672 if (phy_caps->phy_type_low != phy_cfg->phy_type_low || in ice_phy_caps_equals_cfg()
3673 phy_caps->phy_type_high != phy_cfg->phy_type_high || in ice_phy_caps_equals_cfg()
3674 ((phy_caps->caps & caps_mask) != (phy_cfg->caps & cfg_mask)) || in ice_phy_caps_equals_cfg()
3675 phy_caps->low_power_ctrl_an != phy_cfg->low_power_ctrl_an || in ice_phy_caps_equals_cfg()
3676 phy_caps->eee_cap != phy_cfg->eee_cap || in ice_phy_caps_equals_cfg()
3677 phy_caps->eeer_value != phy_cfg->eeer_value || in ice_phy_caps_equals_cfg()
3678 phy_caps->link_fec_options != phy_cfg->link_fec_opt) in ice_phy_caps_equals_cfg()
3685 * ice_copy_phy_caps_to_cfg - Copy PHY ability data to configuration data
3702 cfg->phy_type_low = caps->phy_type_low; in ice_copy_phy_caps_to_cfg()
3703 cfg->phy_type_high = caps->phy_type_high; in ice_copy_phy_caps_to_cfg()
3704 cfg->caps = caps->caps; in ice_copy_phy_caps_to_cfg()
3705 cfg->low_power_ctrl_an = caps->low_power_ctrl_an; in ice_copy_phy_caps_to_cfg()
3706 cfg->eee_cap = caps->eee_cap; in ice_copy_phy_caps_to_cfg()
3707 cfg->eeer_value = caps->eeer_value; in ice_copy_phy_caps_to_cfg()
3708 cfg->link_fec_opt = caps->link_fec_options; in ice_copy_phy_caps_to_cfg()
3709 cfg->module_compliance_enforcement = in ice_copy_phy_caps_to_cfg()
3710 caps->module_compliance_enforcement; in ice_copy_phy_caps_to_cfg()
3714 * ice_cfg_phy_fec - Configure PHY FEC data based on FEC mode
3728 return -EINVAL; in ice_cfg_phy_fec()
3730 hw = pi->hw; in ice_cfg_phy_fec()
3734 return -ENOMEM; in ice_cfg_phy_fec()
3743 cfg->caps |= pcaps->caps & ICE_AQC_PHY_EN_AUTO_FEC; in ice_cfg_phy_fec()
3744 cfg->link_fec_opt = pcaps->link_fec_options; in ice_cfg_phy_fec()
3748 /* Clear RS bits, and AND BASE-R ability in ice_cfg_phy_fec()
3751 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_EN | in ice_cfg_phy_fec()
3753 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_10G_KR_40G_KR4_REQ | in ice_cfg_phy_fec()
3757 /* Clear BASE-R bits, and AND RS ability in ice_cfg_phy_fec()
3760 cfg->link_fec_opt &= ICE_AQC_PHY_FEC_25G_RS_CLAUSE91_EN; in ice_cfg_phy_fec()
3761 cfg->link_fec_opt |= ICE_AQC_PHY_FEC_25G_RS_528_REQ | in ice_cfg_phy_fec()
3766 cfg->link_fec_opt &= ~ICE_AQC_PHY_FEC_MASK; in ice_cfg_phy_fec()
3770 cfg->caps &= ICE_AQC_PHY_CAPS_MASK; in ice_cfg_phy_fec()
3771 cfg->link_fec_opt |= pcaps->link_fec_options; in ice_cfg_phy_fec()
3774 status = -EINVAL; in ice_cfg_phy_fec()
3788 cfg->link_fec_opt = tlv.fec_options; in ice_cfg_phy_fec()
3796 * ice_get_link_status - get status of the HW network link
3810 return -EINVAL; in ice_get_link_status()
3812 phy_info = &pi->phy; in ice_get_link_status()
3814 if (phy_info->get_link_info) { in ice_get_link_status()
3818 ice_debug(pi->hw, ICE_DBG_LINK, "get link status error, status = %d\n", in ice_get_link_status()
3822 *link_up = phy_info->link_info.link_info & ICE_AQ_LINK_UP; in ice_get_link_status()
3833 * Sets up the link and restarts the Auto-Negotiation over the link.
3846 cmd->cmd_flags = ICE_AQC_RESTART_AN_LINK_RESTART; in ice_aq_set_link_restart_an()
3847 cmd->lport_num = pi->lport; in ice_aq_set_link_restart_an()
3849 cmd->cmd_flags |= ICE_AQC_RESTART_AN_LINK_ENABLE; in ice_aq_set_link_restart_an()
3851 cmd->cmd_flags &= ~ICE_AQC_RESTART_AN_LINK_ENABLE; in ice_aq_set_link_restart_an()
3853 return ice_aq_send_cmd(pi->hw, &desc, NULL, 0, cd); in ice_aq_set_link_restart_an()
3876 cmd->lport_num = port_num; in ice_aq_set_event_mask()
3878 cmd->event_mask = cpu_to_le16(mask); in ice_aq_set_event_mask()
3900 cmd->lb_mode = ICE_AQ_MAC_LB_EN; in ice_aq_set_mac_loopback()
3908 * @is_orig_mode: is this LED set to original mode (by the net-list)
3918 struct ice_hw *hw = pi->hw; in ice_aq_set_port_id_led()
3926 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_ORIG; in ice_aq_set_port_id_led()
3928 cmd->ident_mode = ICE_AQC_PORT_IDENT_LED_BLINK; in ice_aq_set_port_id_led()
3937 * @option_count: input - size of the buffer in port options structures,
3938 * output - number of returned port options
3963 return -EINVAL; in ice_aq_get_port_options()
3969 cmd->lport_num = lport; in ice_aq_get_port_options()
3970 cmd->lport_num_valid = lport_valid; in ice_aq_get_port_options()
3979 cmd->port_options_count); in ice_aq_get_port_options()
3982 cmd->port_options); in ice_aq_get_port_options()
3985 cmd->port_options); in ice_aq_get_port_options()
3986 if (*active_option_idx > (*option_count - 1)) in ice_aq_get_port_options()
3987 return -EIO; in ice_aq_get_port_options()
3993 cmd->pending_port_option_status); in ice_aq_get_port_options()
3996 cmd->pending_port_option_status); in ice_aq_get_port_options()
3997 if (*pending_option_idx > (*option_count - 1)) in ice_aq_get_port_options()
3998 return -EIO; in ice_aq_get_port_options()
4034 return -EINVAL; in ice_aq_set_port_option()
4040 cmd->lport_num = lport; in ice_aq_set_port_option()
4042 cmd->lport_num_valid = lport_valid; in ice_aq_set_port_option()
4043 cmd->selected_port_option = new_option; in ice_aq_set_port_option()
4049 * ice_get_phy_lane_number - Get PHY lane number for current adapter
4063 return -ENOMEM; in ice_get_phy_lane_number()
4084 if (hw->pf_id == lport) { in ice_get_phy_lane_number()
4093 err = -ENXIO; in ice_get_phy_lane_number()
4108 * @length: 1-16 for read, 1 for write.
4125 return -EINVAL; in ice_aq_sff_eeprom()
4130 cmd->lport_num = (u8)(lport & 0xff); in ice_aq_sff_eeprom()
4131 cmd->lport_num_valid = (u8)((lport >> 8) & 0x01); in ice_aq_sff_eeprom()
4136 cmd->i2c_bus_addr = cpu_to_le16(i2c_bus_addr); in ice_aq_sff_eeprom()
4137 cmd->i2c_mem_addr = cpu_to_le16(mem_addr & 0xff); in ice_aq_sff_eeprom()
4138 cmd->eeprom_page = le16_encode_bits(page, ICE_AQC_SFF_EEPROM_PAGE_M); in ice_aq_sff_eeprom()
4184 u16 opcode, vsi_id, vsi_handle = params->vsi_handle, glob_lut_idx = 0; in __ice_aq_get_set_rss_lut()
4185 enum ice_lut_type lut_type = params->lut_type; in __ice_aq_get_set_rss_lut()
4190 u8 *lut = params->lut; in __ice_aq_get_set_rss_lut()
4194 return -EINVAL; in __ice_aq_get_set_rss_lut()
4197 if (lut_size > params->lut_size) in __ice_aq_get_set_rss_lut()
4198 return -EINVAL; in __ice_aq_get_set_rss_lut()
4199 else if (set && lut_size != params->lut_size) in __ice_aq_get_set_rss_lut()
4200 return -EINVAL; in __ice_aq_get_set_rss_lut()
4209 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); in __ice_aq_get_set_rss_lut()
4213 params->global_lut_id); in __ice_aq_get_set_rss_lut()
4216 desc_params->flags = cpu_to_le16(flags); in __ice_aq_get_set_rss_lut()
4272 desc_params->vsi_id = cpu_to_le16(vsi_id | ICE_AQC_RSS_VSI_VALID); in __ice_aq_get_set_rss_key()
4290 return -EINVAL; in ice_aq_get_rss_key()
4309 return -EINVAL; in ice_aq_set_rss_key()
4351 return -EINVAL; in ice_aq_add_lan_txq()
4354 return -EINVAL; in ice_aq_add_lan_txq()
4357 sum_size += struct_size(list, txqs, list->num_txqs); in ice_aq_add_lan_txq()
4358 list = (struct ice_aqc_add_tx_qgrp *)(list->txqs + in ice_aq_add_lan_txq()
4359 list->num_txqs); in ice_aq_add_lan_txq()
4363 return -EINVAL; in ice_aq_add_lan_txq()
4367 cmd->num_qgrps = num_qgrps; in ice_aq_add_lan_txq()
4402 return -EINVAL; in ice_aq_dis_lan_txq()
4405 return -EINVAL; in ice_aq_dis_lan_txq()
4407 cmd->num_entries = num_qgrps; in ice_aq_dis_lan_txq()
4413 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VM_RESET; in ice_aq_dis_lan_txq()
4417 cmd->cmd_type = ICE_AQC_Q_DIS_CMD_VF_RESET; in ice_aq_dis_lan_txq()
4419 vmvf_and_timeout |= (vmvf_num + hw->func_caps.vf_base_id) & in ice_aq_dis_lan_txq()
4427 cmd->vmvf_and_timeout = cpu_to_le16(vmvf_and_timeout); in ice_aq_dis_lan_txq()
4430 cmd->cmd_type |= ICE_AQC_Q_DIS_CMD_FLUSH_PIPE; in ice_aq_dis_lan_txq()
4441 u16 item_size = struct_size(item, q_id, item->num_qs); in ice_aq_dis_lan_txq()
4444 if ((item->num_qs % 2) == 0) in ice_aq_dis_lan_txq()
4453 return -EINVAL; in ice_aq_dis_lan_txq()
4460 vmvf_num, hw->adminq.sq_last_status); in ice_aq_dis_lan_txq()
4464 hw->adminq.sq_last_status); in ice_aq_dis_lan_txq()
4498 return -EINVAL; in ice_aq_cfg_lan_txq()
4500 cmd->cmd_type = ICE_AQC_Q_CFG_TC_CHNG; in ice_aq_cfg_lan_txq()
4501 cmd->num_qs = num_qs; in ice_aq_cfg_lan_txq()
4502 cmd->port_num_chng = (oldport & ICE_AQC_Q_CFG_SRC_PRT_M); in ice_aq_cfg_lan_txq()
4503 cmd->port_num_chng |= FIELD_PREP(ICE_AQC_Q_CFG_DST_PRT_M, newport); in ice_aq_cfg_lan_txq()
4504 cmd->time_out = FIELD_PREP(ICE_AQC_Q_CFG_TIMEOUT_M, 5); in ice_aq_cfg_lan_txq()
4505 cmd->blocked_cgds = 0; in ice_aq_cfg_lan_txq()
4510 hw->adminq.sq_last_status); in ice_aq_cfg_lan_txq()
4539 return -EINVAL; in ice_aq_add_rdma_qsets()
4542 u16 num_qsets = le16_to_cpu(list->num_qsets); in ice_aq_add_rdma_qsets()
4545 list = (struct ice_aqc_add_rdma_qset_data *)(list->rdma_qsets + in ice_aq_add_rdma_qsets()
4550 return -EINVAL; in ice_aq_add_rdma_qsets()
4554 cmd->num_qset_grps = num_qset_grps; in ice_aq_add_rdma_qsets()
4562 * ice_get_lan_q_ctx - get the LAN queue context for the given VSI and TC
4577 if (q_handle >= vsi->num_lan_q_entries[tc]) in ice_get_lan_q_ctx()
4579 if (!vsi->lan_q_ctx[tc]) in ice_get_lan_q_ctx()
4581 q_ctx = vsi->lan_q_ctx[tc]; in ice_get_lan_q_ctx()
4609 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) in ice_ena_vsi_txq()
4610 return -EIO; in ice_ena_vsi_txq()
4612 if (num_qgrps > 1 || buf->num_txqs > 1) in ice_ena_vsi_txq()
4613 return -ENOSPC; in ice_ena_vsi_txq()
4615 hw = pi->hw; in ice_ena_vsi_txq()
4618 return -EINVAL; in ice_ena_vsi_txq()
4620 mutex_lock(&pi->sched_lock); in ice_ena_vsi_txq()
4626 status = -EINVAL; in ice_ena_vsi_txq()
4634 status = -EINVAL; in ice_ena_vsi_txq()
4638 buf->parent_teid = parent->info.node_teid; in ice_ena_vsi_txq()
4639 node.parent_teid = parent->info.node_teid; in ice_ena_vsi_txq()
4642 * - Scheduling mode is Bytes Per Second (BPS), indicated by Bit 0. in ice_ena_vsi_txq()
4643 * - 0 priority among siblings, indicated by Bit 1-3. in ice_ena_vsi_txq()
4644 * - WFQ, indicated by Bit 4. in ice_ena_vsi_txq()
4645 * - 0 Adjustment value is used in PSM credit update flow, indicated by in ice_ena_vsi_txq()
4646 * Bit 5-6. in ice_ena_vsi_txq()
4647 * - Bit 7 is reserved. in ice_ena_vsi_txq()
4651 buf->txqs[0].info.valid_sections = in ice_ena_vsi_txq()
4654 buf->txqs[0].info.generic = 0; in ice_ena_vsi_txq()
4655 buf->txqs[0].info.cir_bw.bw_profile_idx = in ice_ena_vsi_txq()
4657 buf->txqs[0].info.cir_bw.bw_alloc = in ice_ena_vsi_txq()
4659 buf->txqs[0].info.eir_bw.bw_profile_idx = in ice_ena_vsi_txq()
4661 buf->txqs[0].info.eir_bw.bw_alloc = in ice_ena_vsi_txq()
4668 le16_to_cpu(buf->txqs[0].txq_id), in ice_ena_vsi_txq()
4669 hw->adminq.sq_last_status); in ice_ena_vsi_txq()
4673 node.node_teid = buf->txqs[0].q_teid; in ice_ena_vsi_txq()
4675 q_ctx->q_handle = q_handle; in ice_ena_vsi_txq()
4676 q_ctx->q_teid = le32_to_cpu(node.node_teid); in ice_ena_vsi_txq()
4679 status = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, &node, NULL); in ice_ena_vsi_txq()
4684 mutex_unlock(&pi->sched_lock); in ice_ena_vsi_txq()
4712 int status = -ENOENT; in ice_dis_vsi_txq()
4715 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) in ice_dis_vsi_txq()
4716 return -EIO; in ice_dis_vsi_txq()
4718 hw = pi->hw; in ice_dis_vsi_txq()
4728 return -EIO; in ice_dis_vsi_txq()
4731 mutex_lock(&pi->sched_lock); in ice_dis_vsi_txq()
4736 node = ice_sched_find_node_by_teid(pi->root, q_teids[i]); in ice_dis_vsi_txq()
4745 if (q_ctx->q_handle != q_handles[i]) { in ice_dis_vsi_txq()
4747 q_ctx->q_handle, q_handles[i]); in ice_dis_vsi_txq()
4750 qg_list->parent_teid = node->info.parent_teid; in ice_dis_vsi_txq()
4751 qg_list->num_qs = 1; in ice_dis_vsi_txq()
4752 qg_list->q_id[0] = cpu_to_le16(q_ids[i]); in ice_dis_vsi_txq()
4759 q_ctx->q_handle = ICE_INVAL_Q_HANDLE; in ice_dis_vsi_txq()
4760 q_ctx->q_teid = ICE_INVAL_TEID; in ice_dis_vsi_txq()
4762 mutex_unlock(&pi->sched_lock); in ice_dis_vsi_txq()
4767 * ice_cfg_vsi_qs - configure the new/existing VSI queues
4783 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) in ice_cfg_vsi_qs()
4784 return -EIO; in ice_cfg_vsi_qs()
4786 if (!ice_is_vsi_valid(pi->hw, vsi_handle)) in ice_cfg_vsi_qs()
4787 return -EINVAL; in ice_cfg_vsi_qs()
4789 mutex_lock(&pi->sched_lock); in ice_cfg_vsi_qs()
4802 mutex_unlock(&pi->sched_lock); in ice_cfg_vsi_qs()
4807 * ice_cfg_vsi_lan - configure VSI LAN queues
4824 * ice_cfg_vsi_rdma - configure the VSI RDMA queues
4862 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) in ice_ena_vsi_rdma_qset()
4863 return -EIO; in ice_ena_vsi_rdma_qset()
4864 hw = pi->hw; in ice_ena_vsi_rdma_qset()
4867 return -EINVAL; in ice_ena_vsi_rdma_qset()
4872 return -ENOMEM; in ice_ena_vsi_rdma_qset()
4873 mutex_lock(&pi->sched_lock); in ice_ena_vsi_rdma_qset()
4878 ret = -EINVAL; in ice_ena_vsi_rdma_qset()
4881 buf->parent_teid = parent->info.node_teid; in ice_ena_vsi_rdma_qset()
4882 node.parent_teid = parent->info.node_teid; in ice_ena_vsi_rdma_qset()
4884 buf->num_qsets = cpu_to_le16(num_qsets); in ice_ena_vsi_rdma_qset()
4886 buf->rdma_qsets[i].tx_qset_id = cpu_to_le16(rdma_qset[i]); in ice_ena_vsi_rdma_qset()
4887 buf->rdma_qsets[i].info.valid_sections = in ice_ena_vsi_rdma_qset()
4890 buf->rdma_qsets[i].info.generic = 0; in ice_ena_vsi_rdma_qset()
4891 buf->rdma_qsets[i].info.cir_bw.bw_profile_idx = in ice_ena_vsi_rdma_qset()
4893 buf->rdma_qsets[i].info.cir_bw.bw_alloc = in ice_ena_vsi_rdma_qset()
4895 buf->rdma_qsets[i].info.eir_bw.bw_profile_idx = in ice_ena_vsi_rdma_qset()
4897 buf->rdma_qsets[i].info.eir_bw.bw_alloc = in ice_ena_vsi_rdma_qset()
4907 node.node_teid = buf->rdma_qsets[i].qset_teid; in ice_ena_vsi_rdma_qset()
4908 ret = ice_sched_add_node(pi, hw->num_tx_sched_layers - 1, in ice_ena_vsi_rdma_qset()
4915 mutex_unlock(&pi->sched_lock); in ice_ena_vsi_rdma_qset()
4921 * ice_dis_vsi_rdma_qset - free RDMA resources
4937 if (!pi || pi->port_state != ICE_SCHED_PORT_STATE_READY) in ice_dis_vsi_rdma_qset()
4938 return -EIO; in ice_dis_vsi_rdma_qset()
4940 hw = pi->hw; in ice_dis_vsi_rdma_qset()
4942 mutex_lock(&pi->sched_lock); in ice_dis_vsi_rdma_qset()
4947 node = ice_sched_find_node_by_teid(pi->root, qset_teid[i]); in ice_dis_vsi_rdma_qset()
4951 qg_list->parent_teid = node->info.parent_teid; in ice_dis_vsi_rdma_qset()
4952 qg_list->num_qs = 1; in ice_dis_vsi_rdma_qset()
4953 qg_list->q_id[0] = in ice_dis_vsi_rdma_qset()
4965 mutex_unlock(&pi->sched_lock); in ice_dis_vsi_rdma_qset()
4970 * ice_aq_get_cgu_abilities - get cgu abilities
4988 * ice_aq_set_input_pin_cfg - set input pin config
5008 cmd->input_idx = input_idx; in ice_aq_set_input_pin_cfg()
5009 cmd->flags1 = flags1; in ice_aq_set_input_pin_cfg()
5010 cmd->flags2 = flags2; in ice_aq_set_input_pin_cfg()
5011 cmd->freq = cpu_to_le32(freq); in ice_aq_set_input_pin_cfg()
5012 cmd->phase_delay = cpu_to_le32(phase_delay); in ice_aq_set_input_pin_cfg()
5018 * ice_aq_get_input_pin_cfg - get input pin config
5041 cmd->input_idx = input_idx; in ice_aq_get_input_pin_cfg()
5046 *status = cmd->status; in ice_aq_get_input_pin_cfg()
5048 *type = cmd->type; in ice_aq_get_input_pin_cfg()
5050 *flags1 = cmd->flags1; in ice_aq_get_input_pin_cfg()
5052 *flags2 = cmd->flags2; in ice_aq_get_input_pin_cfg()
5054 *freq = le32_to_cpu(cmd->freq); in ice_aq_get_input_pin_cfg()
5056 *phase_delay = le32_to_cpu(cmd->phase_delay); in ice_aq_get_input_pin_cfg()
5063 * ice_aq_set_output_pin_cfg - set output pin config
5083 cmd->output_idx = output_idx; in ice_aq_set_output_pin_cfg()
5084 cmd->flags = flags; in ice_aq_set_output_pin_cfg()
5085 cmd->src_sel = src_sel; in ice_aq_set_output_pin_cfg()
5086 cmd->freq = cpu_to_le32(freq); in ice_aq_set_output_pin_cfg()
5087 cmd->phase_delay = cpu_to_le32(phase_delay); in ice_aq_set_output_pin_cfg()
5093 * ice_aq_get_output_pin_cfg - get output pin config
5114 cmd->output_idx = output_idx; in ice_aq_get_output_pin_cfg()
5119 *flags = cmd->flags; in ice_aq_get_output_pin_cfg()
5121 *src_sel = cmd->src_sel; in ice_aq_get_output_pin_cfg()
5123 *freq = le32_to_cpu(cmd->freq); in ice_aq_get_output_pin_cfg()
5125 *src_freq = le32_to_cpu(cmd->src_freq); in ice_aq_get_output_pin_cfg()
5132 * ice_aq_get_cgu_dpll_status - get dpll status
5155 cmd->dpll_num = dpll_num; in ice_aq_get_cgu_dpll_status()
5159 *ref_state = cmd->ref_state; in ice_aq_get_cgu_dpll_status()
5160 *dpll_state = cmd->dpll_state; in ice_aq_get_cgu_dpll_status()
5161 *config = cmd->config; in ice_aq_get_cgu_dpll_status()
5162 *phase_offset = le32_to_cpu(cmd->phase_offset_h); in ice_aq_get_cgu_dpll_status()
5164 *phase_offset += le32_to_cpu(cmd->phase_offset_l); in ice_aq_get_cgu_dpll_status()
5166 *eec_mode = cmd->eec_mode; in ice_aq_get_cgu_dpll_status()
5173 * ice_aq_set_cgu_dpll_config - set dpll config
5192 cmd->dpll_num = dpll_num; in ice_aq_set_cgu_dpll_config()
5193 cmd->ref_state = ref_state; in ice_aq_set_cgu_dpll_config()
5194 cmd->config = config; in ice_aq_set_cgu_dpll_config()
5195 cmd->eec_mode = eec_mode; in ice_aq_set_cgu_dpll_config()
5201 * ice_aq_set_cgu_ref_prio - set input reference priority
5219 cmd->dpll_num = dpll_num; in ice_aq_set_cgu_ref_prio()
5220 cmd->ref_idx = ref_idx; in ice_aq_set_cgu_ref_prio()
5221 cmd->ref_priority = ref_priority; in ice_aq_set_cgu_ref_prio()
5227 * ice_aq_get_cgu_ref_prio - get input reference priority
5246 cmd->dpll_num = dpll_num; in ice_aq_get_cgu_ref_prio()
5247 cmd->ref_idx = ref_idx; in ice_aq_get_cgu_ref_prio()
5251 *ref_prio = cmd->ref_priority; in ice_aq_get_cgu_ref_prio()
5257 * ice_aq_get_cgu_info - get cgu info
5279 *cgu_id = le32_to_cpu(cmd->cgu_id); in ice_aq_get_cgu_info()
5280 *cgu_cfg_ver = le32_to_cpu(cmd->cgu_cfg_ver); in ice_aq_get_cgu_info()
5281 *cgu_fw_ver = le32_to_cpu(cmd->cgu_fw_ver); in ice_aq_get_cgu_info()
5288 * ice_aq_set_phy_rec_clk_out - set RCLK phy out
5307 cmd->phy_output = phy_output; in ice_aq_set_phy_rec_clk_out()
5308 cmd->port_num = ICE_AQC_SET_PHY_REC_CLK_OUT_CURR_PORT; in ice_aq_set_phy_rec_clk_out()
5309 cmd->flags = enable & ICE_AQC_SET_PHY_REC_CLK_OUT_OUT_EN; in ice_aq_set_phy_rec_clk_out()
5310 cmd->freq = cpu_to_le32(*freq); in ice_aq_set_phy_rec_clk_out()
5314 *freq = le32_to_cpu(cmd->freq); in ice_aq_set_phy_rec_clk_out()
5320 * ice_aq_get_phy_rec_clk_out - get phy recovered signal info
5340 cmd->phy_output = *phy_output; in ice_aq_get_phy_rec_clk_out()
5344 *phy_output = cmd->phy_output; in ice_aq_get_phy_rec_clk_out()
5346 *port_num = cmd->port_num; in ice_aq_get_phy_rec_clk_out()
5348 *flags = cmd->flags; in ice_aq_get_phy_rec_clk_out()
5350 *node_handle = le16_to_cpu(cmd->node_handle); in ice_aq_get_phy_rec_clk_out()
5374 cmd->sensor = ICE_INTERNAL_TEMP_SENSOR; in ice_aq_get_sensor_reading()
5375 cmd->format = ICE_INTERNAL_TEMP_SENSOR_FORMAT; in ice_aq_get_sensor_reading()
5386 * ice_replay_pre_init - replay pre initialization
5393 struct ice_switch_info *sw = hw->switch_info; in ice_replay_pre_init()
5403 list_replace_init(&sw->recp_list[i].filt_rules, in ice_replay_pre_init()
5404 &sw->recp_list[i].filt_replay_rules); in ice_replay_pre_init()
5411 * ice_replay_vsi - replay VSI configuration
5423 return -EINVAL; in ice_replay_vsi()
5425 /* Replay pre-initialization if there is any */ in ice_replay_vsi()
5443 * ice_replay_post - post replay configuration cleanup
5456 * ice_stat_update40 - read 40 bit stat from the chip and update stat values
5467 u64 new_data = rd64(hw, reg) & (BIT_ULL(40) - 1); in ice_stat_update40()
5483 *cur_stat += new_data - *prev_stat; in ice_stat_update40()
5485 /* to manage the potential roll-over */ in ice_stat_update40()
5486 *cur_stat += (new_data + BIT_ULL(40)) - *prev_stat; in ice_stat_update40()
5493 * ice_stat_update32 - read 32 bit stat from the chip and update stat values
5522 *cur_stat += new_data - *prev_stat; in ice_stat_update32()
5524 /* to manage the potential roll-over */ in ice_stat_update32()
5525 *cur_stat += (new_data + BIT_ULL(32)) - *prev_stat; in ice_stat_update32()
5532 * ice_sched_query_elem - query element information from HW
5548 buf->node_teid = cpu_to_le32(node_teid); in ice_sched_query_elem()
5560 * @bus_addr: 7-bit I2C bus address
5562 * @params: I2C parameters: bit [7] - Repeated start,
5564 * bit [4] - I2C address type,
5565 * bits [3:0] - data size to read (0-16 bytes)
5585 return -EINVAL; in ice_aq_read_i2c()
5589 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); in ice_aq_read_i2c()
5590 cmd->topo_addr = topo_addr; in ice_aq_read_i2c()
5591 cmd->i2c_params = params; in ice_aq_read_i2c()
5592 cmd->i2c_addr = addr; in ice_aq_read_i2c()
5601 *data = resp->i2c_data[i]; in ice_aq_read_i2c()
5613 * @bus_addr: 7-bit I2C bus address
5615 * @params: I2C parameters: bit [4] - I2C address type, bits [3:0] - data size to write (0-7 bytes)
5622 * * 0 - Successful write to the i2c device
5623 * * -EINVAL - Data size greater than 4 bytes
5624 * * -EIO - FW error
5642 return -EINVAL; in ice_aq_write_i2c()
5644 cmd->i2c_bus_addr = cpu_to_le16(bus_addr); in ice_aq_write_i2c()
5645 cmd->topo_addr = topo_addr; in ice_aq_write_i2c()
5646 cmd->i2c_params = params; in ice_aq_write_i2c()
5647 cmd->i2c_addr = addr; in ice_aq_write_i2c()
5649 memcpy(cmd->i2c_data, data, data_size); in ice_aq_write_i2c()
5655 * ice_get_pca9575_handle - find and return the PCA9575 controller
5660 * When found - the value will be cached in the hw structure and following calls
5663 * Return: 0 on success, -ENXIO when there's no PCA9575 present.
5673 if (hw->io_expander_handle) { in ice_get_pca9575_handle()
5674 *pca9575_handle = hw->io_expander_handle; in ice_get_pca9575_handle()
5682 if (hw->device_id == ICE_DEV_ID_E810C_SFP) in ice_get_pca9575_handle()
5684 else if (hw->device_id == ICE_DEV_ID_E810C_QSFP) in ice_get_pca9575_handle()
5687 return -ENXIO; in ice_get_pca9575_handle()
5692 cmd->addr.topo_params.node_type_ctx = in ice_get_pca9575_handle()
5694 cmd->addr.topo_params.index = idx; in ice_get_pca9575_handle()
5698 return -ENXIO; in ice_get_pca9575_handle()
5703 return -ENXIO; in ice_get_pca9575_handle()
5706 hw->io_expander_handle = in ice_get_pca9575_handle()
5708 *pca9575_handle = hw->io_expander_handle; in ice_get_pca9575_handle()
5714 * ice_read_pca9575_reg - read the register from the PCA9575 controller
5763 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); in ice_aq_set_gpio()
5764 cmd->gpio_num = pin_idx; in ice_aq_set_gpio()
5765 cmd->gpio_val = value ? 1 : 0; in ice_aq_set_gpio()
5791 cmd->gpio_ctrl_handle = cpu_to_le16(gpio_ctrl_handle); in ice_aq_get_gpio()
5792 cmd->gpio_num = pin_idx; in ice_aq_get_gpio()
5798 *value = !!cmd->gpio_val; in ice_aq_get_gpio()
5813 if (hw->api_maj_ver == maj) { in ice_is_fw_api_min_ver()
5814 if (hw->api_min_ver > min) in ice_is_fw_api_min_ver()
5816 if (hw->api_min_ver == min && hw->api_patch >= patch) in ice_is_fw_api_min_ver()
5818 } else if (hw->api_maj_ver > maj) { in ice_is_fw_api_min_ver()
5850 struct ice_hw *hw = pi->hw; in ice_get_link_default_override()
5861 tlv_start = tlv + pi->lport * ICE_SR_PFA_LINK_OVERRIDE_WORDS + in ice_get_link_default_override()
5870 ldo->options = FIELD_GET(ICE_LINK_OVERRIDE_OPT_M, buf); in ice_get_link_default_override()
5871 ldo->phy_config = (buf & ICE_LINK_OVERRIDE_PHY_CFG_M) >> in ice_get_link_default_override()
5881 ldo->fec_options = buf & ICE_LINK_OVERRIDE_FEC_OPT_M; in ice_get_link_default_override()
5892 ldo->phy_type_low |= ((u64)buf << (i * 16)); in ice_get_link_default_override()
5905 ldo->phy_type_high |= ((u64)buf << (i * 16)); in ice_get_link_default_override()
5912 * ice_is_phy_caps_an_enabled - check if PHY capabilities autoneg is enabled
5917 if (caps->caps & ICE_AQC_PHY_AN_MODE || in ice_is_phy_caps_an_enabled()
5918 caps->low_power_ctrl_an & (ICE_AQC_PHY_AN_EN_CLAUSE28 | in ice_is_phy_caps_an_enabled()
5927 * ice_is_fw_health_report_supported - checks if firmware supports health events
5941 * ice_aq_set_health_status_cfg - Configure FW health events
5946 * PF. The supported event types are: PF-specific, all PFs, and global.
5959 cmd->event_source = event_source; in ice_aq_set_health_status_cfg()
5965 * ice_aq_set_lldp_mib - Set the LLDP MIB
5968 * @buf: pointer to the caller-supplied buffer to store the MIB block
5984 return -EINVAL; in ice_aq_set_lldp_mib()
5991 cmd->type = mib_type; in ice_aq_set_lldp_mib()
5992 cmd->length = cpu_to_le16(buf_size); in ice_aq_set_lldp_mib()
5998 * ice_fw_supports_lldp_fltr_ctrl - check NVM version supports lldp_fltr_ctrl
6003 if (hw->mac_type != ICE_MAC_E810) in ice_fw_supports_lldp_fltr_ctrl()
6012 * ice_lldp_fltr_add_remove - add or remove a LLDP Rx switch filter
6028 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_ADD; in ice_lldp_fltr_add_remove()
6030 cmd->cmd_flags = ICE_AQC_LLDP_FILTER_ACTION_DELETE; in ice_lldp_fltr_add_remove()
6032 cmd->vsi_num = cpu_to_le16(vsi_num); in ice_lldp_fltr_add_remove()
6038 * ice_lldp_execute_pending_mib - execute LLDP pending MIB request
6069 * by [fls(speed) - 1]
6087 * ice_get_link_speed - get integer speed from table
6088 * @index: array index from fls(aq speed) - 1