Lines Matching full:enum
84 enum {
92 enum {
97 enum {
106 enum {
118 enum dev_master {
124 enum dev_state {
130 enum cc_pause {
136 enum cc_fec {
142 enum {
149 enum cxgb4_netdev_tls_ops {
196 enum {
443 enum pcie_memwin drv_memwin;
464 enum chip_type chip; /* chip code */
572 enum fw_caps {
587 enum cc_pause requested_fc; /* flow control user has requested */
588 enum cc_pause fc; /* actual link flow control */
589 enum cc_pause advertised_fc; /* actual advertised flow control */
591 enum cc_fec requested_fec; /* Forward Error Correction: */
592 enum cc_fec fec; /* requested and actual in use */
605 enum {
611 enum {
622 enum {
629 enum {
635 enum {
659 enum fw_port_type port_type;
703 enum { /* adapter flags */
718 enum {
916 enum cxgb4_uld uld_type;
919 enum sge_eosw_state {
930 enum sge_eosw_state state; /* Current ETHOFLD State */
1065 enum {
1115 enum chip_type chip;
1261 enum {
1265 enum {
1270 enum {
1275 enum {
1279 enum {
1425 enum {
1431 enum {
1438 enum {
1645 enum cpl_tx_tnl_lso_type cxgb_encap_offload_supported(struct sk_buff *skb);
1851 int t4_fwcache(struct adapter *adap, enum fw_params_param_dev_fwcache op);
1868 struct fw_hdr *card_fw, enum dev_state state, int *reset);
1872 enum t4_bar2_qtype { T4_BAR2_QTYPE_EGRESS, T4_BAR2_QTYPE_INGRESS };
1875 enum t4_bar2_qtype qtype,
1930 const char *t4_get_port_type_description(enum fw_port_type port_type);
1962 enum dev_master master, enum dev_state *state);
2066 enum ctxt_type ctype, u32 *data);
2068 enum ctxt_type ctype, u32 *data);