Lines Matching +full:max +full:- +full:by +full:- +full:define
7 * Copyright (c) 2003-2016 Cavium, Inc.
11 * published by the Free Software Foundation.
14 * AS-IS and WITHOUT ANY WARRANTY; without even the implied warranty
23 #define __OCTEON_CONFIG_H__
25 /*--------------------------CONFIG VALUES------------------------*/
35 #define MAX_OCTEON_NICIF 128
36 #define MAX_OCTEON_DEVICES MAX_OCTEON_NICIF
37 #define MAX_OCTEON_LINKS MAX_OCTEON_NICIF
38 #define MAX_OCTEON_MULTICAST_ADDR 32
40 #define MAX_OCTEON_FILL_COUNT 8
43 #define CN6XXX_MAX_INPUT_QUEUES 32
44 #define CN6XXX_MAX_IQ_DESCRIPTORS 2048
45 #define CN6XXX_DB_MIN 1
46 #define CN6XXX_DB_MAX 8
47 #define CN6XXX_DB_TIMEOUT 1
50 #define CN6XXX_MAX_OUTPUT_QUEUES 32
51 #define CN6XXX_MAX_OQ_DESCRIPTORS 2048
52 #define CN6XXX_OQ_BUF_SIZE 1664
53 #define CN6XXX_OQ_PKTSPER_INTR ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
55 #define CN6XXX_OQ_REFIL_THRESHOLD ((CN6XXX_MAX_OQ_DESCRIPTORS < 512) ? \
58 #define CN6XXX_OQ_INTR_PKT 64
59 #define CN6XXX_OQ_INTR_TIME 100
60 #define DEFAULT_NUM_NIC_PORTS_66XX 2
61 #define DEFAULT_NUM_NIC_PORTS_68XX 4
62 #define DEFAULT_NUM_NIC_PORTS_68XX_210NV 2
65 #define CN23XX_MAX_VFS_PER_PF_PASS_1_0 8
66 #define CN23XX_MAX_VFS_PER_PF_PASS_1_1 31
67 #define CN23XX_MAX_VFS_PER_PF 63
68 #define CN23XX_MAX_RINGS_PER_VF 8
70 #define CN23XX_MAX_RINGS_PER_PF_PASS_1_0 12
71 #define CN23XX_MAX_RINGS_PER_PF_PASS_1_1 32
72 #define CN23XX_MAX_RINGS_PER_PF 64
73 #define CN23XX_MAX_RINGS_PER_VF 8
75 #define CN23XX_MAX_INPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
76 #define CN23XX_MAX_IQ_DESCRIPTORS 2048
77 #define CN23XX_DEFAULT_IQ_DESCRIPTORS 512
78 #define CN23XX_MIN_IQ_DESCRIPTORS 128
79 #define CN23XX_DB_MIN 1
80 #define CN23XX_DB_MAX 8
81 #define CN23XX_DB_TIMEOUT 1
83 #define CN23XX_MAX_OUTPUT_QUEUES CN23XX_MAX_RINGS_PER_PF
84 #define CN23XX_MAX_OQ_DESCRIPTORS 2048
85 #define CN23XX_DEFAULT_OQ_DESCRIPTORS 512
86 #define CN23XX_MIN_OQ_DESCRIPTORS 128
87 #define CN23XX_OQ_BUF_SIZE 1664
88 #define CN23XX_OQ_PKTSPER_INTR 128
89 /*#define CAVIUM_ONLY_CN23XX_RX_PERF*/
90 #define CN23XX_OQ_REFIL_THRESHOLD 16
92 #define CN23XX_OQ_INTR_PKT 64
93 #define CN23XX_OQ_INTR_TIME 100
94 #define DEFAULT_NUM_NIC_PORTS_23XX 1
96 #define CN23XX_CFG_IO_QUEUES CN23XX_MAX_RINGS_PER_PF
98 #define CN23XX_MAX_MACS 4
100 #define CN23XX_DEF_IQ_INTR_THRESHOLD 32
101 #define CN23XX_DEF_IQ_INTR_BYTE_THRESHOLD (64 * 1024)
103 #define CN6XXX_CFG_IO_QUEUES 32
104 #define OCTEON_32BYTE_INSTR 32
105 #define OCTEON_64BYTE_INSTR 64
106 #define OCTEON_MAX_BASE_IOQ 4
108 #define OCTEON_DMA_INTR_PKT 64
109 #define OCTEON_DMA_INTR_TIME 1000
111 #define MAX_TXQS_PER_INTF 8
112 #define MAX_RXQS_PER_INTF 8
113 #define DEF_TXQS_PER_INTF 4
114 #define DEF_RXQS_PER_INTF 4
116 #define INVALID_IOQ_NO 0xff
118 #define DEFAULT_POW_GRP 0
121 #define CFG_GET_IQ_CFG(cfg) ((cfg)->iq)
122 #define CFG_GET_IQ_MAX_Q(cfg) ((cfg)->iq.max_iqs)
123 #define CFG_GET_IQ_PENDING_LIST_SIZE(cfg) ((cfg)->iq.pending_list_size)
124 #define CFG_GET_IQ_INSTR_TYPE(cfg) ((cfg)->iq.instr_type)
125 #define CFG_GET_IQ_DB_MIN(cfg) ((cfg)->iq.db_min)
126 #define CFG_GET_IQ_DB_TIMEOUT(cfg) ((cfg)->iq.db_timeout)
128 #define CFG_GET_IQ_INTR_PKT(cfg) ((cfg)->iq.iq_intr_pkt)
129 #define CFG_SET_IQ_INTR_PKT(cfg, val) (cfg)->iq.iq_intr_pkt = val
131 #define CFG_GET_OQ_MAX_Q(cfg) ((cfg)->oq.max_oqs)
132 #define CFG_GET_OQ_PKTS_PER_INTR(cfg) ((cfg)->oq.pkts_per_intr)
133 #define CFG_GET_OQ_REFILL_THRESHOLD(cfg) ((cfg)->oq.refill_threshold)
134 #define CFG_GET_OQ_INTR_PKT(cfg) ((cfg)->oq.oq_intr_pkt)
135 #define CFG_GET_OQ_INTR_TIME(cfg) ((cfg)->oq.oq_intr_time)
136 #define CFG_SET_OQ_INTR_PKT(cfg, val) (cfg)->oq.oq_intr_pkt = val
137 #define CFG_SET_OQ_INTR_TIME(cfg, val) (cfg)->oq.oq_intr_time = val
139 #define CFG_GET_DMA_INTR_PKT(cfg) ((cfg)->dma.dma_intr_pkt)
140 #define CFG_GET_DMA_INTR_TIME(cfg) ((cfg)->dma.dma_intr_time)
141 #define CFG_GET_NUM_NIC_PORTS(cfg) ((cfg)->num_nic_ports)
142 #define CFG_GET_NUM_DEF_TX_DESCS(cfg) ((cfg)->num_def_tx_descs)
143 #define CFG_GET_NUM_DEF_RX_DESCS(cfg) ((cfg)->num_def_rx_descs)
144 #define CFG_GET_DEF_RX_BUF_SIZE(cfg) ((cfg)->def_rx_buf_size)
146 #define CFG_GET_MAX_TXQS_NIC_IF(cfg, idx) \
147 ((cfg)->nic_if_cfg[idx].max_txqs)
148 #define CFG_GET_NUM_TXQS_NIC_IF(cfg, idx) \
149 ((cfg)->nic_if_cfg[idx].num_txqs)
150 #define CFG_GET_MAX_RXQS_NIC_IF(cfg, idx) \
151 ((cfg)->nic_if_cfg[idx].max_rxqs)
152 #define CFG_GET_NUM_RXQS_NIC_IF(cfg, idx) \
153 ((cfg)->nic_if_cfg[idx].num_rxqs)
154 #define CFG_GET_NUM_RX_DESCS_NIC_IF(cfg, idx) \
155 ((cfg)->nic_if_cfg[idx].num_rx_descs)
156 #define CFG_GET_NUM_TX_DESCS_NIC_IF(cfg, idx) \
157 ((cfg)->nic_if_cfg[idx].num_tx_descs)
158 #define CFG_GET_NUM_RX_BUF_SIZE_NIC_IF(cfg, idx) \
159 ((cfg)->nic_if_cfg[idx].rx_buf_size)
160 #define CFG_GET_BASE_QUE_NIC_IF(cfg, idx) \
161 ((cfg)->nic_if_cfg[idx].base_queue)
162 #define CFG_GET_GMXID_NIC_IF(cfg, idx) \
163 ((cfg)->nic_if_cfg[idx].gmx_port_id)
165 #define CFG_GET_CTRL_Q_GRP(cfg) ((cfg)->misc.ctrlq_grp)
166 #define CFG_GET_HOST_LINK_QUERY_INTERVAL(cfg) \
167 ((cfg)->misc.host_link_query_interval)
168 #define CFG_GET_OCT_LINK_QUERY_INTERVAL(cfg) \
169 ((cfg)->misc.oct_link_query_interval)
170 #define CFG_GET_IS_SLI_BP_ON(cfg) ((cfg)->misc.enable_sli_oq_bp)
172 #define CFG_SET_NUM_RX_DESCS_NIC_IF(cfg, idx, value) \
173 ((cfg)->nic_if_cfg[idx].num_rx_descs = value)
174 #define CFG_SET_NUM_TX_DESCS_NIC_IF(cfg, idx, value) \
175 ((cfg)->nic_if_cfg[idx].num_tx_descs = value)
177 /* Max IOQs per OCTEON Link */
178 #define MAX_IOQS_PER_NICIF 64
187 #define LIO_210SV_NAME "210sv"
188 #define LIO_210NV_NAME "210nv"
189 #define LIO_410NV_NAME "410nv"
190 #define LIO_23XX_NAME "23xx"
192 /** Structure to define the configuration attributes for each Input queue.
210 /** Command size - 32 or 64 bytes */
218 /* Max number of IQs available */
221 /* Max number of IQs available */
229 /** Command size - 32 or 64 bytes */
247 /** Structure to define the configuration attributes for each Output queue.
258 * by this field. The driver uses time interval interrupt coalescing
259 * by default. The time is specified in microseconds.
264 * only if it sent as many packets as specified by this field.
270 /** The number of buffers that were consumed during packet processing by
277 /* Max number of OQs available */
281 /* Max number of OQs available */
284 /** The number of buffers that were consumed during packet processing by
292 * only if it sent as many packets as specified by this field.
300 * by this field. The driver uses time interval interrupt coalescing
301 * by default. The time is specified in microseconds.
337 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
343 /* Max Txqs: Half for each of the two ports :max_iq/2 */
346 /* Max Txqs: Half for each of the two ports :max_iq/2 */
352 /* Max Rxqs: Half for each of the two ports :max_oq/2 */
378 /** Structure to define the configuration attributes for meta data.
404 /** Structure to define the configuration for all OCTEON processors. */
434 #define BAR1_INDEX_DYNAMIC_MAP 2
435 #define BAR1_INDEX_STATIC_MAP 15
436 #define OCTEON_BAR1_ENTRY_SIZE (4 * 1024 * 1024)
438 #define MAX_BAR1_IOREMAP_SIZE (16 * OCTEON_BAR1_ENTRY_SIZE)
440 /* Response lists - 1 ordered, 1 unordered-blocking, 1 unordered-nonblocking
444 #define MAX_RESPONSE_LISTS 6
446 /* Opcode hash bits. The opcode is hashed on the lower 6-bits to lookup the
449 #define OPCODE_MASK_BITS 6
451 /* Mask for the 6-bit lookup hash */
452 #define OCTEON_OPCODE_MASK 0x3f
454 /* Size of the dispatch table. The 6-bit hash can index into 2^6 entries */
455 #define DISPATCH_LIST_SIZE BIT(OPCODE_MASK_BITS)
458 #define MAX_OCTEON_INSTR_QUEUES(oct) \
463 #define MAX_OCTEON_OUTPUT_QUEUES(oct) \
467 #define MAX_POSSIBLE_OCTEON_INSTR_QUEUES CN23XX_MAX_INPUT_QUEUES
468 #define MAX_POSSIBLE_OCTEON_OUTPUT_QUEUES CN23XX_MAX_OUTPUT_QUEUES
470 #define MAX_POSSIBLE_VFS 64