Lines Matching +full:queue +full:- +full:sizes
9 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
59 * Copyright (c) 2014-2016 Advanced Micro Devices, Inc.
132 /* DMA register entry bit positions and sizes */
208 /* DMA channel register entry bit positions and sizes */
343 /* MAC register entry bit positions and sizes */
675 /* MMC register entry bit positions and sizes */
788 /* MTL register entry bit positions and sizes */
794 /* MTL queue register offsets
795 * Multiple queues can be active. The first queue has registers
796 * that begin at 0x1100. Each subsequent queue has registers that
797 * are accessed using an offset of 0x80 from the previous queue.
812 /* MTL queue register entry bit positions and sizes */
846 /* MTL queue register value */
875 * that begin at 0x1100. Each subsequent queue has registers that
876 * are accessed using an offset of 0x80 from the previous queue.
885 /* MTL traffic class register entry bit positions and sizes */
904 /* PCS register entry bit positions and sizes */
915 /* SerDes integration register entry bit positions and sizes */
942 /* SerDes RxTx register entry bit positions and sizes */
974 /* MAC Control register entry bit positions and sizes */
1103 /* I2C Control register entry bit positions and sizes */
1145 /* Descriptor/Packet entry bit positions and sizes */
1449 (((_var) >> (_index)) & ((0x1 << (_width)) - 1))
1453 (_var) &= ~(((0x1 << (_width)) - 1) << (_index)); \
1454 (_var) |= (((_val) & ((0x1 << (_width)) - 1)) << (_index)); \
1458 ((le32_to_cpu((_var)) >> (_index)) & ((0x1 << (_width)) - 1))
1462 (_var) &= cpu_to_le32(~(((0x1 << (_width)) - 1) << (_index))); \
1464 ((0x1 << (_width)) - 1)) << (_index))); \
1503 ioread32((_pdata)->xgmac_regs + _reg)
1511 iowrite32((_val), (_pdata)->xgmac_regs + _reg)
1522 /* Macros for reading or writing MTL queue or traffic class registers
1524 * base register value is calculated by the queue or traffic class number
1527 ioread32((_pdata)->xgmac_regs + \
1536 iowrite32((_val), (_pdata)->xgmac_regs + \
1553 ioread32((_channel)->dma_regs + _reg)
1561 iowrite32((_val), (_channel)->dma_regs + _reg)
1586 iowrite32(_val, (_pdata)->xpcs_regs + (_off))
1589 ioread32((_pdata)->xpcs_regs + (_off))
1592 iowrite16(_val, (_pdata)->xpcs_regs + (_off))
1595 ioread16((_pdata)->xpcs_regs + (_off))
1611 ioread16((_pdata)->sir0_regs + _reg)
1619 iowrite16((_val), (_pdata)->sir0_regs + _reg)
1631 ioread16((_pdata)->sir1_regs + _reg)
1639 iowrite16((_val), (_pdata)->sir1_regs + _reg)
1654 ioread16((_pdata)->rxtx_regs + _reg)
1662 iowrite16((_val), (_pdata)->rxtx_regs + _reg)
1687 ioread32((_pdata)->xprop_regs + (_reg))
1695 iowrite32((_val), (_pdata)->xprop_regs + (_reg))
1720 ioread32((_pdata)->xi2c_regs + (_reg))
1728 iowrite32((_val), (_pdata)->xi2c_regs + (_reg))
1746 ((_pdata)->hw_if.read_mmd_regs((_pdata), 0, \
1753 ((_pdata)->hw_if.write_mmd_regs((_pdata), 0, \