amazon/ena/ena_admin_defs.h

1 /* SPDX-License-Identifier: GPL-2.0 OR Linux-OpenIB */
3  * Copyright 2015-2020 Amazon.com, Inc. or its affiliates. All rights reserved.
13  /* customer metrics - in correlation with
41 	/* Additional status is provided in ACQ entry extended_status */
77 	/* descriptors and headers are in device memory (a.k.a Low Latency
97 	/* completion queue entry for each sq descriptor */
99 	/* completion queue entry upon request in sq descriptor */
150 	 * 1 : ctrl_data - control buffer address valid
151 	 * 2 : ctrl_data_indirect - control buffer address
173 	 * 7:5 : sq_direction - 0x1 - Tx; 0x2 - Rx
208 	/* indicates to the driver which AQ entry has been consumed by the
224 	 * 7:5 : sq_direction - 0x1 - Tx, 0x2 - Rx
230 	/* 3:0 : placement_policy - Describing where the SQ
232 	 *    0x1 - descriptors and headers are in OS memory,
233 	 *    0x3 - descriptors and headers in device memory
234 	 *    (a.k.a Low Latency Queue)
235 	 * 6:4 : completion_policy - Describing what policy
236 	 *    to use for generation completion entry (cqe) in
237 	 *    the CQ associated with this SQ: 0x0 - cqe for each
238 	 *    sq descriptor, 0x1 - cqe upon request in sq
239 	 *    descriptor, 0x2 - current queue head pointer is
241 	 *    0x3 - current queue head pointer is updated in OS
247 	/* 0 : is_physically_contiguous - Described if the
263 	 * used for Low Latency queues. Has to be page aligned.
293 	/* low latency queue ring base address as an offset to PCIe MMIO
298 	/* low latency queue headers' memory as an offset to PCIe MMIO
318 	 * 5 : interrupt_mode_enabled - if set, cq operates
319 	 *    in interrupt mode, otherwise - polling
324 	/* 4:0 : cq_entry_size_words - size of CQ entry in
325 	 *    32-bit words, valid values: 4, 8.
370  * buffer pointed by AQ entry
507 	/* 1:0 : select - 0x1 - current value; 0x3 - default
557 	/* header in a separate ring, implies 16B descriptor list entry */
575 /* packet descriptor list entry always starts with one or more descriptors,
577  * beginning of the subsequent entry. Stride refers to how the rest of the
629 	/* if inline header is specified - this is the size of descriptor list
630 	 * entry. If header in a separate ring is specified - this is the size
631 	 * of header ring entry. bitfield of enum ena_admin_llq_ring_entry_size.
632 	 * specify the entry sizes the device supports
636 	/* the entry size the driver selected to use. */
639 	/* valid only if inline header is specified. First entry associated with
642 	 * descriptors precedding the header in the first entry. The field is
662 	/* accelerated low latency queues requirement. driver needs to
755 	 * 1 : duplex - Full Duplex
771 	 * 1 : TX_L4_ipv4_csum_part - The checksum field
774 	 * 3 : TX_L4_ipv6_csum_part - The checksum field
784 	 * 0 : RX_L3_csum_ipv4 - IPv4 checksum
785 	 * 1 : RX_L4_ipv4_csum - TCP/UDP/IPv4 checksum
786 	 * 2 : RX_L4_ipv6_csum - TCP/UDP/IPv6 checksum
787 	 * 3 : RX_hash - Hash calculation
808 	/* 7:0 : funcs - bitmask of ena_admin_hash_functions */
811 	/* 7:0 : selected_func - bitmask of
872 	 * 1 : L3_sort - support swap L3 addresses if DA is
874 	 * 2 : L4_sort - support swap L4 ports if DP smaller
880 	 * 1 : enable_L3_sort - enable swap L3 addresses if
882 	 * 2 : enable_L4_sort - enable swap L4 ports if DP
969 	/* index of the inline entry. 0xFFFFFFFF means invalid */
972 	/* used for updating single entry, ignored when setting the entire
1105 	 * 7:1 : reserved - MBZ