Lines Matching +full:16 +full:- +full:bit
1 /* SPDX-License-Identifier: GPL-2.0-only */
33 #define FE_DMA_GLO_PG_SZ_MASK BIT(3)
36 #define FE_RST_GDM4_MBI_ARB_MASK BIT(3)
37 #define FE_RST_GDM3_MBI_ARB_MASK BIT(2)
38 #define FE_RST_CORE_MASK BIT(0)
43 #define WAN1_EN_MASK BIT(16)
59 #define PCE_DPI_EN_MASK BIT(2)
60 #define PCE_KA_EN_MASK BIT(1)
61 #define PCE_MC_EN_MASK BIT(0)
65 #define PSE_CFG_QUEUE_ID_MASK GENMASK(20, 16)
66 #define PSE_CFG_WR_EN_MASK BIT(8)
67 #define PSE_CFG_OQRSV_SEL_MASK BIT(0)
76 #define PSE_SHARE_USED_LTHD_MASK GENMASK(31, 16)
80 #define PSE_SHARE_USED_MTHD_MASK GENMASK(31, 16)
84 #define GDM2_RDM_ACK_WAIT_PREF_MASK BIT(9)
85 #define GDM2_CHN_VLD_MODE_MASK BIT(5)
88 #define FE_IFC_EN_MASK BIT(0)
94 #define PSE_IQ_RES1_P2_MASK GENMASK(23, 16)
101 #define PATN_FCPU_EN_MASK BIT(7)
102 #define PATN_SWP_EN_MASK BIT(6)
103 #define PATN_DP_EN_MASK BIT(5)
104 #define PATN_SP_EN_MASK BIT(4)
106 #define PATN_EN_MASK BIT(0)
109 #define PATN_DP_MASK GENMASK(31, 16)
113 #define CDM1_VLAN_MASK GENMASK(31, 16)
131 #define GDM_DROP_CRC_ERR BIT(23)
132 #define GDM_IP4_CKSUM BIT(22)
133 #define GDM_TCP_CKSUM BIT(21)
134 #define GDM_UDP_CKSUM BIT(20)
135 #define GDM_STRIP_CRC BIT(16)
142 #define GDM_INGRESS_FC_EN_MASK BIT(1)
143 #define GDM_STAG_EN_MASK BIT(0)
147 #define GDM_LONG_LEN_MASK GENMASK(29, 16)
154 #define LPBK_EN_MASK BIT(0)
160 #define FE_CPORT_PAD BIT(26)
161 #define FE_CPORT_PORT_XFC_MASK BIT(25)
162 #define FE_CPORT_QUEUE_XFC_MASK BIT(24)
165 #define FE_GDM_MIB_RX_CLEAR_MASK BIT(1)
166 #define FE_GDM_MIB_TX_CLEAR_MASK BIT(0)
169 #define FE_STRICT_RFC2819_MODE_MASK BIT(31)
170 #define FE_GDM1_TX_MIB_SPLIT_EN_MASK BIT(17)
171 #define FE_GDM1_RX_MIB_SPLIT_EN_MASK BIT(16)
215 #define PPE_GLO_CFG_BUSY_MASK BIT(31)
216 #define PPE_GLO_CFG_FLOW_DROP_UPDATE_MASK BIT(9)
217 #define PPE_GLO_CFG_PSE_HASH_OFS_MASK BIT(6)
218 #define PPE_GLO_CFG_PPE_BSWAP_MASK BIT(5)
219 #define PPE_GLO_CFG_TTL_DROP_MASK BIT(4)
220 #define PPE_GLO_CFG_IP4_CS_DROP_MASK BIT(3)
221 #define PPE_GLO_CFG_IP4_L4_CS_DROP_MASK BIT(2)
222 #define PPE_GLO_CFG_EN_MASK BIT(0)
225 #define PPE_FLOW_CFG_IP6_HASH_GRE_KEY_MASK BIT(20)
226 #define PPE_FLOW_CFG_IP4_HASH_GRE_KEY_MASK BIT(19)
227 #define PPE_FLOW_CFG_IP4_HASH_FLOW_LABEL_MASK BIT(18)
228 #define PPE_FLOW_CFG_IP4_NAT_FRAG_MASK BIT(17)
229 #define PPE_FLOW_CFG_IP_PROTO_BLACKLIST_MASK BIT(16)
230 #define PPE_FLOW_CFG_IP4_DSLITE_MASK BIT(14)
231 #define PPE_FLOW_CFG_IP4_NAPT_MASK BIT(13)
232 #define PPE_FLOW_CFG_IP4_NAT_MASK BIT(12)
233 #define PPE_FLOW_CFG_IP6_6RD_MASK BIT(10)
234 #define PPE_FLOW_CFG_IP6_5T_ROUTE_MASK BIT(9)
235 #define PPE_FLOW_CFG_IP6_3T_ROUTE_MASK BIT(8)
236 #define PPE_FLOW_CFG_IP4_UDP_FRAG_MASK BIT(7)
237 #define PPE_FLOW_CFG_IP4_TCP_FRAG_MASK BIT(6)
241 #define PPE_IP_PROTO_CHK_IPV6_MASK GENMASK(31, 16)
246 #define PPE_TB_CFG_AGE_TCP_FIN_MASK BIT(11)
247 #define PPE_TB_CFG_AGE_UDP_MASK BIT(10)
248 #define PPE_TB_CFG_AGE_TCP_MASK BIT(9)
249 #define PPE_TB_CFG_AGE_UNBIND_MASK BIT(8)
250 #define PPE_TB_CFG_AGE_NON_L4_MASK BIT(7)
251 #define PPE_TB_CFG_AGE_PREBIND_MASK BIT(6)
253 #define PPE_TB_ENTRY_SIZE_MASK BIT(3)
259 #define PPE_BIND_RATE_L2B_BIND_MASK GENMASK(31, 16)
263 #define PPE_BIND_LIMIT0_HALF_MASK GENMASK(29, 16)
267 #define PPE_BIND_LIMIT1_NON_L4_MASK GENMASK(23, 16)
271 #define PPE_BIND_AGE0_DELTA_NON_L4 GENMASK(30, 16)
275 #define PPE_UNBIND_AGE_MIN_PACKETS_MASK GENMASK(31, 16)
279 #define PPE_BIND_AGE1_DELTA_TCP_FIN GENMASK(30, 16)
291 #define PPE_DRAM_HASH1_EN_MASK BIT(24)
293 #define PPE_DRAM_TABLE_EN_MASK BIT(16)
295 #define PPE_SRAM_HASH1_EN_MASK BIT(8)
297 #define PPE_SRAM_TABLE_EN_MASK BIT(0)
301 #define FP1_EGRESS_MTU_MASK GENMASK(29, 16)
305 #define PPE_SRAM_CTRL_ACK_MASK BIT(31)
306 #define PPE_SRAM_CTRL_DUAL_SUCESS_MASK BIT(30)
308 #define PPE_SRAM_WR_DUAL_DIRECTION_MASK BIT(2)
309 #define PPE_SRAM_CTRL_WR_MASK BIT(1)
310 #define PPE_SRAM_CTRL_REQ_MASK BIT(0)
342 #define GDM3_PAD_EN_MASK BIT(28)
345 #define GDM4_PAD_EN_MASK BIT(28)
349 #define GDM4_SPORT_OFF2_MASK GENMASK(19, 16)
355 #define IP_ASSEMBLE_NBQ_MASK GENMASK(20, 16)
360 #define MC_VLAN_EN_MASK BIT(0)
363 #define MC_VLAN_CFG_CMD_DONE_MASK BIT(31)
364 #define MC_VLAN_CFG_TABLE_ID_MASK GENMASK(21, 16)
366 #define MC_VLAN_CFG_TABLE_SEL_MASK BIT(4)
367 #define MC_VLAN_CFG_RW_MASK BIT(0)
379 #define FC_ID_OF_SRC_PORT26_MASK GENMASK(20, 16)
387 #define GLOBAL_CFG_RX_2B_OFFSET_MASK BIT(31)
389 #define GLOBAL_CFG_CPU_TXR_RR_MASK BIT(28)
390 #define GLOBAL_CFG_DSCP_BYTE_SWAP_MASK BIT(27)
391 #define GLOBAL_CFG_PAYLOAD_BYTE_SWAP_MASK BIT(26)
392 #define GLOBAL_CFG_MULTICAST_MODIFY_FP_MASK BIT(25)
393 #define GLOBAL_CFG_OAM_MODIFY_MASK BIT(24)
394 #define GLOBAL_CFG_RESET_MASK BIT(23)
395 #define GLOBAL_CFG_RESET_DONE_MASK BIT(22)
396 #define GLOBAL_CFG_MULTICAST_EN_MASK BIT(21)
397 #define GLOBAL_CFG_IRQ1_EN_MASK BIT(20)
398 #define GLOBAL_CFG_IRQ0_EN_MASK BIT(19)
399 #define GLOBAL_CFG_LOOPCNT_EN_MASK BIT(18)
400 #define GLOBAL_CFG_RD_BYPASS_WR_MASK BIT(17)
401 #define GLOBAL_CFG_QDMA_LOOPBACK_MASK BIT(16)
403 #define GLOBAL_CFG_CHECK_DONE_MASK BIT(7)
404 #define GLOBAL_CFG_TX_WB_DONE_MASK BIT(6)
406 #define GLOBAL_CFG_RX_DMA_BUSY_MASK BIT(3)
407 #define GLOBAL_CFG_RX_DMA_EN_MASK BIT(2)
408 #define GLOBAL_CFG_TX_DMA_BUSY_MASK BIT(1)
409 #define GLOBAL_CFG_TX_DMA_EN_MASK BIT(0)
416 #define HW_FWD_DSCP_SCATTER_LEN_MASK GENMASK(17, 16)
432 #define RX15_COHERENT_INT_MASK BIT(31)
433 #define RX14_COHERENT_INT_MASK BIT(30)
434 #define RX13_COHERENT_INT_MASK BIT(29)
435 #define RX12_COHERENT_INT_MASK BIT(28)
436 #define RX11_COHERENT_INT_MASK BIT(27)
437 #define RX10_COHERENT_INT_MASK BIT(26)
438 #define RX9_COHERENT_INT_MASK BIT(25)
439 #define RX8_COHERENT_INT_MASK BIT(24)
440 #define RX7_COHERENT_INT_MASK BIT(23)
441 #define RX6_COHERENT_INT_MASK BIT(22)
442 #define RX5_COHERENT_INT_MASK BIT(21)
443 #define RX4_COHERENT_INT_MASK BIT(20)
444 #define RX3_COHERENT_INT_MASK BIT(19)
445 #define RX2_COHERENT_INT_MASK BIT(18)
446 #define RX1_COHERENT_INT_MASK BIT(17)
447 #define RX0_COHERENT_INT_MASK BIT(16)
448 #define TX7_COHERENT_INT_MASK BIT(15)
449 #define TX6_COHERENT_INT_MASK BIT(14)
450 #define TX5_COHERENT_INT_MASK BIT(13)
451 #define TX4_COHERENT_INT_MASK BIT(12)
452 #define TX3_COHERENT_INT_MASK BIT(11)
453 #define TX2_COHERENT_INT_MASK BIT(10)
454 #define TX1_COHERENT_INT_MASK BIT(9)
455 #define TX0_COHERENT_INT_MASK BIT(8)
456 #define CNT_OVER_FLOW_INT_MASK BIT(7)
457 #define IRQ1_FULL_INT_MASK BIT(5)
458 #define IRQ1_INT_MASK BIT(4)
459 #define HWFWD_DSCP_LOW_INT_MASK BIT(3)
460 #define HWFWD_DSCP_EMPTY_INT_MASK BIT(2)
461 #define IRQ0_FULL_INT_MASK BIT(1)
462 #define IRQ0_INT_MASK BIT(0)
484 #define RX15_NO_CPU_DSCP_INT_MASK BIT(31)
485 #define RX14_NO_CPU_DSCP_INT_MASK BIT(30)
486 #define RX13_NO_CPU_DSCP_INT_MASK BIT(29)
487 #define RX12_NO_CPU_DSCP_INT_MASK BIT(28)
488 #define RX11_NO_CPU_DSCP_INT_MASK BIT(27)
489 #define RX10_NO_CPU_DSCP_INT_MASK BIT(26)
490 #define RX9_NO_CPU_DSCP_INT_MASK BIT(25)
491 #define RX8_NO_CPU_DSCP_INT_MASK BIT(24)
492 #define RX7_NO_CPU_DSCP_INT_MASK BIT(23)
493 #define RX6_NO_CPU_DSCP_INT_MASK BIT(22)
494 #define RX5_NO_CPU_DSCP_INT_MASK BIT(21)
495 #define RX4_NO_CPU_DSCP_INT_MASK BIT(20)
496 #define RX3_NO_CPU_DSCP_INT_MASK BIT(19)
497 #define RX2_NO_CPU_DSCP_INT_MASK BIT(18)
498 #define RX1_NO_CPU_DSCP_INT_MASK BIT(17)
499 #define RX0_NO_CPU_DSCP_INT_MASK BIT(16)
500 #define RX15_DONE_INT_MASK BIT(15)
501 #define RX14_DONE_INT_MASK BIT(14)
502 #define RX13_DONE_INT_MASK BIT(13)
503 #define RX12_DONE_INT_MASK BIT(12)
504 #define RX11_DONE_INT_MASK BIT(11)
505 #define RX10_DONE_INT_MASK BIT(10)
506 #define RX9_DONE_INT_MASK BIT(9)
507 #define RX8_DONE_INT_MASK BIT(8)
508 #define RX7_DONE_INT_MASK BIT(7)
509 #define RX6_DONE_INT_MASK BIT(6)
510 #define RX5_DONE_INT_MASK BIT(5)
511 #define RX4_DONE_INT_MASK BIT(4)
512 #define RX3_DONE_INT_MASK BIT(3)
513 #define RX2_DONE_INT_MASK BIT(2)
514 #define RX1_DONE_INT_MASK BIT(1)
515 #define RX0_DONE_INT_MASK BIT(0)
532 #define TX31_COHERENT_INT_MASK BIT(31)
533 #define TX30_COHERENT_INT_MASK BIT(30)
534 #define TX29_COHERENT_INT_MASK BIT(29)
535 #define TX28_COHERENT_INT_MASK BIT(28)
536 #define TX27_COHERENT_INT_MASK BIT(27)
537 #define TX26_COHERENT_INT_MASK BIT(26)
538 #define TX25_COHERENT_INT_MASK BIT(25)
539 #define TX24_COHERENT_INT_MASK BIT(24)
540 #define TX23_COHERENT_INT_MASK BIT(23)
541 #define TX22_COHERENT_INT_MASK BIT(22)
542 #define TX21_COHERENT_INT_MASK BIT(21)
543 #define TX20_COHERENT_INT_MASK BIT(20)
544 #define TX19_COHERENT_INT_MASK BIT(19)
545 #define TX18_COHERENT_INT_MASK BIT(18)
546 #define TX17_COHERENT_INT_MASK BIT(17)
547 #define TX16_COHERENT_INT_MASK BIT(16)
548 #define TX15_COHERENT_INT_MASK BIT(15)
549 #define TX14_COHERENT_INT_MASK BIT(14)
550 #define TX13_COHERENT_INT_MASK BIT(13)
551 #define TX12_COHERENT_INT_MASK BIT(12)
552 #define TX11_COHERENT_INT_MASK BIT(11)
553 #define TX10_COHERENT_INT_MASK BIT(10)
554 #define TX9_COHERENT_INT_MASK BIT(9)
555 #define TX8_COHERENT_INT_MASK BIT(8)
574 #define TX_IRQ_THR_MASK GENMASK(27, 16)
581 #define IRQ_ENTRY_LEN_MASK GENMASK(27, 16)
585 (((_n) < 8) ? 0x0100 + ((_n) << 5) : 0x0b00 + (((_n) - 8) << 5))
588 (((_n) < 8) ? 0x0104 + ((_n) << 5) : 0x0b04 + (((_n) - 8) << 5))
590 #define TX_RING_IRQ_BLOCKING_MAP_MASK BIT(6)
591 #define TX_RING_IRQ_BLOCKING_CFG_MASK BIT(4)
592 #define TX_RING_IRQ_BLOCKING_TX_DROP_EN_MASK BIT(2)
593 #define TX_RING_IRQ_BLOCKING_MAX_TH_TXRING_EN_MASK BIT(1)
594 #define TX_RING_IRQ_BLOCKING_MIN_TH_TXRING_EN_MASK BIT(0)
597 (((_n) < 8) ? 0x0108 + ((_n) << 5) : 0x0b08 + (((_n) - 8) << 5))
602 (((_n) < 8) ? 0x010c + ((_n) << 5) : 0x0b0c + (((_n) - 8) << 5))
606 #define IRQ_RING_IDX_MASK GENMASK(20, 16)
610 (((_n) < 16) ? 0x0200 + ((_n) << 5) : 0x0e00 + (((_n) - 16) << 5))
613 (((_n) < 16) ? 0x0204 + ((_n) << 5) : 0x0e04 + (((_n) - 16) << 5))
615 #define RX_RING_THR_MASK GENMASK(31, 16)
619 (((_n) < 16) ? 0x0208 + ((_n) << 5) : 0x0e08 + (((_n) - 16) << 5))
624 (((_n) < 16) ? 0x020c + ((_n) << 5) : 0x0e0c + (((_n) - 16) << 5))
627 (((_n) < 16) ? 0x0210 + ((_n) << 5) : 0x0e10 + (((_n) - 16) << 5))
630 (((_n) < 16) ? 0x0214 + ((_n) << 5) : 0x0e14 + (((_n) - 16) << 5))
636 #define RX_RING_SG_EN_MASK BIT(0)
639 #define INGRESS_TRTCM_EN_MASK BIT(31)
640 #define INGRESS_TRTCM_MODE_MASK BIT(30)
641 #define INGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
645 #define TXQ_DISABLE_CHAN_QUEUE_MASK(_n, _m) BIT((_m) + (((_n) & 0x3) << 3))
651 #define CNTR_EN_MASK BIT(31)
652 #define CNTR_ALL_CHAN_EN_MASK BIT(30)
653 #define CNTR_ALL_QUEUE_EN_MASK BIT(29)
654 #define CNTR_ALL_DSCP_RING_EN_MASK BIT(28)
656 #define CNTR_DSCP_RING_MASK GENMASK(20, 16)
663 #define LMGR_INIT_START BIT(31)
664 #define LMGR_SRAM_MODE_MASK BIT(30)
666 #define HW_FWD_DESC_NUM_MASK GENMASK(16, 0)
672 #define EGRESS_RATE_METER_EN_MASK BIT(31)
673 #define EGRESS_RATE_METER_EQ_RATE_EN_MASK BIT(17)
674 #define EGRESS_RATE_METER_WINDOW_SZ_MASK GENMASK(16, 12)
678 #define EGRESS_TRTCM_EN_MASK BIT(31)
679 #define EGRESS_TRTCM_MODE_MASK BIT(30)
680 #define EGRESS_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
683 #define TRTCM_PARAM_RW_MASK BIT(31)
684 #define TRTCM_PARAM_RW_DONE_MASK BIT(30)
688 #define TRTCM_PARAM_RATE_TYPE_MASK BIT(16)
695 #define TWRR_WEIGHT_SCALE_MASK BIT(31)
696 #define TWRR_WEIGHT_BASE_MASK BIT(3)
699 #define TWRR_RW_CMD_MASK BIT(31)
700 #define TWRR_RW_CMD_DONE BIT(30)
702 #define TWRR_QUEUE_IDX_MASK GENMASK(18, 16)
706 #define PSE_BUF_ESTIMATE_EN_MASK BIT(29)
712 #define GLB_TRTCM_EN_MASK BIT(31)
713 #define GLB_TRTCM_MODE_MASK BIT(30)
714 #define GLB_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
718 #define TXQ_CNGST_DROP_EN BIT(31)
719 #define TXQ_CNGST_DEI_DROP_EN BIT(30)
722 #define SLA_TRTCM_EN_MASK BIT(31)
723 #define SLA_TRTCM_MODE_MASK BIT(30)
724 #define SLA_SLOW_TICK_RATIO_MASK GENMASK(29, 16)
728 #define QDMA_DESC_DONE_MASK BIT(31)
729 #define QDMA_DESC_DROP_MASK BIT(30) /* tx: drop - rx: overflow */
730 #define QDMA_DESC_MORE_MASK BIT(29) /* more SG elements */
731 #define QDMA_DESC_DEI_MASK BIT(25)
732 #define QDMA_DESC_NO_DROP_MASK BIT(24)
737 #define QDMA_ETH_TXMSG_MIC_IDX_MASK BIT(30)
739 #define QDMA_ETH_TXMSG_ICO_MASK BIT(13)
740 #define QDMA_ETH_TXMSG_UCO_MASK BIT(12)
741 #define QDMA_ETH_TXMSG_TCO_MASK BIT(11)
742 #define QDMA_ETH_TXMSG_TSO_MASK BIT(10)
743 #define QDMA_ETH_TXMSG_FAST_MASK BIT(9)
744 #define QDMA_ETH_TXMSG_OAM_MASK BIT(8)
748 #define QDMA_ETH_TXMSG_NO_DROP BIT(31)
752 #define QDMA_ETH_TXMSG_HWF_MASK BIT(14)
753 #define QDMA_ETH_TXMSG_HOP_MASK BIT(13)
754 #define QDMA_ETH_TXMSG_PTP_MASK BIT(12)
761 #define QDMA_ETH_RXMSG_DEI_MASK BIT(31)
762 #define QDMA_ETH_RXMSG_IP6_MASK BIT(30)
763 #define QDMA_ETH_RXMSG_IP4_MASK BIT(29)
764 #define QDMA_ETH_RXMSG_IP4F_MASK BIT(28)
765 #define QDMA_ETH_RXMSG_L4_VALID_MASK BIT(27)
766 #define QDMA_ETH_RXMSG_L4F_MASK BIT(26)
768 #define QDMA_ETH_RXMSG_CRSN_MASK GENMASK(20, 16)
783 #define QDMA_FWD_DESC_CTX_MASK BIT(31)
785 #define QDMA_FWD_DESC_IDX_MASK GENMASK(27, 16)