Lines Matching +full:clock +full:- +full:phase
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * Copyright (C) 2011 - 2012 Michal Simek <monstr@monstr.eu>
9 * Based on sdhci-of-esdhc.c
18 #include <linux/clk-provider.h>
26 #include <linux/firmware/xlnx-zynqmp.h>
29 #include "sdhci-cqhci.h"
30 #include "sdhci-pltfm.h"
81 /* Default settings for ZynqMP Clock Phases */
94 * On some SoCs the syscon area has a feature where the upper 16-bits of
95 * each 32-bit register act as a write mask for the lower 16-bits. This allows
103 * struct sdhci_arasan_soc_ctl_field - Field used in sdhci_arasan_soc_ctl_map
107 * @shift: Bit offset within @reg of this field (or -1 if not avail)
116 * struct sdhci_arasan_soc_ctl_map - Map in syscon to corecfg registers
135 * struct sdhci_arasan_clk_ops - Clock Operations for Arasan SD controller
137 * @sdcardclk_ops: The output clock related operations
138 * @sampleclk_ops: The sample clock related operations
146 * struct sdhci_arasan_clk_data - Arasan Controller Clock Data.
148 * @sdcardclk_hw: Struct for the clock we might provide to a PHY.
149 * @sdcardclk: Pointer to normal 'struct clock' for sdcardclk_hw.
150 * @sampleclk_hw: Struct for the clock we might provide to a PHY.
151 * @sampleclk: Pointer to normal 'struct clock' for sampleclk_hw.
152 * @clk_phase_in: Array of Input Clock Phase Delays for all speed modes
153 * @clk_phase_out: Array of Output Clock Phase Delays for all speed modes
154 * @set_clk_delays: Function pointer for setting Clock Delays
155 * @clk_of_data: Platform specific runtime clock data storage pointer
169 * struct sdhci_arasan_data - Arasan Controller Data
172 * @clk_ahb: Pointer to the AHB clock
177 * @clk_data: Struct for the Arasan Controller Clock Data.
178 * @clk_ops: Struct for the Arasan Controller Clock Operations.
201 * internal clock even when the clock isn't stable */
225 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
231 .clockmultiplier = { .reg = 0, .width = -1, .shift = -1 },
246 reg = readl(host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_delaychain()
252 writel(reg, host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_delaychain()
259 reg = readl(host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_dll()
265 writel(reg, host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_set_dll()
270 return readl_relaxed_poll_timeout(host->ioaddr + PHY_CTRL_REG2, reg, in sdhci_arasan_phy_set_dll()
275 static void sdhci_arasan_phy_dll_set_freq(struct sdhci_host *host, int clock) in sdhci_arasan_phy_dll_set_freq() argument
279 freq = DIV_ROUND_CLOSEST(clock, 1000000); in sdhci_arasan_phy_dll_set_freq()
291 reg = readl(host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_dll_set_freq()
294 writel(reg, host->ioaddr + PHY_CTRL_REG2); in sdhci_arasan_phy_dll_set_freq()
298 * sdhci_arasan_syscon_write - Write to a field in soc_ctl registers
317 struct regmap *soc_ctl_base = sdhci_arasan->soc_ctl_base; in sdhci_arasan_syscon_write()
318 u32 reg = fld->reg; in sdhci_arasan_syscon_write()
319 u16 width = fld->width; in sdhci_arasan_syscon_write()
320 s16 shift = fld->shift; in sdhci_arasan_syscon_write()
330 return -EINVAL; in sdhci_arasan_syscon_write()
332 if (sdhci_arasan->soc_ctl_map->hiword_update) in sdhci_arasan_syscon_write()
344 mmc_hostname(host->mmc), ret); in sdhci_arasan_syscon_write()
349 static void sdhci_arasan_set_clock(struct sdhci_host *host, unsigned int clock) in sdhci_arasan_set_clock() argument
353 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clock()
356 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
357 if (!sdhci_arasan->is_phy_on && clock <= PHY_CLK_TOO_SLOW_HZ) { in sdhci_arasan_set_clock()
359 * If PHY off, set clock to max speed and power PHY on. in sdhci_arasan_set_clock()
362 * when changing the clock the PHY doesn't like to be in sdhci_arasan_set_clock()
365 * clock is off. in sdhci_arasan_set_clock()
371 sdhci_set_clock(host, host->max_clk); in sdhci_arasan_set_clock()
372 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
374 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
378 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
383 * sdhci_set_clock() will set the real clock. in sdhci_arasan_set_clock()
385 } else if (clock > PHY_CLK_TOO_SLOW_HZ) { in sdhci_arasan_set_clock()
387 * At higher clock speeds the PHY is fine being power in sdhci_arasan_set_clock()
389 * changing clock speeds. in sdhci_arasan_set_clock()
395 if (ctrl_phy && sdhci_arasan->is_phy_on) { in sdhci_arasan_set_clock()
396 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_set_clock()
397 sdhci_arasan->is_phy_on = false; in sdhci_arasan_set_clock()
400 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN) { in sdhci_arasan_set_clock()
406 if (clock == DEFAULT_SPEED_MAX_DTR) in sdhci_arasan_set_clock()
407 clock = (DEFAULT_SPEED_MAX_DTR * 19) / 25; in sdhci_arasan_set_clock()
410 /* Set the Input and Output Clock Phase Delays */ in sdhci_arasan_set_clock()
411 if (clk_data->set_clk_delays && clock > PHY_CLK_TOO_SLOW_HZ) in sdhci_arasan_set_clock()
412 clk_data->set_clk_delays(host); in sdhci_arasan_set_clock()
414 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) { in sdhci_arasan_set_clock()
418 sdhci_arasan_phy_dll_set_freq(host, clock); in sdhci_arasan_set_clock()
419 } else if (sdhci_arasan->internal_phy_reg) { in sdhci_arasan_set_clock()
424 sdhci_set_clock(host, clock); in sdhci_arasan_set_clock()
426 if (sdhci_arasan->internal_phy_reg && clock >= MIN_PHY_CLK_HZ) in sdhci_arasan_set_clock()
429 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE) in sdhci_arasan_set_clock()
432 * after enabling the clock even though the clock is not in sdhci_arasan_set_clock()
433 * stable. Trying to use a clock without waiting here results in sdhci_arasan_set_clock()
440 if (phy_power_on(sdhci_arasan->phy)) { in sdhci_arasan_set_clock()
442 mmc_hostname(host->mmc)); in sdhci_arasan_set_clock()
446 sdhci_arasan->is_phy_on = true; in sdhci_arasan_set_clock()
457 if (ios->enhanced_strobe) in sdhci_arasan_hs400_enhanced_strobe()
473 if (sdhci_arasan->quirks & SDHCI_ARASAN_QUIRK_FORCE_CDTEST) { in sdhci_arasan_reset()
498 switch (ios->signal_voltage) { in sdhci_arasan_voltage_switch()
514 return -EINVAL; in sdhci_arasan_voltage_switch()
536 cqhci_irq(host->mmc, intmask, cmd_error, data_error); in sdhci_arasan_cqhci_irq()
586 * sdhci_arasan_suspend - Suspend method for the driver
600 if (host->tuning_mode != SDHCI_TUNING_MODE_3) in sdhci_arasan_suspend()
601 mmc_retune_needed(host->mmc); in sdhci_arasan_suspend()
603 if (sdhci_arasan->has_cqe) { in sdhci_arasan_suspend()
604 ret = cqhci_suspend(host->mmc); in sdhci_arasan_suspend()
613 if (!IS_ERR(sdhci_arasan->phy) && sdhci_arasan->is_phy_on) { in sdhci_arasan_suspend()
614 ret = phy_power_off(sdhci_arasan->phy); in sdhci_arasan_suspend()
622 sdhci_arasan->is_phy_on = false; in sdhci_arasan_suspend()
625 clk_disable(pltfm_host->clk); in sdhci_arasan_suspend()
626 clk_disable(sdhci_arasan->clk_ahb); in sdhci_arasan_suspend()
632 * sdhci_arasan_resume - Resume method for the driver
646 ret = clk_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_resume()
648 dev_err(dev, "Cannot enable AHB clock.\n"); in sdhci_arasan_resume()
652 ret = clk_enable(pltfm_host->clk); in sdhci_arasan_resume()
654 dev_err(dev, "Cannot enable SD clock.\n"); in sdhci_arasan_resume()
658 if (!IS_ERR(sdhci_arasan->phy) && host->mmc->actual_clock) { in sdhci_arasan_resume()
659 ret = phy_power_on(sdhci_arasan->phy); in sdhci_arasan_resume()
664 sdhci_arasan->is_phy_on = true; in sdhci_arasan_resume()
673 if (sdhci_arasan->has_cqe) in sdhci_arasan_resume()
674 return cqhci_resume(host->mmc); in sdhci_arasan_resume()
684 * sdhci_arasan_sdcardclk_recalc_rate - Return the card clock rate
686 * @hw: Pointer to the hardware clock structure.
689 * Return the current actual rate of the SD card clock. This can be used
692 * Return: The card clock rate.
701 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sdcardclk_recalc_rate()
703 return host->mmc->actual_clock; in sdhci_arasan_sdcardclk_recalc_rate()
711 * sdhci_arasan_sampleclk_recalc_rate - Return the sampling clock rate
713 * @hw: Pointer to the hardware clock structure.
716 * Return the current actual rate of the sampling clock. This can be used
719 * Return: The sample clock rate.
728 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_sampleclk_recalc_rate()
730 return host->mmc->actual_clock; in sdhci_arasan_sampleclk_recalc_rate()
738 * sdhci_zynqmp_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
740 * @hw: Pointer to the hardware clock structure.
741 * @degrees: The clock phase shift between 0 - 359.
743 * Set the SD Output Clock Tap Delays for Output path
753 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sdcardclk_set_phase()
760 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sdcardclk_set_phase()
763 switch (host->timing) { in sdhci_zynqmp_sdcardclk_set_phase()
769 /* For 50MHz clock, 30 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
773 /* For 100MHz clock, 15 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
778 /* For 200MHz clock, 8 Taps are available */ in sdhci_zynqmp_sdcardclk_set_phase()
787 /* Set the Clock Phase */ in sdhci_zynqmp_sdcardclk_set_phase()
804 * sdhci_zynqmp_sampleclk_set_phase - Set the SD Input Clock Tap Delays
806 * @hw: Pointer to the hardware clock structure.
807 * @degrees: The clock phase shift between 0 - 359.
809 * Set the SD Input Clock Tap Delays for Input path
819 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_sampleclk_set_phase()
826 if (host->version < SDHCI_SPEC_300) in sdhci_zynqmp_sampleclk_set_phase()
832 switch (host->timing) { in sdhci_zynqmp_sampleclk_set_phase()
838 /* For 50MHz clock, 120 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
842 /* For 100MHz clock, 60 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
847 /* For 200MHz clock, 30 Taps are available */ in sdhci_zynqmp_sampleclk_set_phase()
856 /* Set the Clock Phase */ in sdhci_zynqmp_sampleclk_set_phase()
870 * sdhci_versal_sdcardclk_set_phase - Set the SD Output Clock Tap Delays
872 * @hw: Pointer to the hardware clock structure.
873 * @degrees: The clock phase shift between 0 - 359.
875 * Set the SD Output Clock Tap Delays for Output path
885 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sdcardclk_set_phase()
889 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sdcardclk_set_phase()
892 switch (host->timing) { in sdhci_versal_sdcardclk_set_phase()
898 /* For 50MHz clock, 30 Taps are available */ in sdhci_versal_sdcardclk_set_phase()
902 /* For 100MHz clock, 15 Taps are available */ in sdhci_versal_sdcardclk_set_phase()
907 /* For 200MHz clock, 8 Taps are available */ in sdhci_versal_sdcardclk_set_phase()
916 /* Set the Clock Phase */ in sdhci_versal_sdcardclk_set_phase()
937 * sdhci_versal_sampleclk_set_phase - Set the SD Input Clock Tap Delays
939 * @hw: Pointer to the hardware clock structure.
940 * @degrees: The clock phase shift between 0 - 359.
942 * Set the SD Input Clock Tap Delays for Input path
952 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_sampleclk_set_phase()
956 if (host->version < SDHCI_SPEC_300) in sdhci_versal_sampleclk_set_phase()
959 switch (host->timing) { in sdhci_versal_sampleclk_set_phase()
965 /* For 50MHz clock, 120 Taps are available */ in sdhci_versal_sampleclk_set_phase()
969 /* For 100MHz clock, 60 Taps are available */ in sdhci_versal_sampleclk_set_phase()
974 /* For 200MHz clock, 30 Taps are available */ in sdhci_versal_sampleclk_set_phase()
983 /* Set the Clock Phase */ in sdhci_versal_sampleclk_set_phase()
1013 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_net_emmc_sdcardclk_set_phase()
1016 switch (host->timing) { in sdhci_versal_net_emmc_sdcardclk_set_phase()
1023 /* For 200MHz clock, 32 Taps are available */ in sdhci_versal_net_emmc_sdcardclk_set_phase()
1032 /* Set the Clock Phase */ in sdhci_versal_net_emmc_sdcardclk_set_phase()
1058 struct sdhci_host *host = sdhci_arasan->host; in sdhci_versal_net_emmc_sampleclk_set_phase()
1062 switch (host->timing) { in sdhci_versal_net_emmc_sampleclk_set_phase()
1080 /* Set the Clock Phase */ in sdhci_versal_net_emmc_sampleclk_set_phase()
1123 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in arasan_zynqmp_execute_tuning()
1130 if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in arasan_zynqmp_execute_tuning()
1145 * sdhci_arasan_update_clockmultiplier - Set corecfg_clockmultiplier
1150 * The corecfg_clockmultiplier is supposed to contain clock multiplier
1151 * value of programmable clock generator.
1154 * - Many existing devices don't seem to do this and work fine. To keep
1158 * - The value of corecfg_clockmultiplier should sync with that of corresponding
1168 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_clockmultiplier()
1175 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_clockmultiplier()
1176 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_clockmultiplier()
1177 mmc_hostname(host->mmc)); in sdhci_arasan_update_clockmultiplier()
1181 sdhci_arasan_syscon_write(host, &soc_ctl_map->clockmultiplier, value); in sdhci_arasan_update_clockmultiplier()
1185 * sdhci_arasan_update_baseclkfreq - Set corecfg_baseclkfreq
1193 * - Many existing devices don't seem to do this and work fine. To keep
1197 * - It's assumed that clk_xin is not dynamic and that we use the SDHCI divider
1198 * to achieve lower clock rates. That means that this function is called once
1206 sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_baseclkfreq()
1207 u32 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_arasan_update_baseclkfreq()
1214 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_baseclkfreq()
1215 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_baseclkfreq()
1216 mmc_hostname(host->mmc)); in sdhci_arasan_update_baseclkfreq()
1220 sdhci_arasan_syscon_write(host, &soc_ctl_map->baseclkfreq, mhz); in sdhci_arasan_update_baseclkfreq()
1227 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_set_clk_delays()
1229 clk_set_phase(clk_data->sampleclk, in sdhci_arasan_set_clk_delays()
1230 clk_data->clk_phase_in[host->timing]); in sdhci_arasan_set_clk_delays()
1231 clk_set_phase(clk_data->sdcardclk, in sdhci_arasan_set_clk_delays()
1232 clk_data->clk_phase_out[host->timing]); in sdhci_arasan_set_clk_delays()
1239 struct device_node *np = dev->of_node; in arasan_dt_read_clk_phase()
1246 * Tap Values then use the pre-defined values. in arasan_dt_read_clk_phase()
1251 dev_dbg(dev, "Using predefined clock phase for %s = %d %d\n", in arasan_dt_read_clk_phase()
1252 prop, clk_data->clk_phase_in[timing], in arasan_dt_read_clk_phase()
1253 clk_data->clk_phase_out[timing]); in arasan_dt_read_clk_phase()
1257 /* The values read are Input and Output Clock Delays in order */ in arasan_dt_read_clk_phase()
1258 clk_data->clk_phase_in[timing] = clk_phase[0]; in arasan_dt_read_clk_phase()
1259 clk_data->clk_phase_out[timing] = clk_phase[1]; in arasan_dt_read_clk_phase()
1263 * arasan_dt_parse_clk_phases - Read Clock Delay values from DT
1266 * @clk_data: Pointer to the Clock Data structure
1268 * Called at initialization to parse the values of Clock Delays.
1281 clk_data->set_clk_delays = sdhci_arasan_set_clk_delays; in arasan_dt_parse_clk_phases()
1283 if (of_device_is_compatible(dev->of_node, "xlnx,zynqmp-8.9a")) { in arasan_dt_parse_clk_phases()
1289 of_property_read_u32(dev->of_node, "xlnx,mio-bank", &mio_bank); in arasan_dt_parse_clk_phases()
1296 clk_data->clk_phase_in[i] = zynqmp_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1297 clk_data->clk_phase_out[i] = zynqmp_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1301 if (of_device_is_compatible(dev->of_node, "xlnx,versal-8.9a")) { in arasan_dt_parse_clk_phases()
1308 clk_data->clk_phase_in[i] = versal_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1309 clk_data->clk_phase_out[i] = versal_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1312 if (of_device_is_compatible(dev->of_node, "xlnx,versal-net-emmc")) { in arasan_dt_parse_clk_phases()
1319 clk_data->clk_phase_in[i] = versal_net_iclk_phase[i]; in arasan_dt_parse_clk_phases()
1320 clk_data->clk_phase_out[i] = versal_net_oclk_phase[i]; in arasan_dt_parse_clk_phases()
1324 "clk-phase-legacy"); in arasan_dt_parse_clk_phases()
1326 "clk-phase-mmc-hs"); in arasan_dt_parse_clk_phases()
1328 "clk-phase-sd-hs"); in arasan_dt_parse_clk_phases()
1330 "clk-phase-uhs-sdr12"); in arasan_dt_parse_clk_phases()
1332 "clk-phase-uhs-sdr25"); in arasan_dt_parse_clk_phases()
1334 "clk-phase-uhs-sdr50"); in arasan_dt_parse_clk_phases()
1336 "clk-phase-uhs-sdr104"); in arasan_dt_parse_clk_phases()
1338 "clk-phase-uhs-ddr50"); in arasan_dt_parse_clk_phases()
1340 "clk-phase-mmc-ddr52"); in arasan_dt_parse_clk_phases()
1342 "clk-phase-mmc-hs200"); in arasan_dt_parse_clk_phases()
1344 "clk-phase-mmc-hs400"); in arasan_dt_parse_clk_phases()
1491 /* SoC-specific compatible strings w/ soc_ctl_map */
1493 .compatible = "rockchip,rk3399-sdhci-5.1",
1497 .compatible = "intel,lgm-sdhci-5.1-emmc",
1501 .compatible = "intel,lgm-sdhci-5.1-sdxc",
1505 .compatible = "intel,keembay-sdhci-5.1-emmc",
1509 .compatible = "intel,keembay-sdhci-5.1-sd",
1513 .compatible = "intel,keembay-sdhci-5.1-sdio",
1518 .compatible = "arasan,sdhci-8.9a",
1522 .compatible = "arasan,sdhci-5.1",
1526 .compatible = "arasan,sdhci-4.9a",
1530 .compatible = "xlnx,zynqmp-8.9a",
1534 .compatible = "xlnx,versal-8.9a",
1538 .compatible = "xlnx,versal-net-emmc",
1546 * sdhci_arasan_register_sdcardclk - Register the sdcardclk for a PHY to use
1549 * @clk_xin: Pointer to the functional clock
1552 * Some PHY devices need to know what the actual card clock is. In order for
1553 * them to find out, we'll provide a clock through the common clock framework
1563 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sdcardclk()
1564 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdcardclk()
1569 ret = of_property_read_string_index(np, "clock-output-names", 0, in sdhci_arasan_register_sdcardclk()
1572 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sdcardclk()
1580 sdcardclk_init.ops = sdhci_arasan->clk_ops->sdcardclk_ops; in sdhci_arasan_register_sdcardclk()
1582 clk_data->sdcardclk_hw.init = &sdcardclk_init; in sdhci_arasan_register_sdcardclk()
1583 clk_data->sdcardclk = in sdhci_arasan_register_sdcardclk()
1584 devm_clk_register(dev, &clk_data->sdcardclk_hw); in sdhci_arasan_register_sdcardclk()
1585 if (IS_ERR(clk_data->sdcardclk)) in sdhci_arasan_register_sdcardclk()
1586 return PTR_ERR(clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1587 clk_data->sdcardclk_hw.init = NULL; in sdhci_arasan_register_sdcardclk()
1590 clk_data->sdcardclk); in sdhci_arasan_register_sdcardclk()
1592 dev_err(dev, "Failed to add sdcard clock provider\n"); in sdhci_arasan_register_sdcardclk()
1598 * sdhci_arasan_register_sampleclk - Register the sampleclk for a PHY to use
1601 * @clk_xin: Pointer to the functional clock
1604 * Some PHY devices need to know what the actual card clock is. In order for
1605 * them to find out, we'll provide a clock through the common clock framework
1615 struct sdhci_arasan_clk_data *clk_data = &sdhci_arasan->clk_data; in sdhci_arasan_register_sampleclk()
1616 struct device_node *np = dev->of_node; in sdhci_arasan_register_sampleclk()
1621 ret = of_property_read_string_index(np, "clock-output-names", 1, in sdhci_arasan_register_sampleclk()
1624 dev_err(dev, "DT has #clock-cells but no clock-output-names\n"); in sdhci_arasan_register_sampleclk()
1632 sampleclk_init.ops = sdhci_arasan->clk_ops->sampleclk_ops; in sdhci_arasan_register_sampleclk()
1634 clk_data->sampleclk_hw.init = &sampleclk_init; in sdhci_arasan_register_sampleclk()
1635 clk_data->sampleclk = in sdhci_arasan_register_sampleclk()
1636 devm_clk_register(dev, &clk_data->sampleclk_hw); in sdhci_arasan_register_sampleclk()
1637 if (IS_ERR(clk_data->sampleclk)) in sdhci_arasan_register_sampleclk()
1638 return PTR_ERR(clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1639 clk_data->sampleclk_hw.init = NULL; in sdhci_arasan_register_sampleclk()
1642 clk_data->sampleclk); in sdhci_arasan_register_sampleclk()
1644 dev_err(dev, "Failed to add sample clock provider\n"); in sdhci_arasan_register_sampleclk()
1650 * sdhci_arasan_unregister_sdclk - Undoes sdhci_arasan_register_sdclk()
1659 struct device_node *np = dev->of_node; in sdhci_arasan_unregister_sdclk()
1661 if (!of_property_present(np, "#clock-cells")) in sdhci_arasan_unregister_sdclk()
1664 of_clk_del_provider(dev->of_node); in sdhci_arasan_unregister_sdclk()
1668 * sdhci_arasan_update_support64b - Set SUPPORT_64B (64-bit System Bus Support)
1673 * 0: the Core supports only 32-bit System Address Bus.
1674 * 1: the Core supports 64-bit System Address Bus.
1678 * Keem Bay does not support 64-bit access.
1687 soc_ctl_map = sdhci_arasan->soc_ctl_map; in sdhci_arasan_update_support64b()
1692 if (!sdhci_arasan->soc_ctl_base) { in sdhci_arasan_update_support64b()
1693 pr_warn("%s: Have regmap, but no soc-ctl-syscon\n", in sdhci_arasan_update_support64b()
1694 mmc_hostname(host->mmc)); in sdhci_arasan_update_support64b()
1698 sdhci_arasan_syscon_write(host, &soc_ctl_map->support64b, value); in sdhci_arasan_update_support64b()
1702 * sdhci_arasan_register_sdclk - Register the sdcardclk for a PHY to use
1705 * @clk_xin: Pointer to the functional clock
1708 * Some PHY devices need to know what the actual card clock is. In order for
1709 * them to find out, we'll provide a clock through the common clock framework
1712 * Note: without seriously re-architecting SDHCI's clock code and testing on
1713 * all platforms, there's no way to create a totally beautiful clock here
1714 * with all clock ops implemented. Instead, we'll just create a clock that can
1715 * be queried and set the CLK_GET_RATE_NOCACHE attribute to tell common clock
1718 * re-architecting SDHCI if we see some benefit to it.
1726 struct device_node *np = dev->of_node; in sdhci_arasan_register_sdclk()
1730 /* Providing a clock to the PHY is optional; no error if missing */ in sdhci_arasan_register_sdclk()
1731 if (of_property_read_u32(np, "#clock-cells", &num_clks) < 0) in sdhci_arasan_register_sdclk()
1753 struct sdhci_host *host = sdhci_arasan->host; in sdhci_zynqmp_set_dynamic_config()
1754 struct clk_hw *hw = &sdhci_arasan->clk_data.sdcardclk_hw; in sdhci_zynqmp_set_dynamic_config()
1777 !!(host->mmc->caps & MMC_CAP_NONREMOVABLE)); in sdhci_zynqmp_set_dynamic_config()
1781 mhz = DIV_ROUND_CLOSEST_ULL(clk_get_rate(pltfm_host->clk), 1000000); in sdhci_zynqmp_set_dynamic_config()
1796 !!(host->mmc->caps & MMC_CAP_8_BIT_DATA)); in sdhci_zynqmp_set_dynamic_config()
1811 struct sdhci_host *host = sdhci_arasan->host; in sdhci_arasan_add_host()
1816 if (!sdhci_arasan->has_cqe) in sdhci_arasan_add_host()
1823 cq_host = devm_kzalloc(host->mmc->parent, in sdhci_arasan_add_host()
1826 ret = -ENOMEM; in sdhci_arasan_add_host()
1830 cq_host->mmio = host->ioaddr + SDHCI_ARASAN_CQE_BASE_ADDR; in sdhci_arasan_add_host()
1831 cq_host->ops = &sdhci_arasan_cqhci_ops; in sdhci_arasan_add_host()
1833 dma64 = host->flags & SDHCI_USE_64_BIT_DMA; in sdhci_arasan_add_host()
1835 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; in sdhci_arasan_add_host()
1837 ret = cqhci_init(cq_host, host->mmc, dma64); in sdhci_arasan_add_host()
1860 struct device *dev = &pdev->dev; in sdhci_arasan_probe()
1861 struct device_node *np = dev->of_node; in sdhci_arasan_probe()
1867 return -EINVAL; in sdhci_arasan_probe()
1869 host = sdhci_pltfm_init(pdev, data->pdata, sizeof(*sdhci_arasan)); in sdhci_arasan_probe()
1876 sdhci_arasan->host = host; in sdhci_arasan_probe()
1878 sdhci_arasan->soc_ctl_map = data->soc_ctl_map; in sdhci_arasan_probe()
1879 sdhci_arasan->clk_ops = data->clk_ops; in sdhci_arasan_probe()
1881 node = of_parse_phandle(np, "arasan,soc-ctl-syscon", 0); in sdhci_arasan_probe()
1883 sdhci_arasan->soc_ctl_base = syscon_node_to_regmap(node); in sdhci_arasan_probe()
1886 if (IS_ERR(sdhci_arasan->soc_ctl_base)) { in sdhci_arasan_probe()
1888 PTR_ERR(sdhci_arasan->soc_ctl_base), in sdhci_arasan_probe()
1896 sdhci_arasan->clk_ahb = devm_clk_get(dev, "clk_ahb"); in sdhci_arasan_probe()
1897 if (IS_ERR(sdhci_arasan->clk_ahb)) { in sdhci_arasan_probe()
1898 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->clk_ahb), in sdhci_arasan_probe()
1899 "clk_ahb clock not found.\n"); in sdhci_arasan_probe()
1905 ret = dev_err_probe(dev, PTR_ERR(clk_xin), "clk_xin clock not found.\n"); in sdhci_arasan_probe()
1909 ret = clk_prepare_enable(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
1911 dev_err(dev, "Unable to enable AHB clock.\n"); in sdhci_arasan_probe()
1915 /* If clock-frequency property is set, use the provided value */ in sdhci_arasan_probe()
1916 if (pltfm_host->clock && in sdhci_arasan_probe()
1917 pltfm_host->clock != clk_get_rate(clk_xin)) { in sdhci_arasan_probe()
1918 ret = clk_set_rate(clk_xin, pltfm_host->clock); in sdhci_arasan_probe()
1920 dev_err(&pdev->dev, "Failed to set SD clock rate\n"); in sdhci_arasan_probe()
1927 dev_err(dev, "Unable to enable SD clock.\n"); in sdhci_arasan_probe()
1937 if (of_property_read_bool(np, "xlnx,fails-without-test-cd")) in sdhci_arasan_probe()
1938 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_FORCE_CDTEST; in sdhci_arasan_probe()
1940 if (of_property_read_bool(np, "xlnx,int-clock-stable-broken")) in sdhci_arasan_probe()
1941 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_UNSTABLE; in sdhci_arasan_probe()
1943 pltfm_host->clk = clk_xin; in sdhci_arasan_probe()
1945 if (of_device_is_compatible(np, "rockchip,rk3399-sdhci-5.1")) in sdhci_arasan_probe()
1948 if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-emmc") || in sdhci_arasan_probe()
1949 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd") || in sdhci_arasan_probe()
1950 of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sdio")) { in sdhci_arasan_probe()
1954 host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; in sdhci_arasan_probe()
1963 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1964 host->mmc_host_ops.execute_tuning = in sdhci_arasan_probe()
1967 sdhci_arasan->quirks |= SDHCI_ARASAN_QUIRK_CLOCK_25_BROKEN; in sdhci_arasan_probe()
1968 host->quirks |= SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12; in sdhci_arasan_probe()
1971 arasan_dt_parse_clk_phases(dev, &sdhci_arasan->clk_data); in sdhci_arasan_probe()
1973 ret = mmc_of_parse(host->mmc); in sdhci_arasan_probe()
1979 if (of_device_is_compatible(np, "xlnx,zynqmp-8.9a")) { in sdhci_arasan_probe()
1988 sdhci_arasan->phy = ERR_PTR(-ENODEV); in sdhci_arasan_probe()
1989 if (of_device_is_compatible(np, "arasan,sdhci-5.1")) { in sdhci_arasan_probe()
1990 sdhci_arasan->phy = devm_phy_get(dev, "phy_arasan"); in sdhci_arasan_probe()
1991 if (IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_probe()
1992 ret = dev_err_probe(dev, PTR_ERR(sdhci_arasan->phy), in sdhci_arasan_probe()
1993 "No phy for arasan,sdhci-5.1.\n"); in sdhci_arasan_probe()
1997 ret = phy_init(sdhci_arasan->phy); in sdhci_arasan_probe()
2003 host->mmc_host_ops.hs400_enhanced_strobe = in sdhci_arasan_probe()
2005 host->mmc_host_ops.start_signal_voltage_switch = in sdhci_arasan_probe()
2007 sdhci_arasan->has_cqe = true; in sdhci_arasan_probe()
2008 host->mmc->caps2 |= MMC_CAP2_CQE; in sdhci_arasan_probe()
2010 if (!of_property_read_bool(np, "disable-cqe-dcmd")) in sdhci_arasan_probe()
2011 host->mmc->caps2 |= MMC_CAP2_CQE_DCMD; in sdhci_arasan_probe()
2014 if (of_device_is_compatible(np, "xlnx,versal-net-emmc")) in sdhci_arasan_probe()
2015 sdhci_arasan->internal_phy_reg = true; in sdhci_arasan_probe()
2024 if (!IS_ERR(sdhci_arasan->phy)) in sdhci_arasan_probe()
2025 phy_exit(sdhci_arasan->phy); in sdhci_arasan_probe()
2031 clk_disable_unprepare(sdhci_arasan->clk_ahb); in sdhci_arasan_probe()
2042 struct clk *clk_ahb = sdhci_arasan->clk_ahb; in sdhci_arasan_remove()
2043 struct clk *clk_xin = pltfm_host->clk; in sdhci_arasan_remove()
2045 if (!IS_ERR(sdhci_arasan->phy)) { in sdhci_arasan_remove()
2046 if (sdhci_arasan->is_phy_on) in sdhci_arasan_remove()
2047 phy_power_off(sdhci_arasan->phy); in sdhci_arasan_remove()
2048 phy_exit(sdhci_arasan->phy); in sdhci_arasan_remove()
2051 sdhci_arasan_unregister_sdclk(&pdev->dev); in sdhci_arasan_remove()
2061 .name = "sdhci-arasan",