Lines Matching +full:lpc +full:- +full:ctrl
1 // SPDX-License-Identifier: GPL-2.0-or-later
4 * (Based on NXP driver for lpc 31xx)
14 #include <linux/dma-mapping.h>
38 #include <linux/mmc/slot-gpio.h>
73 ((d)->des2 = ((d)->des2 & cpu_to_le32(0x03ffe000)) | \
78 u32 des4; /* Lower 32-bits of Buffer Address Pointer 1*/
79 u32 des5; /* Upper 32-bits of Buffer Address Pointer 1*/
81 u32 des6; /* Lower 32-bits of Next Descriptor Address */
82 u32 des7; /* Upper 32-bits of Next Descriptor Address */
97 ((d)->des1 = ((d)->des1 & cpu_to_le32(0x03ffe000)) | (cpu_to_le32((s) & 0x1fff)))
110 struct dw_mci_slot *slot = s->private; in dw_mci_req_show()
117 spin_lock_bh(&slot->host->lock); in dw_mci_req_show()
118 mrq = slot->mrq; in dw_mci_req_show()
121 cmd = mrq->cmd; in dw_mci_req_show()
122 data = mrq->data; in dw_mci_req_show()
123 stop = mrq->stop; in dw_mci_req_show()
128 cmd->opcode, cmd->arg, cmd->flags, in dw_mci_req_show()
129 cmd->resp[0], cmd->resp[1], cmd->resp[2], in dw_mci_req_show()
130 cmd->resp[2], cmd->error); in dw_mci_req_show()
133 data->bytes_xfered, data->blocks, in dw_mci_req_show()
134 data->blksz, data->flags, data->error); in dw_mci_req_show()
138 stop->opcode, stop->arg, stop->flags, in dw_mci_req_show()
139 stop->resp[0], stop->resp[1], stop->resp[2], in dw_mci_req_show()
140 stop->resp[2], stop->error); in dw_mci_req_show()
143 spin_unlock_bh(&slot->host->lock); in dw_mci_req_show()
151 struct dw_mci *host = s->private; in dw_mci_regs_show()
153 pm_runtime_get_sync(host->dev); in dw_mci_regs_show()
158 seq_printf(s, "CTRL:\t0x%08x\n", mci_readl(host, CTRL)); in dw_mci_regs_show()
162 pm_runtime_put_autosuspend(host->dev); in dw_mci_regs_show()
170 struct mmc_host *mmc = slot->mmc; in dw_mci_init_debugfs()
171 struct dw_mci *host = slot->host; in dw_mci_init_debugfs()
174 root = mmc->debugfs_root; in dw_mci_init_debugfs()
180 debugfs_create_u32("state", S_IRUSR, root, &host->state); in dw_mci_init_debugfs()
182 &host->pending_events); in dw_mci_init_debugfs()
184 &host->completed_events); in dw_mci_init_debugfs()
186 fault_create_debugfs_attr("fail_data_crc", root, &host->fail_data_crc); in dw_mci_init_debugfs()
193 u32 ctrl; in dw_mci_ctrl_reset() local
195 ctrl = mci_readl(host, CTRL); in dw_mci_ctrl_reset()
196 ctrl |= reset; in dw_mci_ctrl_reset()
197 mci_writel(host, CTRL, ctrl); in dw_mci_ctrl_reset()
200 if (readl_poll_timeout_atomic(host->regs + SDMMC_CTRL, ctrl, in dw_mci_ctrl_reset()
201 !(ctrl & reset), in dw_mci_ctrl_reset()
203 dev_err(host->dev, in dw_mci_ctrl_reset()
204 "Timeout resetting block (ctrl reset %#x)\n", in dw_mci_ctrl_reset()
205 ctrl & reset); in dw_mci_ctrl_reset()
226 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_wait_while_busy()
230 dev_err(host->dev, "Busy; trying anyway\n"); in dw_mci_wait_while_busy()
236 struct dw_mci *host = slot->host; in mci_send_cmd()
244 if (readl_poll_timeout_atomic(host->regs + SDMMC_CMD, cmd_status, in mci_send_cmd()
247 dev_err(&slot->mmc->class_dev, in mci_send_cmd()
255 struct dw_mci *host = slot->host; in dw_mci_prepare_command()
258 cmd->error = -EINPROGRESS; in dw_mci_prepare_command()
259 cmdr = cmd->opcode; in dw_mci_prepare_command()
261 if (cmd->opcode == MMC_STOP_TRANSMISSION || in dw_mci_prepare_command()
262 cmd->opcode == MMC_GO_IDLE_STATE || in dw_mci_prepare_command()
263 cmd->opcode == MMC_GO_INACTIVE_STATE || in dw_mci_prepare_command()
264 (cmd->opcode == SD_IO_RW_DIRECT && in dw_mci_prepare_command()
265 ((cmd->arg >> 9) & 0x1FFFF) == SDIO_CCCR_ABORT)) in dw_mci_prepare_command()
267 else if (cmd->opcode != MMC_SEND_STATUS && cmd->data) in dw_mci_prepare_command()
270 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in dw_mci_prepare_command()
277 WARN_ON(slot->host->state != STATE_SENDING_CMD); in dw_mci_prepare_command()
278 slot->host->state = STATE_SENDING_CMD11; in dw_mci_prepare_command()
288 * ever called with a non-zero clock. That shouldn't happen in dw_mci_prepare_command()
292 clk_en_a &= ~(SDMMC_CLKEN_LOW_PWR << slot->id); in dw_mci_prepare_command()
298 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_prepare_command()
301 if (cmd->flags & MMC_RSP_136) in dw_mci_prepare_command()
305 if (cmd->flags & MMC_RSP_CRC) in dw_mci_prepare_command()
308 if (cmd->data) { in dw_mci_prepare_command()
310 if (cmd->data->flags & MMC_DATA_WRITE) in dw_mci_prepare_command()
314 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &slot->flags)) in dw_mci_prepare_command()
325 if (!cmd->data) in dw_mci_prep_stop_abort()
328 stop = &host->stop_abort; in dw_mci_prep_stop_abort()
329 cmdr = cmd->opcode; in dw_mci_prep_stop_abort()
338 stop->opcode = MMC_STOP_TRANSMISSION; in dw_mci_prep_stop_abort()
339 stop->arg = 0; in dw_mci_prep_stop_abort()
340 stop->flags = MMC_RSP_R1B | MMC_CMD_AC; in dw_mci_prep_stop_abort()
342 stop->opcode = SD_IO_RW_DIRECT; in dw_mci_prep_stop_abort()
343 stop->arg |= (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | in dw_mci_prep_stop_abort()
344 ((cmd->arg >> 28) & 0x7); in dw_mci_prep_stop_abort()
345 stop->flags = MMC_RSP_SPI_R5 | MMC_RSP_R5 | MMC_CMD_AC; in dw_mci_prep_stop_abort()
350 cmdr = stop->opcode | SDMMC_CMD_STOP | in dw_mci_prep_stop_abort()
353 if (!test_bit(DW_MMC_CARD_NO_USE_HOLD, &host->slot->flags)) in dw_mci_prep_stop_abort()
372 host->bus_hz); in dw_mci_set_cto()
390 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_cto()
391 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_set_cto()
392 mod_timer(&host->cto_timer, in dw_mci_set_cto()
394 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_cto()
400 host->cmd = cmd; in dw_mci_start_command()
401 dev_vdbg(host->dev, in dw_mci_start_command()
403 cmd->arg, cmd_flags); in dw_mci_start_command()
405 mci_writel(host, CMDARG, cmd->arg); in dw_mci_start_command()
418 struct mmc_command *stop = &host->stop_abort; in send_stop_abort()
420 dw_mci_start_command(host, stop, host->stop_cmdr); in send_stop_abort()
426 if (host->using_dma) { in dw_mci_stop_dma()
427 host->dma_ops->stop(host); in dw_mci_stop_dma()
428 host->dma_ops->cleanup(host); in dw_mci_stop_dma()
432 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_stop_dma()
437 struct mmc_data *data = host->data; in dw_mci_dma_cleanup()
439 if (data && data->host_cookie == COOKIE_MAPPED) { in dw_mci_dma_cleanup()
440 dma_unmap_sg(host->dev, in dw_mci_dma_cleanup()
441 data->sg, in dw_mci_dma_cleanup()
442 data->sg_len, in dw_mci_dma_cleanup()
444 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_dma_cleanup()
461 temp = mci_readl(host, CTRL); in dw_mci_idmac_stop_dma()
464 mci_writel(host, CTRL, temp); in dw_mci_idmac_stop_dma()
476 struct mmc_data *data = host->data; in dw_mci_dmac_complete_dma()
478 dev_vdbg(host->dev, "DMA complete\n"); in dw_mci_dmac_complete_dma()
480 if ((host->use_dma == TRANS_MODE_EDMAC) && in dw_mci_dmac_complete_dma()
481 data && (data->flags & MMC_DATA_READ)) in dw_mci_dmac_complete_dma()
483 dma_sync_sg_for_cpu(mmc_dev(host->slot->mmc), in dw_mci_dmac_complete_dma()
484 data->sg, in dw_mci_dmac_complete_dma()
485 data->sg_len, in dw_mci_dmac_complete_dma()
488 host->dma_ops->cleanup(host); in dw_mci_dmac_complete_dma()
495 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_dmac_complete_dma()
496 queue_work(system_bh_wq, &host->bh_work); in dw_mci_dmac_complete_dma()
504 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
507 host->ring_size = in dw_mci_idmac_init()
511 for (i = 0, p = host->sg_cpu; i < host->ring_size - 1; in dw_mci_idmac_init()
513 p->des6 = (host->sg_dma + in dw_mci_idmac_init()
517 p->des7 = (u64)(host->sg_dma + in dw_mci_idmac_init()
521 p->des0 = 0; in dw_mci_idmac_init()
522 p->des1 = 0; in dw_mci_idmac_init()
523 p->des2 = 0; in dw_mci_idmac_init()
524 p->des3 = 0; in dw_mci_idmac_init()
527 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
528 p->des6 = host->sg_dma & 0xffffffff; in dw_mci_idmac_init()
529 p->des7 = (u64)host->sg_dma >> 32; in dw_mci_idmac_init()
530 p->des0 = IDMAC_DES0_ER; in dw_mci_idmac_init()
535 host->ring_size = in dw_mci_idmac_init()
539 for (i = 0, p = host->sg_cpu; in dw_mci_idmac_init()
540 i < host->ring_size - 1; in dw_mci_idmac_init()
542 p->des3 = cpu_to_le32(host->sg_dma + in dw_mci_idmac_init()
544 p->des0 = 0; in dw_mci_idmac_init()
545 p->des1 = 0; in dw_mci_idmac_init()
548 /* Set the last descriptor as the end-of-ring descriptor */ in dw_mci_idmac_init()
549 p->des3 = cpu_to_le32(host->sg_dma); in dw_mci_idmac_init()
550 p->des0 = cpu_to_le32(IDMAC_DES0_ER); in dw_mci_idmac_init()
555 if (host->dma_64bit_address == 1) { in dw_mci_idmac_init()
556 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
562 mci_writel(host, DBADDRL, host->sg_dma & 0xffffffff); in dw_mci_idmac_init()
563 mci_writel(host, DBADDRU, (u64)host->sg_dma >> 32); in dw_mci_idmac_init()
566 /* Mask out interrupts - get Tx & Rx complete only */ in dw_mci_idmac_init()
572 mci_writel(host, DBADDR, host->sg_dma); in dw_mci_idmac_init()
587 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc64()
590 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc64()
592 u64 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc64()
598 length -= desc_len; in dw_mci_prepare_desc64()
606 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc64()
615 desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC | in dw_mci_prepare_desc64()
622 desc->des4 = mem_addr & 0xffffffff; in dw_mci_prepare_desc64()
623 desc->des5 = mem_addr >> 32; in dw_mci_prepare_desc64()
634 desc_first->des0 |= IDMAC_DES0_FD; in dw_mci_prepare_desc64()
637 desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC); in dw_mci_prepare_desc64()
638 desc_last->des0 |= IDMAC_DES0_LD; in dw_mci_prepare_desc64()
643 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc64()
644 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc64()
646 return -EINVAL; in dw_mci_prepare_desc64()
659 desc_first = desc_last = desc = host->sg_cpu; in dw_mci_prepare_desc32()
662 unsigned int length = sg_dma_len(&data->sg[i]); in dw_mci_prepare_desc32()
664 u32 mem_addr = sg_dma_address(&data->sg[i]); in dw_mci_prepare_desc32()
670 length -= desc_len; in dw_mci_prepare_desc32()
678 if (readl_poll_timeout_atomic(&desc->des0, val, in dw_mci_prepare_desc32()
688 desc->des0 = cpu_to_le32(IDMAC_DES0_OWN | in dw_mci_prepare_desc32()
696 desc->des2 = cpu_to_le32(mem_addr); in dw_mci_prepare_desc32()
707 desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD); in dw_mci_prepare_desc32()
710 desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | in dw_mci_prepare_desc32()
712 desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD); in dw_mci_prepare_desc32()
717 dev_dbg(host->dev, "descriptor is still owned by IDMAC.\n"); in dw_mci_prepare_desc32()
718 memset(host->sg_cpu, 0, DESC_RING_BUF_SZ); in dw_mci_prepare_desc32()
720 return -EINVAL; in dw_mci_prepare_desc32()
728 if (host->dma_64bit_address == 1) in dw_mci_idmac_start_dma()
729 ret = dw_mci_prepare_desc64(host, host->data, sg_len); in dw_mci_idmac_start_dma()
731 ret = dw_mci_prepare_desc32(host, host->data, sg_len); in dw_mci_idmac_start_dma()
744 temp = mci_readl(host, CTRL); in dw_mci_idmac_start_dma()
746 mci_writel(host, CTRL, temp); in dw_mci_idmac_start_dma()
773 dmaengine_terminate_async(host->dms->ch); in dw_mci_edmac_stop_dma()
781 struct scatterlist *sgl = host->data->sg; in dw_mci_edmac_start_dma()
783 u32 sg_elems = host->data->sg_len; in dw_mci_edmac_start_dma()
785 u32 fifo_offset = host->fifo_reg - host->regs; in dw_mci_edmac_start_dma()
790 cfg.dst_addr = host->phy_regs + fifo_offset; in dw_mci_edmac_start_dma()
800 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
805 ret = dmaengine_slave_config(host->dms->ch, &cfg); in dw_mci_edmac_start_dma()
807 dev_err(host->dev, "Failed to config edmac.\n"); in dw_mci_edmac_start_dma()
808 return -EBUSY; in dw_mci_edmac_start_dma()
811 desc = dmaengine_prep_slave_sg(host->dms->ch, sgl, in dw_mci_edmac_start_dma()
815 dev_err(host->dev, "Can't prepare slave sg.\n"); in dw_mci_edmac_start_dma()
816 return -EBUSY; in dw_mci_edmac_start_dma()
820 desc->callback = dw_mci_dmac_complete_dma; in dw_mci_edmac_start_dma()
821 desc->callback_param = (void *)host; in dw_mci_edmac_start_dma()
825 if (host->data->flags & MMC_DATA_WRITE) in dw_mci_edmac_start_dma()
826 dma_sync_sg_for_device(mmc_dev(host->slot->mmc), sgl, in dw_mci_edmac_start_dma()
829 dma_async_issue_pending(host->dms->ch); in dw_mci_edmac_start_dma()
837 host->dms = kzalloc(sizeof(struct dw_mci_dma_slave), GFP_KERNEL); in dw_mci_edmac_init()
838 if (!host->dms) in dw_mci_edmac_init()
839 return -ENOMEM; in dw_mci_edmac_init()
841 host->dms->ch = dma_request_chan(host->dev, "rx-tx"); in dw_mci_edmac_init()
842 if (IS_ERR(host->dms->ch)) { in dw_mci_edmac_init()
843 int ret = PTR_ERR(host->dms->ch); in dw_mci_edmac_init()
845 dev_err(host->dev, "Failed to get external DMA channel.\n"); in dw_mci_edmac_init()
846 kfree(host->dms); in dw_mci_edmac_init()
847 host->dms = NULL; in dw_mci_edmac_init()
856 if (host->dms) { in dw_mci_edmac_exit()
857 if (host->dms->ch) { in dw_mci_edmac_exit()
858 dma_release_channel(host->dms->ch); in dw_mci_edmac_exit()
859 host->dms->ch = NULL; in dw_mci_edmac_exit()
861 kfree(host->dms); in dw_mci_edmac_exit()
862 host->dms = NULL; in dw_mci_edmac_exit()
882 if (data->host_cookie == COOKIE_PRE_MAPPED) in dw_mci_pre_dma_transfer()
883 return data->sg_len; in dw_mci_pre_dma_transfer()
887 * non-word-aligned buffers or lengths. Also, we don't bother in dw_mci_pre_dma_transfer()
890 if (data->blocks * data->blksz < DW_MCI_DMA_THRESHOLD) in dw_mci_pre_dma_transfer()
891 return -EINVAL; in dw_mci_pre_dma_transfer()
893 if (data->blksz & 3) in dw_mci_pre_dma_transfer()
894 return -EINVAL; in dw_mci_pre_dma_transfer()
896 for_each_sg(data->sg, sg, data->sg_len, i) { in dw_mci_pre_dma_transfer()
897 if (sg->offset & 3 || sg->length & 3) in dw_mci_pre_dma_transfer()
898 return -EINVAL; in dw_mci_pre_dma_transfer()
901 sg_len = dma_map_sg(host->dev, in dw_mci_pre_dma_transfer()
902 data->sg, in dw_mci_pre_dma_transfer()
903 data->sg_len, in dw_mci_pre_dma_transfer()
906 return -EINVAL; in dw_mci_pre_dma_transfer()
908 data->host_cookie = cookie; in dw_mci_pre_dma_transfer()
917 struct mmc_data *data = mrq->data; in dw_mci_pre_req()
919 if (!slot->host->use_dma || !data) in dw_mci_pre_req()
923 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
925 if (dw_mci_pre_dma_transfer(slot->host, mrq->data, in dw_mci_pre_req()
927 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_pre_req()
935 struct mmc_data *data = mrq->data; in dw_mci_post_req()
937 if (!slot->host->use_dma || !data) in dw_mci_post_req()
940 if (data->host_cookie != COOKIE_UNMAPPED) in dw_mci_post_req()
941 dma_unmap_sg(slot->host->dev, in dw_mci_post_req()
942 data->sg, in dw_mci_post_req()
943 data->sg_len, in dw_mci_post_req()
945 data->host_cookie = COOKIE_UNMAPPED; in dw_mci_post_req()
952 struct dw_mci *host = slot->host; in dw_mci_get_cd()
956 if (((mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_get_cd()
960 if (!test_bit(DW_MMC_CARD_PRESENT, &slot->flags)) { in dw_mci_get_cd()
961 if (mmc->caps & MMC_CAP_NEEDS_POLL) { in dw_mci_get_cd()
962 dev_info(&mmc->class_dev, in dw_mci_get_cd()
965 dev_info(&mmc->class_dev, in dw_mci_get_cd()
966 "card is non-removable.\n"); in dw_mci_get_cd()
968 set_bit(DW_MMC_CARD_PRESENT, &slot->flags); in dw_mci_get_cd()
975 present = (mci_readl(slot->host, CDETECT) & (1 << slot->id)) in dw_mci_get_cd()
978 spin_lock_bh(&host->lock); in dw_mci_get_cd()
979 if (present && !test_and_set_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
980 dev_dbg(&mmc->class_dev, "card is present\n"); in dw_mci_get_cd()
982 !test_and_clear_bit(DW_MMC_CARD_PRESENT, &slot->flags)) in dw_mci_get_cd()
983 dev_dbg(&mmc->class_dev, "card is not present\n"); in dw_mci_get_cd()
984 spin_unlock_bh(&host->lock); in dw_mci_get_cd()
991 unsigned int blksz = data->blksz; in dw_mci_adjust_fifoth()
993 u32 fifo_width = 1 << host->data_shift; in dw_mci_adjust_fifoth()
996 int idx = ARRAY_SIZE(mszs) - 1; in dw_mci_adjust_fifoth()
999 if (!host->use_dma) in dw_mci_adjust_fifoth()
1002 tx_wmark = (host->fifo_depth) / 2; in dw_mci_adjust_fifoth()
1003 tx_wmark_invers = host->fifo_depth - tx_wmark; in dw_mci_adjust_fifoth()
1016 rx_wmark = mszs[idx] - 1; in dw_mci_adjust_fifoth()
1019 } while (--idx > 0); in dw_mci_adjust_fifoth()
1031 unsigned int blksz = data->blksz; in dw_mci_ctrl_thld()
1040 if (host->verid < DW_MMC_240A || in dw_mci_ctrl_thld()
1041 (host->verid < DW_MMC_280A && data->flags & MMC_DATA_WRITE)) in dw_mci_ctrl_thld()
1048 if (data->flags & MMC_DATA_WRITE && in dw_mci_ctrl_thld()
1049 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1052 if (data->flags & MMC_DATA_WRITE) in dw_mci_ctrl_thld()
1057 if (host->timing != MMC_TIMING_MMC_HS200 && in dw_mci_ctrl_thld()
1058 host->timing != MMC_TIMING_UHS_SDR104 && in dw_mci_ctrl_thld()
1059 host->timing != MMC_TIMING_MMC_HS400) in dw_mci_ctrl_thld()
1062 blksz_depth = blksz / (1 << host->data_shift); in dw_mci_ctrl_thld()
1063 fifo_depth = host->fifo_depth; in dw_mci_ctrl_thld()
1087 host->using_dma = 0; in dw_mci_submit_data_dma()
1090 if (!host->use_dma) in dw_mci_submit_data_dma()
1091 return -ENODEV; in dw_mci_submit_data_dma()
1095 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1099 host->using_dma = 1; in dw_mci_submit_data_dma()
1101 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_submit_data_dma()
1102 dev_vdbg(host->dev, in dw_mci_submit_data_dma()
1104 (unsigned long)host->sg_cpu, in dw_mci_submit_data_dma()
1105 (unsigned long)host->sg_dma, in dw_mci_submit_data_dma()
1113 if (host->prev_blksz != data->blksz) in dw_mci_submit_data_dma()
1117 temp = mci_readl(host, CTRL); in dw_mci_submit_data_dma()
1119 mci_writel(host, CTRL, temp); in dw_mci_submit_data_dma()
1122 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1126 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data_dma()
1128 if (host->dma_ops->start(host, sg_len)) { in dw_mci_submit_data_dma()
1129 host->dma_ops->stop(host); in dw_mci_submit_data_dma()
1131 dev_dbg(host->dev, in dw_mci_submit_data_dma()
1134 return -ENODEV; in dw_mci_submit_data_dma()
1146 data->error = -EINPROGRESS; in dw_mci_submit_data()
1148 WARN_ON(host->data); in dw_mci_submit_data()
1149 host->sg = NULL; in dw_mci_submit_data()
1150 host->data = data; in dw_mci_submit_data()
1152 if (data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1153 host->dir_status = DW_MCI_RECV_STATUS; in dw_mci_submit_data()
1155 host->dir_status = DW_MCI_SEND_STATUS; in dw_mci_submit_data()
1160 if (host->data->flags & MMC_DATA_READ) in dw_mci_submit_data()
1165 sg_miter_start(&host->sg_miter, data->sg, data->sg_len, flags); in dw_mci_submit_data()
1166 host->sg = data->sg; in dw_mci_submit_data()
1167 host->part_buf_start = 0; in dw_mci_submit_data()
1168 host->part_buf_count = 0; in dw_mci_submit_data()
1172 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_submit_data()
1176 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_submit_data()
1178 temp = mci_readl(host, CTRL); in dw_mci_submit_data()
1180 mci_writel(host, CTRL, temp); in dw_mci_submit_data()
1188 if (host->wm_aligned) in dw_mci_submit_data()
1191 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_submit_data()
1192 host->prev_blksz = 0; in dw_mci_submit_data()
1199 host->prev_blksz = data->blksz; in dw_mci_submit_data()
1205 struct dw_mci *host = slot->host; in dw_mci_setup_bus()
1206 unsigned int clock = slot->clock; in dw_mci_setup_bus()
1212 if (host->state == STATE_WAITING_CMD11_DONE) in dw_mci_setup_bus()
1215 slot->mmc->actual_clock = 0; in dw_mci_setup_bus()
1220 } else if (clock != host->current_speed || force_clkinit) { in dw_mci_setup_bus()
1221 div = host->bus_hz / clock; in dw_mci_setup_bus()
1222 if (host->bus_hz % clock && host->bus_hz > clock) in dw_mci_setup_bus()
1225 * over-clocking the card. in dw_mci_setup_bus()
1229 div = (host->bus_hz != clock) ? DIV_ROUND_UP(div, 2) : 0; in dw_mci_setup_bus()
1231 if ((clock != slot->__clk_old && in dw_mci_setup_bus()
1232 !test_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags)) || in dw_mci_setup_bus()
1236 dev_info(&slot->mmc->class_dev, in dw_mci_setup_bus()
1238 slot->id, host->bus_hz, clock, in dw_mci_setup_bus()
1239 div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1240 host->bus_hz, div); in dw_mci_setup_bus()
1246 if (slot->mmc->caps & MMC_CAP_NEEDS_POLL && in dw_mci_setup_bus()
1247 slot->mmc->f_min == clock) in dw_mci_setup_bus()
1248 set_bit(DW_MMC_CARD_NEEDS_POLL, &slot->flags); in dw_mci_setup_bus()
1265 clk_en_a = SDMMC_CLKEN_ENABLE << slot->id; in dw_mci_setup_bus()
1266 if (!test_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags)) in dw_mci_setup_bus()
1267 clk_en_a |= SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_setup_bus()
1274 slot->__clk_old = clock; in dw_mci_setup_bus()
1275 slot->mmc->actual_clock = div ? ((host->bus_hz / div) >> 1) : in dw_mci_setup_bus()
1276 host->bus_hz; in dw_mci_setup_bus()
1279 host->current_speed = clock; in dw_mci_setup_bus()
1282 mci_writel(host, CTYPE, (slot->ctype << slot->id)); in dw_mci_setup_bus()
1288 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_set_data_timeout()
1292 if (drv_data && drv_data->set_data_timeout) in dw_mci_set_data_timeout()
1293 return drv_data->set_data_timeout(host, timeout_ns); in dw_mci_set_data_timeout()
1299 tmp = DIV_ROUND_UP_ULL((u64)timeout_ns * host->bus_hz, NSEC_PER_SEC); in dw_mci_set_data_timeout()
1312 dev_dbg(host->dev, "timeout_ns: %u => TMOUT[31:8]: %#08x", in dw_mci_set_data_timeout()
1324 mrq = slot->mrq; in __dw_mci_start_request()
1326 host->mrq = mrq; in __dw_mci_start_request()
1328 host->pending_events = 0; in __dw_mci_start_request()
1329 host->completed_events = 0; in __dw_mci_start_request()
1330 host->cmd_status = 0; in __dw_mci_start_request()
1331 host->data_status = 0; in __dw_mci_start_request()
1332 host->dir_status = 0; in __dw_mci_start_request()
1334 data = cmd->data; in __dw_mci_start_request()
1336 dw_mci_set_data_timeout(host, data->timeout_ns); in __dw_mci_start_request()
1337 mci_writel(host, BYTCNT, data->blksz*data->blocks); in __dw_mci_start_request()
1338 mci_writel(host, BLKSIZ, data->blksz); in __dw_mci_start_request()
1341 cmdflags = dw_mci_prepare_command(slot->mmc, cmd); in __dw_mci_start_request()
1344 if (test_and_clear_bit(DW_MMC_CARD_NEED_INIT, &slot->flags)) in __dw_mci_start_request()
1354 if (cmd->opcode == SD_SWITCH_VOLTAGE) { in __dw_mci_start_request()
1367 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_start_request()
1368 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in __dw_mci_start_request()
1369 mod_timer(&host->cmd11_timer, in __dw_mci_start_request()
1371 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_start_request()
1374 host->stop_cmdr = dw_mci_prep_stop_abort(host, cmd); in __dw_mci_start_request()
1380 struct mmc_request *mrq = slot->mrq; in dw_mci_start_request()
1383 cmd = mrq->sbc ? mrq->sbc : mrq->cmd; in dw_mci_start_request()
1387 /* must be called with host->lock held */
1391 dev_vdbg(&slot->mmc->class_dev, "queue request: state=%d\n", in dw_mci_queue_request()
1392 host->state); in dw_mci_queue_request()
1394 slot->mrq = mrq; in dw_mci_queue_request()
1396 if (host->state == STATE_WAITING_CMD11_DONE) { in dw_mci_queue_request()
1397 dev_warn(&slot->mmc->class_dev, in dw_mci_queue_request()
1404 host->state = STATE_IDLE; in dw_mci_queue_request()
1407 if (host->state == STATE_IDLE) { in dw_mci_queue_request()
1408 host->state = STATE_SENDING_CMD; in dw_mci_queue_request()
1411 list_add_tail(&slot->queue_node, &host->queue); in dw_mci_queue_request()
1418 struct dw_mci *host = slot->host; in dw_mci_request()
1420 WARN_ON(slot->mrq); in dw_mci_request()
1429 mrq->cmd->error = -ENOMEDIUM; in dw_mci_request()
1434 spin_lock_bh(&host->lock); in dw_mci_request()
1438 spin_unlock_bh(&host->lock); in dw_mci_request()
1444 const struct dw_mci_drv_data *drv_data = slot->host->drv_data; in dw_mci_set_ios()
1448 switch (ios->bus_width) { in dw_mci_set_ios()
1450 slot->ctype = SDMMC_CTYPE_4BIT; in dw_mci_set_ios()
1453 slot->ctype = SDMMC_CTYPE_8BIT; in dw_mci_set_ios()
1457 slot->ctype = SDMMC_CTYPE_1BIT; in dw_mci_set_ios()
1460 regs = mci_readl(slot->host, UHS_REG); in dw_mci_set_ios()
1463 if (ios->timing == MMC_TIMING_MMC_DDR52 || in dw_mci_set_ios()
1464 ios->timing == MMC_TIMING_UHS_DDR50 || in dw_mci_set_ios()
1465 ios->timing == MMC_TIMING_MMC_HS400) in dw_mci_set_ios()
1466 regs |= ((0x1 << slot->id) << 16); in dw_mci_set_ios()
1468 regs &= ~((0x1 << slot->id) << 16); in dw_mci_set_ios()
1470 mci_writel(slot->host, UHS_REG, regs); in dw_mci_set_ios()
1471 slot->host->timing = ios->timing; in dw_mci_set_ios()
1474 * Use mirror of ios->clock to prevent race with mmc in dw_mci_set_ios()
1477 slot->clock = ios->clock; in dw_mci_set_ios()
1479 if (drv_data && drv_data->set_ios) in dw_mci_set_ios()
1480 drv_data->set_ios(slot->host, ios); in dw_mci_set_ios()
1482 switch (ios->power_mode) { in dw_mci_set_ios()
1484 if (!IS_ERR(mmc->supply.vmmc)) { in dw_mci_set_ios()
1485 ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, in dw_mci_set_ios()
1486 ios->vdd); in dw_mci_set_ios()
1488 dev_err(slot->host->dev, in dw_mci_set_ios()
1494 set_bit(DW_MMC_CARD_NEED_INIT, &slot->flags); in dw_mci_set_ios()
1495 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1496 regs |= (1 << slot->id); in dw_mci_set_ios()
1497 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1500 if (!slot->host->vqmmc_enabled) { in dw_mci_set_ios()
1501 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_set_ios()
1502 ret = regulator_enable(mmc->supply.vqmmc); in dw_mci_set_ios()
1504 dev_err(slot->host->dev, in dw_mci_set_ios()
1507 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1511 slot->host->vqmmc_enabled = true; in dw_mci_set_ios()
1515 dw_mci_ctrl_reset(slot->host, in dw_mci_set_ios()
1527 if (!IS_ERR(mmc->supply.vmmc)) in dw_mci_set_ios()
1528 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); in dw_mci_set_ios()
1530 if (!IS_ERR(mmc->supply.vqmmc) && slot->host->vqmmc_enabled) in dw_mci_set_ios()
1531 regulator_disable(mmc->supply.vqmmc); in dw_mci_set_ios()
1532 slot->host->vqmmc_enabled = false; in dw_mci_set_ios()
1534 regs = mci_readl(slot->host, PWREN); in dw_mci_set_ios()
1535 regs &= ~(1 << slot->id); in dw_mci_set_ios()
1536 mci_writel(slot->host, PWREN, regs); in dw_mci_set_ios()
1542 if (slot->host->state == STATE_WAITING_CMD11_DONE && ios->clock != 0) in dw_mci_set_ios()
1543 slot->host->state = STATE_IDLE; in dw_mci_set_ios()
1555 status = mci_readl(slot->host, STATUS); in dw_mci_card_busy()
1563 struct dw_mci *host = slot->host; in dw_mci_switch_voltage()
1564 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_switch_voltage()
1566 u32 v18 = SDMMC_UHS_18V << slot->id; in dw_mci_switch_voltage()
1569 if (drv_data && drv_data->switch_voltage) in dw_mci_switch_voltage()
1570 return drv_data->switch_voltage(mmc, ios); in dw_mci_switch_voltage()
1578 if (ios->signal_voltage == MMC_SIGNAL_VOLTAGE_330) in dw_mci_switch_voltage()
1583 if (!IS_ERR(mmc->supply.vqmmc)) { in dw_mci_switch_voltage()
1586 dev_dbg(&mmc->class_dev, in dw_mci_switch_voltage()
1587 "Regulator set error %d - %s V\n", in dw_mci_switch_voltage()
1608 mci_readl(slot->host, WRTPRT) & (1 << slot->id) ? 1 : 0; in dw_mci_get_ro()
1610 dev_dbg(&mmc->class_dev, "card is %s\n", in dw_mci_get_ro()
1611 read_only ? "read-only" : "read-write"); in dw_mci_get_ro()
1619 struct dw_mci *host = slot->host; in dw_mci_hw_reset()
1620 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_hw_reset()
1623 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_hw_reset()
1630 if (drv_data && drv_data->hw_reset) { in dw_mci_hw_reset()
1631 drv_data->hw_reset(host); in dw_mci_hw_reset()
1642 reset &= ~(SDMMC_RST_HWACTIVE << slot->id); in dw_mci_hw_reset()
1645 reset |= SDMMC_RST_HWACTIVE << slot->id; in dw_mci_hw_reset()
1652 struct dw_mci *host = slot->host; in dw_mci_prepare_sdio_irq()
1653 const u32 clken_low_pwr = SDMMC_CLKEN_LOW_PWR << slot->id; in dw_mci_prepare_sdio_irq()
1665 set_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_prepare_sdio_irq()
1668 clear_bit(DW_MMC_CARD_NO_LOW_PWR, &slot->flags); in dw_mci_prepare_sdio_irq()
1681 struct dw_mci *host = slot->host; in __dw_mci_enable_sdio_irq()
1685 spin_lock_irqsave(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1690 int_mask |= SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1692 int_mask &= ~SDMMC_INT_SDIO(slot->sdio_id); in __dw_mci_enable_sdio_irq()
1695 spin_unlock_irqrestore(&host->irq_lock, irqflags); in __dw_mci_enable_sdio_irq()
1701 struct dw_mci *host = slot->host; in dw_mci_enable_sdio_irq()
1708 pm_runtime_get_noresume(host->dev); in dw_mci_enable_sdio_irq()
1710 pm_runtime_put_noidle(host->dev); in dw_mci_enable_sdio_irq()
1723 struct dw_mci *host = slot->host; in dw_mci_execute_tuning()
1724 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_execute_tuning()
1725 int err = -EINVAL; in dw_mci_execute_tuning()
1727 if (drv_data && drv_data->execute_tuning) in dw_mci_execute_tuning()
1728 err = drv_data->execute_tuning(slot, opcode); in dw_mci_execute_tuning()
1736 struct dw_mci *host = slot->host; in dw_mci_prepare_hs400_tuning()
1737 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_prepare_hs400_tuning()
1739 if (drv_data && drv_data->prepare_hs400_tuning) in dw_mci_prepare_hs400_tuning()
1740 return drv_data->prepare_hs400_tuning(host, ios); in dw_mci_prepare_hs400_tuning()
1753 * the scatter-gather pointer to NULL. in dw_mci_reset()
1755 if (host->sg) { in dw_mci_reset()
1756 sg_miter_stop(&host->sg_miter); in dw_mci_reset()
1757 host->sg = NULL; in dw_mci_reset()
1760 if (host->use_dma) in dw_mci_reset()
1770 if (!host->use_dma) { in dw_mci_reset()
1776 if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS, in dw_mci_reset()
1780 dev_err(host->dev, in dw_mci_reset()
1791 if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) { in dw_mci_reset()
1792 dev_err(host->dev, in dw_mci_reset()
1799 if (host->use_dma == TRANS_MODE_IDMAC) in dw_mci_reset()
1806 /* After a CTRL reset we need to have CIU set clock registers */ in dw_mci_reset()
1807 mci_send_cmd(host->slot, SDMMC_CMD_UPD_CLK, 0); in dw_mci_reset()
1834 spin_lock_irqsave(&host->irq_lock, flags); in dw_mci_fault_timer()
1840 if (!host->data_status) { in dw_mci_fault_timer()
1841 host->data_status = SDMMC_INT_DCRC; in dw_mci_fault_timer()
1842 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_fault_timer()
1843 queue_work(system_bh_wq, &host->bh_work); in dw_mci_fault_timer()
1846 spin_unlock_irqrestore(&host->irq_lock, flags); in dw_mci_fault_timer()
1853 struct mmc_data *data = host->data; in dw_mci_start_fault_timer()
1855 if (!data || data->blocks <= 1) in dw_mci_start_fault_timer()
1858 if (!should_fail(&host->fail_data_crc, 1)) in dw_mci_start_fault_timer()
1864 hrtimer_start(&host->fault_timer, in dw_mci_start_fault_timer()
1871 hrtimer_cancel(&host->fault_timer); in dw_mci_stop_fault_timer()
1876 host->fail_data_crc = (struct fault_attr) FAULT_ATTR_INITIALIZER; in dw_mci_init_fault()
1878 hrtimer_setup(&host->fault_timer, dw_mci_fault_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); in dw_mci_init_fault()
1895 __releases(&host->lock) in dw_mci_request_end()
1896 __acquires(&host->lock) in dw_mci_request_end()
1899 struct mmc_host *prev_mmc = host->slot->mmc; in dw_mci_request_end()
1901 WARN_ON(host->cmd || host->data); in dw_mci_request_end()
1903 host->slot->mrq = NULL; in dw_mci_request_end()
1904 host->mrq = NULL; in dw_mci_request_end()
1905 if (!list_empty(&host->queue)) { in dw_mci_request_end()
1906 slot = list_entry(host->queue.next, in dw_mci_request_end()
1908 list_del(&slot->queue_node); in dw_mci_request_end()
1909 dev_vdbg(host->dev, "list not empty: %s is next\n", in dw_mci_request_end()
1910 mmc_hostname(slot->mmc)); in dw_mci_request_end()
1911 host->state = STATE_SENDING_CMD; in dw_mci_request_end()
1914 dev_vdbg(host->dev, "list empty\n"); in dw_mci_request_end()
1916 if (host->state == STATE_SENDING_CMD11) in dw_mci_request_end()
1917 host->state = STATE_WAITING_CMD11_DONE; in dw_mci_request_end()
1919 host->state = STATE_IDLE; in dw_mci_request_end()
1922 spin_unlock(&host->lock); in dw_mci_request_end()
1924 spin_lock(&host->lock); in dw_mci_request_end()
1929 u32 status = host->cmd_status; in dw_mci_command_complete()
1931 host->cmd_status = 0; in dw_mci_command_complete()
1934 if (cmd->flags & MMC_RSP_PRESENT) { in dw_mci_command_complete()
1935 if (cmd->flags & MMC_RSP_136) { in dw_mci_command_complete()
1936 cmd->resp[3] = mci_readl(host, RESP0); in dw_mci_command_complete()
1937 cmd->resp[2] = mci_readl(host, RESP1); in dw_mci_command_complete()
1938 cmd->resp[1] = mci_readl(host, RESP2); in dw_mci_command_complete()
1939 cmd->resp[0] = mci_readl(host, RESP3); in dw_mci_command_complete()
1941 cmd->resp[0] = mci_readl(host, RESP0); in dw_mci_command_complete()
1942 cmd->resp[1] = 0; in dw_mci_command_complete()
1943 cmd->resp[2] = 0; in dw_mci_command_complete()
1944 cmd->resp[3] = 0; in dw_mci_command_complete()
1949 cmd->error = -ETIMEDOUT; in dw_mci_command_complete()
1950 else if ((cmd->flags & MMC_RSP_CRC) && (status & SDMMC_INT_RCRC)) in dw_mci_command_complete()
1951 cmd->error = -EILSEQ; in dw_mci_command_complete()
1953 cmd->error = -EIO; in dw_mci_command_complete()
1955 cmd->error = 0; in dw_mci_command_complete()
1957 return cmd->error; in dw_mci_command_complete()
1962 u32 status = host->data_status; in dw_mci_data_complete()
1966 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1968 data->error = -EILSEQ; in dw_mci_data_complete()
1970 if (host->dir_status == in dw_mci_data_complete()
1977 data->bytes_xfered = 0; in dw_mci_data_complete()
1978 data->error = -ETIMEDOUT; in dw_mci_data_complete()
1979 } else if (host->dir_status == in dw_mci_data_complete()
1981 data->error = -EILSEQ; in dw_mci_data_complete()
1985 data->error = -EILSEQ; in dw_mci_data_complete()
1988 dev_dbg(host->dev, "data error, status 0x%08x\n", status); in dw_mci_data_complete()
1996 data->bytes_xfered = data->blocks * data->blksz; in dw_mci_data_complete()
1997 data->error = 0; in dw_mci_data_complete()
2000 return data->error; in dw_mci_data_complete()
2005 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_set_drto()
2011 if (drv_data && drv_data->get_drto_clks) in dw_mci_set_drto()
2012 drto_clks = drv_data->get_drto_clks(host); in dw_mci_set_drto()
2020 host->bus_hz); in dw_mci_set_drto()
2022 dev_dbg(host->dev, "drto_ms: %u\n", drto_ms); in dw_mci_set_drto()
2027 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_set_drto()
2028 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_set_drto()
2029 mod_timer(&host->dto_timer, in dw_mci_set_drto()
2031 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_set_drto()
2036 if (!test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_cmd_complete()
2046 WARN_ON(timer_delete_sync(&host->cto_timer)); in dw_mci_clear_pending_cmd_complete()
2047 clear_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_clear_pending_cmd_complete()
2054 if (!test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) in dw_mci_clear_pending_data_complete()
2058 WARN_ON(timer_delete_sync(&host->dto_timer)); in dw_mci_clear_pending_data_complete()
2059 clear_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_clear_pending_data_complete()
2074 spin_lock(&host->lock); in dw_mci_work_func()
2076 state = host->state; in dw_mci_work_func()
2077 data = host->data; in dw_mci_work_func()
2078 mrq = host->mrq; in dw_mci_work_func()
2093 cmd = host->cmd; in dw_mci_work_func()
2094 host->cmd = NULL; in dw_mci_work_func()
2095 set_bit(EVENT_CMD_COMPLETE, &host->completed_events); in dw_mci_work_func()
2097 if (cmd == mrq->sbc && !err) { in dw_mci_work_func()
2098 __dw_mci_start_request(host, host->slot, in dw_mci_work_func()
2099 mrq->cmd); in dw_mci_work_func()
2103 if (cmd->data && err) { in dw_mci_work_func()
2125 if (err != -ETIMEDOUT && in dw_mci_work_func()
2126 host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_work_func()
2137 if (!cmd->data || err) { in dw_mci_work_func()
2155 &host->pending_events)) { in dw_mci_work_func()
2156 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_work_func()
2165 &host->pending_events)) { in dw_mci_work_func()
2167 * If all data-related interrupts don't come in dw_mci_work_func()
2170 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_work_func()
2175 set_bit(EVENT_XFER_COMPLETE, &host->completed_events); in dw_mci_work_func()
2191 &host->pending_events)) { in dw_mci_work_func()
2192 if (!(host->data_status & (SDMMC_INT_DRTO | in dw_mci_work_func()
2210 if (host->dir_status == DW_MCI_RECV_STATUS) in dw_mci_work_func()
2216 host->data = NULL; in dw_mci_work_func()
2217 set_bit(EVENT_DATA_COMPLETE, &host->completed_events); in dw_mci_work_func()
2221 if (!data->stop || mrq->sbc) { in dw_mci_work_func()
2222 if (mrq->sbc && data->stop) in dw_mci_work_func()
2223 data->stop->error = 0; in dw_mci_work_func()
2228 /* stop command for open-ended transfer*/ in dw_mci_work_func()
2229 if (data->stop) in dw_mci_work_func()
2242 &host->pending_events)) { in dw_mci_work_func()
2243 host->cmd = NULL; in dw_mci_work_func()
2250 * If err has non-zero, in dw_mci_work_func()
2251 * stop-abort command has been already issued. in dw_mci_work_func()
2262 if (mrq->cmd->error && mrq->data) in dw_mci_work_func()
2266 host->cmd = NULL; in dw_mci_work_func()
2267 host->data = NULL; in dw_mci_work_func()
2269 if (!mrq->sbc && mrq->stop) in dw_mci_work_func()
2270 dw_mci_command_complete(host, mrq->stop); in dw_mci_work_func()
2272 host->cmd_status = 0; in dw_mci_work_func()
2279 &host->pending_events)) in dw_mci_work_func()
2287 host->state = state; in dw_mci_work_func()
2289 spin_unlock(&host->lock); in dw_mci_work_func()
2296 memcpy((void *)&host->part_buf, buf, cnt); in dw_mci_set_part_bytes()
2297 host->part_buf_count = cnt; in dw_mci_set_part_bytes()
2303 cnt = min(cnt, (1 << host->data_shift) - host->part_buf_count); in dw_mci_push_part_bytes()
2304 memcpy((void *)&host->part_buf + host->part_buf_count, buf, cnt); in dw_mci_push_part_bytes()
2305 host->part_buf_count += cnt; in dw_mci_push_part_bytes()
2312 cnt = min_t(int, cnt, host->part_buf_count); in dw_mci_pull_part_bytes()
2314 memcpy(buf, (void *)&host->part_buf + host->part_buf_start, in dw_mci_pull_part_bytes()
2316 host->part_buf_count -= cnt; in dw_mci_pull_part_bytes()
2317 host->part_buf_start += cnt; in dw_mci_pull_part_bytes()
2325 memcpy(buf, &host->part_buf, cnt); in dw_mci_pull_final_bytes()
2326 host->part_buf_start = cnt; in dw_mci_pull_final_bytes()
2327 host->part_buf_count = (1 << host->data_shift) - cnt; in dw_mci_pull_final_bytes()
2332 struct mmc_data *data = host->data; in dw_mci_push_data16()
2336 if (unlikely(host->part_buf_count)) { in dw_mci_push_data16()
2340 cnt -= len; in dw_mci_push_data16()
2341 if (host->part_buf_count == 2) { in dw_mci_push_data16()
2342 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2343 host->part_buf_count = 0; in dw_mci_push_data16()
2350 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_push_data16()
2356 cnt -= len; in dw_mci_push_data16()
2359 mci_fifo_writew(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data16()
2366 for (; cnt >= 2; cnt -= 2) in dw_mci_push_data16()
2367 mci_fifo_writew(host->fifo_reg, *pdata++); in dw_mci_push_data16()
2374 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data16()
2375 (data->blksz * data->blocks)) in dw_mci_push_data16()
2376 mci_fifo_writew(host->fifo_reg, host->part_buf16); in dw_mci_push_data16()
2387 int len = min(cnt & -2, (int)sizeof(aligned_buf)); in dw_mci_pull_data16()
2392 aligned_buf[i] = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2396 cnt -= len; in dw_mci_pull_data16()
2403 for (; cnt >= 2; cnt -= 2) in dw_mci_pull_data16()
2404 *pdata++ = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2408 host->part_buf16 = mci_fifo_readw(host->fifo_reg); in dw_mci_pull_data16()
2415 struct mmc_data *data = host->data; in dw_mci_push_data32()
2419 if (unlikely(host->part_buf_count)) { in dw_mci_push_data32()
2423 cnt -= len; in dw_mci_push_data32()
2424 if (host->part_buf_count == 4) { in dw_mci_push_data32()
2425 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2426 host->part_buf_count = 0; in dw_mci_push_data32()
2433 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_push_data32()
2439 cnt -= len; in dw_mci_push_data32()
2442 mci_fifo_writel(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data32()
2449 for (; cnt >= 4; cnt -= 4) in dw_mci_push_data32()
2450 mci_fifo_writel(host->fifo_reg, *pdata++); in dw_mci_push_data32()
2457 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data32()
2458 (data->blksz * data->blocks)) in dw_mci_push_data32()
2459 mci_fifo_writel(host->fifo_reg, host->part_buf32); in dw_mci_push_data32()
2470 int len = min(cnt & -4, (int)sizeof(aligned_buf)); in dw_mci_pull_data32()
2475 aligned_buf[i] = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2479 cnt -= len; in dw_mci_pull_data32()
2486 for (; cnt >= 4; cnt -= 4) in dw_mci_pull_data32()
2487 *pdata++ = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2491 host->part_buf32 = mci_fifo_readl(host->fifo_reg); in dw_mci_pull_data32()
2498 struct mmc_data *data = host->data; in dw_mci_push_data64()
2502 if (unlikely(host->part_buf_count)) { in dw_mci_push_data64()
2506 cnt -= len; in dw_mci_push_data64()
2508 if (host->part_buf_count == 8) { in dw_mci_push_data64()
2509 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2510 host->part_buf_count = 0; in dw_mci_push_data64()
2517 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_push_data64()
2523 cnt -= len; in dw_mci_push_data64()
2526 mci_fifo_writeq(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data64()
2533 for (; cnt >= 8; cnt -= 8) in dw_mci_push_data64()
2534 mci_fifo_writeq(host->fifo_reg, *pdata++); in dw_mci_push_data64()
2541 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data64()
2542 (data->blksz * data->blocks)) in dw_mci_push_data64()
2543 mci_fifo_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64()
2554 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_pull_data64()
2559 aligned_buf[i] = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2564 cnt -= len; in dw_mci_pull_data64()
2571 for (; cnt >= 8; cnt -= 8) in dw_mci_pull_data64()
2572 *pdata++ = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2576 host->part_buf = mci_fifo_readq(host->fifo_reg); in dw_mci_pull_data64()
2583 struct mmc_data *data = host->data; in dw_mci_push_data64_32()
2587 if (unlikely(host->part_buf_count)) { in dw_mci_push_data64_32()
2591 cnt -= len; in dw_mci_push_data64_32()
2593 if (host->part_buf_count == 8) { in dw_mci_push_data64_32()
2594 mci_fifo_l_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64_32()
2595 host->part_buf_count = 0; in dw_mci_push_data64_32()
2602 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_push_data64_32()
2608 cnt -= len; in dw_mci_push_data64_32()
2611 mci_fifo_l_writeq(host->fifo_reg, aligned_buf[i]); in dw_mci_push_data64_32()
2618 for (; cnt >= 8; cnt -= 8) in dw_mci_push_data64_32()
2619 mci_fifo_l_writeq(host->fifo_reg, *pdata++); in dw_mci_push_data64_32()
2626 if ((data->bytes_xfered + init_cnt) == in dw_mci_push_data64_32()
2627 (data->blksz * data->blocks)) in dw_mci_push_data64_32()
2628 mci_fifo_l_writeq(host->fifo_reg, host->part_buf); in dw_mci_push_data64_32()
2639 int len = min(cnt & -8, (int)sizeof(aligned_buf)); in dw_mci_pull_data64_32()
2644 aligned_buf[i] = mci_fifo_l_readq(host->fifo_reg); in dw_mci_pull_data64_32()
2649 cnt -= len; in dw_mci_pull_data64_32()
2656 for (; cnt >= 8; cnt -= 8) in dw_mci_pull_data64_32()
2657 *pdata++ = mci_fifo_l_readq(host->fifo_reg); in dw_mci_pull_data64_32()
2661 host->part_buf = mci_fifo_l_readq(host->fifo_reg); in dw_mci_pull_data64_32()
2675 cnt -= len; in dw_mci_pull_data()
2678 host->pull_data(host, buf, cnt); in dw_mci_pull_data()
2683 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_read_data_pio()
2686 struct mmc_data *data = host->data; in dw_mci_read_data_pio()
2687 int shift = host->data_shift; in dw_mci_read_data_pio()
2696 host->sg = sg_miter->piter.sg; in dw_mci_read_data_pio()
2697 buf = sg_miter->addr; in dw_mci_read_data_pio()
2698 remain = sg_miter->length; in dw_mci_read_data_pio()
2703 << shift) + host->part_buf_count; in dw_mci_read_data_pio()
2708 data->bytes_xfered += len; in dw_mci_read_data_pio()
2710 remain -= len; in dw_mci_read_data_pio()
2713 sg_miter->consumed = offset; in dw_mci_read_data_pio()
2723 sg_miter->consumed = 0; in dw_mci_read_data_pio()
2730 host->sg = NULL; in dw_mci_read_data_pio()
2732 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_read_data_pio()
2737 struct sg_mapping_iter *sg_miter = &host->sg_miter; in dw_mci_write_data_pio()
2740 struct mmc_data *data = host->data; in dw_mci_write_data_pio()
2741 int shift = host->data_shift; in dw_mci_write_data_pio()
2744 unsigned int fifo_depth = host->fifo_depth; in dw_mci_write_data_pio()
2751 host->sg = sg_miter->piter.sg; in dw_mci_write_data_pio()
2752 buf = sg_miter->addr; in dw_mci_write_data_pio()
2753 remain = sg_miter->length; in dw_mci_write_data_pio()
2757 fcnt = ((fifo_depth - in dw_mci_write_data_pio()
2759 << shift) - host->part_buf_count; in dw_mci_write_data_pio()
2763 host->push_data(host, (void *)(buf + offset), len); in dw_mci_write_data_pio()
2764 data->bytes_xfered += len; in dw_mci_write_data_pio()
2766 remain -= len; in dw_mci_write_data_pio()
2769 sg_miter->consumed = offset; in dw_mci_write_data_pio()
2777 sg_miter->consumed = 0; in dw_mci_write_data_pio()
2784 host->sg = NULL; in dw_mci_write_data_pio()
2786 set_bit(EVENT_XFER_COMPLETE, &host->pending_events); in dw_mci_write_data_pio()
2791 timer_delete(&host->cto_timer); in dw_mci_cmd_interrupt()
2793 if (!host->cmd_status) in dw_mci_cmd_interrupt()
2794 host->cmd_status = status; in dw_mci_cmd_interrupt()
2798 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd_interrupt()
2799 queue_work(system_bh_wq, &host->bh_work); in dw_mci_cmd_interrupt()
2806 struct dw_mci_slot *slot = host->slot; in dw_mci_handle_cd()
2808 mmc_detect_change(slot->mmc, in dw_mci_handle_cd()
2809 msecs_to_jiffies(host->pdata->detect_delay_ms)); in dw_mci_handle_cd()
2816 struct dw_mci_slot *slot = host->slot; in dw_mci_interrupt()
2818 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_interrupt()
2822 if ((host->state == STATE_SENDING_CMD11) && in dw_mci_interrupt()
2831 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2833 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2835 timer_delete(&host->cmd11_timer); in dw_mci_interrupt()
2839 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2841 timer_delete(&host->cto_timer); in dw_mci_interrupt()
2843 host->cmd_status = pending; in dw_mci_interrupt()
2845 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2847 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2851 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2853 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) in dw_mci_interrupt()
2854 timer_delete(&host->dto_timer); in dw_mci_interrupt()
2858 host->data_status = pending; in dw_mci_interrupt()
2860 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_interrupt()
2862 if (host->quirks & DW_MMC_QUIRK_EXTENDED_TMOUT) in dw_mci_interrupt()
2865 &host->pending_events); in dw_mci_interrupt()
2867 queue_work(system_bh_wq, &host->bh_work); in dw_mci_interrupt()
2869 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2873 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2875 timer_delete(&host->dto_timer); in dw_mci_interrupt()
2878 if (!host->data_status) in dw_mci_interrupt()
2879 host->data_status = pending; in dw_mci_interrupt()
2881 if (host->dir_status == DW_MCI_RECV_STATUS) { in dw_mci_interrupt()
2882 if (host->sg != NULL) in dw_mci_interrupt()
2885 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_interrupt()
2886 queue_work(system_bh_wq, &host->bh_work); in dw_mci_interrupt()
2888 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2893 if (host->dir_status == DW_MCI_RECV_STATUS && host->sg) in dw_mci_interrupt()
2899 if (host->dir_status == DW_MCI_SEND_STATUS && host->sg) in dw_mci_interrupt()
2904 spin_lock(&host->irq_lock); in dw_mci_interrupt()
2909 spin_unlock(&host->irq_lock); in dw_mci_interrupt()
2917 if (pending & SDMMC_INT_SDIO(slot->sdio_id)) { in dw_mci_interrupt()
2919 SDMMC_INT_SDIO(slot->sdio_id)); in dw_mci_interrupt()
2921 sdio_signal_irq(slot->mmc); in dw_mci_interrupt()
2926 if (host->use_dma != TRANS_MODE_IDMAC) in dw_mci_interrupt()
2930 if (host->dma_64bit_address == 1) { in dw_mci_interrupt()
2936 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2937 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2945 if (!test_bit(EVENT_DATA_ERROR, &host->pending_events)) in dw_mci_interrupt()
2946 host->dma_ops->complete((void *)host); in dw_mci_interrupt()
2955 struct dw_mci *host = slot->host; in dw_mci_init_slot_caps()
2956 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_init_slot_caps()
2957 struct mmc_host *mmc = slot->mmc; in dw_mci_init_slot_caps()
2960 if (host->pdata->caps) in dw_mci_init_slot_caps()
2961 mmc->caps = host->pdata->caps; in dw_mci_init_slot_caps()
2963 if (host->pdata->pm_caps) in dw_mci_init_slot_caps()
2964 mmc->pm_caps = host->pdata->pm_caps; in dw_mci_init_slot_caps()
2967 mmc->caps |= drv_data->common_caps; in dw_mci_init_slot_caps()
2969 if (host->dev->of_node) { in dw_mci_init_slot_caps()
2970 ctrl_id = of_alias_get_id(host->dev->of_node, "mshc"); in dw_mci_init_slot_caps()
2974 ctrl_id = to_platform_device(host->dev)->id; in dw_mci_init_slot_caps()
2977 if (drv_data && drv_data->caps) { in dw_mci_init_slot_caps()
2978 if (ctrl_id >= drv_data->num_caps) { in dw_mci_init_slot_caps()
2979 dev_err(host->dev, "invalid controller id %d\n", in dw_mci_init_slot_caps()
2981 return -EINVAL; in dw_mci_init_slot_caps()
2983 mmc->caps |= drv_data->caps[ctrl_id]; in dw_mci_init_slot_caps()
2986 if (host->pdata->caps2) in dw_mci_init_slot_caps()
2987 mmc->caps2 = host->pdata->caps2; in dw_mci_init_slot_caps()
2990 if (host->minimum_speed) in dw_mci_init_slot_caps()
2991 mmc->f_min = host->minimum_speed; in dw_mci_init_slot_caps()
2993 mmc->f_min = DW_MCI_FREQ_MIN; in dw_mci_init_slot_caps()
2995 if (!mmc->f_max) in dw_mci_init_slot_caps()
2996 mmc->f_max = DW_MCI_FREQ_MAX; in dw_mci_init_slot_caps()
2999 if (mmc->caps & MMC_CAP_SDIO_IRQ) in dw_mci_init_slot_caps()
3000 mmc->caps2 |= MMC_CAP2_SDIO_IRQ_NOTHREAD; in dw_mci_init_slot_caps()
3011 mmc = mmc_alloc_host(sizeof(struct dw_mci_slot), host->dev); in dw_mci_init_slot()
3013 return -ENOMEM; in dw_mci_init_slot()
3016 slot->id = 0; in dw_mci_init_slot()
3017 slot->sdio_id = host->sdio_id0 + slot->id; in dw_mci_init_slot()
3018 slot->mmc = mmc; in dw_mci_init_slot()
3019 slot->host = host; in dw_mci_init_slot()
3020 host->slot = slot; in dw_mci_init_slot()
3022 mmc->ops = &dw_mci_ops; in dw_mci_init_slot()
3029 if (!mmc->ocr_avail) in dw_mci_init_slot()
3030 mmc->ocr_avail = MMC_VDD_32_33 | MMC_VDD_33_34; in dw_mci_init_slot()
3041 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_slot()
3042 mmc->max_segs = host->ring_size; in dw_mci_init_slot()
3043 mmc->max_blk_size = 65535; in dw_mci_init_slot()
3044 mmc->max_seg_size = 0x1000; in dw_mci_init_slot()
3045 mmc->max_req_size = mmc->max_seg_size * host->ring_size; in dw_mci_init_slot()
3046 mmc->max_blk_count = mmc->max_req_size / 512; in dw_mci_init_slot()
3047 } else if (host->use_dma == TRANS_MODE_EDMAC) { in dw_mci_init_slot()
3048 mmc->max_segs = 64; in dw_mci_init_slot()
3049 mmc->max_blk_size = 65535; in dw_mci_init_slot()
3050 mmc->max_blk_count = 65535; in dw_mci_init_slot()
3051 mmc->max_req_size = in dw_mci_init_slot()
3052 mmc->max_blk_size * mmc->max_blk_count; in dw_mci_init_slot()
3053 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
3056 mmc->max_segs = 64; in dw_mci_init_slot()
3057 mmc->max_blk_size = 65535; /* BLKSIZ is 16 bits */ in dw_mci_init_slot()
3058 mmc->max_blk_count = 512; in dw_mci_init_slot()
3059 mmc->max_req_size = mmc->max_blk_size * in dw_mci_init_slot()
3060 mmc->max_blk_count; in dw_mci_init_slot()
3061 mmc->max_seg_size = mmc->max_req_size; in dw_mci_init_slot()
3084 mmc_remove_host(slot->mmc); in dw_mci_cleanup_slot()
3085 slot->host->slot = NULL; in dw_mci_cleanup_slot()
3086 mmc_free_host(slot->mmc); in dw_mci_cleanup_slot()
3092 struct device *dev = host->dev; in dw_mci_init_dma()
3097 * 2b'00: No DMA Interface -> Actually means using Internal DMA block in dw_mci_init_dma()
3098 * 2b'01: DesignWare DMA Interface -> Synopsys DW-DMA block in dw_mci_init_dma()
3099 * 2b'10: Generic DMA Interface -> non-Synopsys generic DMA block in dw_mci_init_dma()
3100 * 2b'11: Non DW DMA Interface -> pio only in dw_mci_init_dma()
3105 host->use_dma = SDMMC_GET_TRANS_MODE(mci_readl(host, HCON)); in dw_mci_init_dma()
3106 if (host->use_dma == DMA_INTERFACE_IDMA) { in dw_mci_init_dma()
3107 host->use_dma = TRANS_MODE_IDMAC; in dw_mci_init_dma()
3108 } else if (host->use_dma == DMA_INTERFACE_DWDMA || in dw_mci_init_dma()
3109 host->use_dma == DMA_INTERFACE_GDMA) { in dw_mci_init_dma()
3110 host->use_dma = TRANS_MODE_EDMAC; in dw_mci_init_dma()
3116 if (host->use_dma == TRANS_MODE_IDMAC) { in dw_mci_init_dma()
3124 /* host supports IDMAC in 64-bit address mode */ in dw_mci_init_dma()
3125 host->dma_64bit_address = 1; in dw_mci_init_dma()
3126 dev_info(host->dev, in dw_mci_init_dma()
3127 "IDMAC supports 64-bit address mode.\n"); in dw_mci_init_dma()
3128 if (!dma_set_mask(host->dev, DMA_BIT_MASK(64))) in dw_mci_init_dma()
3129 dma_set_coherent_mask(host->dev, in dw_mci_init_dma()
3132 /* host supports IDMAC in 32-bit address mode */ in dw_mci_init_dma()
3133 host->dma_64bit_address = 0; in dw_mci_init_dma()
3134 dev_info(host->dev, in dw_mci_init_dma()
3135 "IDMAC supports 32-bit address mode.\n"); in dw_mci_init_dma()
3139 host->sg_cpu = dmam_alloc_coherent(host->dev, in dw_mci_init_dma()
3141 &host->sg_dma, GFP_KERNEL); in dw_mci_init_dma()
3142 if (!host->sg_cpu) { in dw_mci_init_dma()
3143 dev_err(host->dev, in dw_mci_init_dma()
3149 host->dma_ops = &dw_mci_idmac_ops; in dw_mci_init_dma()
3150 dev_info(host->dev, "Using internal DMA controller.\n"); in dw_mci_init_dma()
3153 if ((device_property_string_array_count(dev, "dma-names") < 0) || in dw_mci_init_dma()
3157 host->dma_ops = &dw_mci_edmac_ops; in dw_mci_init_dma()
3158 dev_info(host->dev, "Using external DMA controller.\n"); in dw_mci_init_dma()
3161 if (host->dma_ops->init && host->dma_ops->start && in dw_mci_init_dma()
3162 host->dma_ops->stop && host->dma_ops->cleanup) { in dw_mci_init_dma()
3163 if (host->dma_ops->init(host)) { in dw_mci_init_dma()
3164 dev_err(host->dev, "%s: Unable to initialize DMA Controller.\n", in dw_mci_init_dma()
3169 dev_err(host->dev, "DMA initialization not found.\n"); in dw_mci_init_dma()
3176 dev_info(host->dev, "Using PIO mode.\n"); in dw_mci_init_dma()
3177 host->use_dma = TRANS_MODE_PIO; in dw_mci_init_dma()
3184 if (host->state != STATE_SENDING_CMD11) { in dw_mci_cmd11_timer()
3185 dev_warn(host->dev, "Unexpected CMD11 timeout\n"); in dw_mci_cmd11_timer()
3189 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cmd11_timer()
3190 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cmd11_timer()
3191 queue_work(system_bh_wq, &host->bh_work); in dw_mci_cmd11_timer()
3200 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3208 * pending command in the controller--we just assume it will never come. in dw_mci_cto_timer()
3210 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_cto_timer()
3213 dev_warn(host->dev, "Unexpected interrupt latency\n"); in dw_mci_cto_timer()
3216 if (test_bit(EVENT_CMD_COMPLETE, &host->pending_events)) { in dw_mci_cto_timer()
3218 dev_warn(host->dev, "CTO timeout when already completed\n"); in dw_mci_cto_timer()
3226 switch (host->state) { in dw_mci_cto_timer()
3235 host->cmd_status = SDMMC_INT_RTO; in dw_mci_cto_timer()
3236 set_bit(EVENT_CMD_COMPLETE, &host->pending_events); in dw_mci_cto_timer()
3237 queue_work(system_bh_wq, &host->bh_work); in dw_mci_cto_timer()
3240 dev_warn(host->dev, "Unexpected command timeout, state %d\n", in dw_mci_cto_timer()
3241 host->state); in dw_mci_cto_timer()
3246 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_cto_timer()
3255 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3261 pending = mci_readl(host, MINTSTS); /* read-only mask reg */ in dw_mci_dto_timer()
3264 dev_warn(host->dev, "Unexpected data interrupt latency\n"); in dw_mci_dto_timer()
3267 if (test_bit(EVENT_DATA_COMPLETE, &host->pending_events)) { in dw_mci_dto_timer()
3269 dev_warn(host->dev, "DTO timeout when already completed\n"); in dw_mci_dto_timer()
3277 switch (host->state) { in dw_mci_dto_timer()
3285 host->data_status = SDMMC_INT_DRTO; in dw_mci_dto_timer()
3286 set_bit(EVENT_DATA_ERROR, &host->pending_events); in dw_mci_dto_timer()
3287 set_bit(EVENT_DATA_COMPLETE, &host->pending_events); in dw_mci_dto_timer()
3288 queue_work(system_bh_wq, &host->bh_work); in dw_mci_dto_timer()
3291 dev_warn(host->dev, "Unexpected data timeout, state %d\n", in dw_mci_dto_timer()
3292 host->state); in dw_mci_dto_timer()
3297 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_dto_timer()
3304 struct device *dev = host->dev; in dw_mci_parse_dt()
3305 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_parse_dt()
3311 return ERR_PTR(-ENOMEM); in dw_mci_parse_dt()
3314 pdata->rstc = devm_reset_control_get_optional_exclusive(dev, "reset"); in dw_mci_parse_dt()
3315 if (IS_ERR(pdata->rstc)) in dw_mci_parse_dt()
3316 return ERR_CAST(pdata->rstc); in dw_mci_parse_dt()
3318 if (device_property_read_u32(dev, "fifo-depth", &pdata->fifo_depth)) in dw_mci_parse_dt()
3320 "fifo-depth property not found, using value of FIFOTH register as default\n"); in dw_mci_parse_dt()
3322 device_property_read_u32(dev, "card-detect-delay", in dw_mci_parse_dt()
3323 &pdata->detect_delay_ms); in dw_mci_parse_dt()
3325 device_property_read_u32(dev, "data-addr", &host->data_addr_override); in dw_mci_parse_dt()
3327 if (device_property_present(dev, "fifo-watermark-aligned")) in dw_mci_parse_dt()
3328 host->wm_aligned = true; in dw_mci_parse_dt()
3330 if (!device_property_read_u32(dev, "clock-frequency", &clock_frequency)) in dw_mci_parse_dt()
3331 pdata->bus_hz = clock_frequency; in dw_mci_parse_dt()
3333 if (drv_data && drv_data->parse_dt) { in dw_mci_parse_dt()
3334 ret = drv_data->parse_dt(host); in dw_mci_parse_dt()
3345 return ERR_PTR(-EINVAL); in dw_mci_parse_dt()
3355 * No need for CD if all slots have a non-error GPIO in dw_mci_enable_cd()
3358 if (host->slot->mmc->caps & MMC_CAP_NEEDS_POLL) in dw_mci_enable_cd()
3361 if (mmc_gpio_get_cd(host->slot->mmc) < 0) { in dw_mci_enable_cd()
3362 spin_lock_irqsave(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3366 spin_unlock_irqrestore(&host->irq_lock, irqflags); in dw_mci_enable_cd()
3372 const struct dw_mci_drv_data *drv_data = host->drv_data; in dw_mci_probe()
3376 if (!host->pdata) { in dw_mci_probe()
3377 host->pdata = dw_mci_parse_dt(host); in dw_mci_probe()
3378 if (IS_ERR(host->pdata)) in dw_mci_probe()
3379 return dev_err_probe(host->dev, PTR_ERR(host->pdata), in dw_mci_probe()
3383 host->biu_clk = devm_clk_get(host->dev, "biu"); in dw_mci_probe()
3384 if (IS_ERR(host->biu_clk)) { in dw_mci_probe()
3385 dev_dbg(host->dev, "biu clock not available\n"); in dw_mci_probe()
3386 ret = PTR_ERR(host->biu_clk); in dw_mci_probe()
3387 if (ret == -EPROBE_DEFER) in dw_mci_probe()
3391 ret = clk_prepare_enable(host->biu_clk); in dw_mci_probe()
3393 dev_err(host->dev, "failed to enable biu clock\n"); in dw_mci_probe()
3398 host->ciu_clk = devm_clk_get(host->dev, "ciu"); in dw_mci_probe()
3399 if (IS_ERR(host->ciu_clk)) { in dw_mci_probe()
3400 dev_dbg(host->dev, "ciu clock not available\n"); in dw_mci_probe()
3401 ret = PTR_ERR(host->ciu_clk); in dw_mci_probe()
3402 if (ret == -EPROBE_DEFER) in dw_mci_probe()
3405 host->bus_hz = host->pdata->bus_hz; in dw_mci_probe()
3407 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_probe()
3409 dev_err(host->dev, "failed to enable ciu clock\n"); in dw_mci_probe()
3413 if (host->pdata->bus_hz) { in dw_mci_probe()
3414 ret = clk_set_rate(host->ciu_clk, host->pdata->bus_hz); in dw_mci_probe()
3416 dev_warn(host->dev, in dw_mci_probe()
3418 host->pdata->bus_hz); in dw_mci_probe()
3420 host->bus_hz = clk_get_rate(host->ciu_clk); in dw_mci_probe()
3423 if (!host->bus_hz) { in dw_mci_probe()
3424 dev_err(host->dev, in dw_mci_probe()
3426 ret = -ENODEV; in dw_mci_probe()
3430 if (host->pdata->rstc) { in dw_mci_probe()
3431 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3433 reset_control_deassert(host->pdata->rstc); in dw_mci_probe()
3436 if (drv_data && drv_data->init) { in dw_mci_probe()
3437 ret = drv_data->init(host); in dw_mci_probe()
3439 dev_err(host->dev, in dw_mci_probe()
3445 timer_setup(&host->cmd11_timer, dw_mci_cmd11_timer, 0); in dw_mci_probe()
3446 timer_setup(&host->cto_timer, dw_mci_cto_timer, 0); in dw_mci_probe()
3447 timer_setup(&host->dto_timer, dw_mci_dto_timer, 0); in dw_mci_probe()
3449 spin_lock_init(&host->lock); in dw_mci_probe()
3450 spin_lock_init(&host->irq_lock); in dw_mci_probe()
3451 INIT_LIST_HEAD(&host->queue); in dw_mci_probe()
3456 * Get the host data width - this assumes that HCON has been set with in dw_mci_probe()
3461 host->push_data = dw_mci_push_data16; in dw_mci_probe()
3462 host->pull_data = dw_mci_pull_data16; in dw_mci_probe()
3464 host->data_shift = 1; in dw_mci_probe()
3466 if ((host->quirks & DW_MMC_QUIRK_FIFO64_32)) { in dw_mci_probe()
3467 host->push_data = dw_mci_push_data64_32; in dw_mci_probe()
3468 host->pull_data = dw_mci_pull_data64_32; in dw_mci_probe()
3470 host->push_data = dw_mci_push_data64; in dw_mci_probe()
3471 host->pull_data = dw_mci_pull_data64; in dw_mci_probe()
3474 host->data_shift = 3; in dw_mci_probe()
3479 "Defaulting to 32-bit access.\n"); in dw_mci_probe()
3480 host->push_data = dw_mci_push_data32; in dw_mci_probe()
3481 host->pull_data = dw_mci_pull_data32; in dw_mci_probe()
3483 host->data_shift = 2; in dw_mci_probe()
3488 ret = -ENODEV; in dw_mci_probe()
3492 host->dma_ops = host->pdata->dma_ops; in dw_mci_probe()
3503 * FIFO threshold settings RxMark = fifo_size / 2 - 1, in dw_mci_probe()
3506 if (!host->pdata->fifo_depth) { in dw_mci_probe()
3508 * Power-on value of RX_WMark is FIFO_DEPTH-1, but this may in dw_mci_probe()
3516 fifo_size = host->pdata->fifo_depth; in dw_mci_probe()
3518 host->fifo_depth = fifo_size; in dw_mci_probe()
3519 host->fifoth_val = in dw_mci_probe()
3520 SDMMC_SET_FIFOTH(0x2, fifo_size / 2 - 1, fifo_size / 2); in dw_mci_probe()
3521 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_probe()
3529 * Need to check the version-id and set data-offset for DATA register. in dw_mci_probe()
3531 host->verid = SDMMC_GET_VERID(mci_readl(host, VERID)); in dw_mci_probe()
3532 dev_info(host->dev, "Version ID is %04x\n", host->verid); in dw_mci_probe()
3534 if (host->data_addr_override) in dw_mci_probe()
3535 host->fifo_reg = host->regs + host->data_addr_override; in dw_mci_probe()
3536 else if (host->verid < DW_MMC_240A) in dw_mci_probe()
3537 host->fifo_reg = host->regs + DATA_OFFSET; in dw_mci_probe()
3539 host->fifo_reg = host->regs + DATA_240A_OFFSET; in dw_mci_probe()
3541 INIT_WORK(&host->bh_work, dw_mci_work_func); in dw_mci_probe()
3542 ret = devm_request_irq(host->dev, host->irq, dw_mci_interrupt, in dw_mci_probe()
3543 host->irq_flags, "dw-mci", host); in dw_mci_probe()
3555 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); in dw_mci_probe()
3557 dev_info(host->dev, in dw_mci_probe()
3559 host->irq, width, fifo_size); in dw_mci_probe()
3564 dev_dbg(host->dev, "slot %d init failed\n", i); in dw_mci_probe()
3574 if (host->use_dma && host->dma_ops->exit) in dw_mci_probe()
3575 host->dma_ops->exit(host); in dw_mci_probe()
3577 reset_control_assert(host->pdata->rstc); in dw_mci_probe()
3580 clk_disable_unprepare(host->ciu_clk); in dw_mci_probe()
3583 clk_disable_unprepare(host->biu_clk); in dw_mci_probe()
3591 dev_dbg(host->dev, "remove slot\n"); in dw_mci_remove()
3592 if (host->slot) in dw_mci_remove()
3593 dw_mci_cleanup_slot(host->slot); in dw_mci_remove()
3602 if (host->use_dma && host->dma_ops->exit) in dw_mci_remove()
3603 host->dma_ops->exit(host); in dw_mci_remove()
3605 reset_control_assert(host->pdata->rstc); in dw_mci_remove()
3607 clk_disable_unprepare(host->ciu_clk); in dw_mci_remove()
3608 clk_disable_unprepare(host->biu_clk); in dw_mci_remove()
3619 if (host->use_dma && host->dma_ops->exit) in dw_mci_runtime_suspend()
3620 host->dma_ops->exit(host); in dw_mci_runtime_suspend()
3622 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_suspend()
3624 if (host->slot && in dw_mci_runtime_suspend()
3625 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_suspend()
3626 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_suspend()
3627 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_suspend()
3638 if (host->slot && in dw_mci_runtime_resume()
3639 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3640 !mmc_card_is_removable(host->slot->mmc))) { in dw_mci_runtime_resume()
3641 ret = clk_prepare_enable(host->biu_clk); in dw_mci_runtime_resume()
3646 ret = clk_prepare_enable(host->ciu_clk); in dw_mci_runtime_resume()
3651 clk_disable_unprepare(host->ciu_clk); in dw_mci_runtime_resume()
3652 ret = -ENODEV; in dw_mci_runtime_resume()
3656 if (host->use_dma && host->dma_ops->init) in dw_mci_runtime_resume()
3657 host->dma_ops->init(host); in dw_mci_runtime_resume()
3663 mci_writel(host, FIFOTH, host->fifoth_val); in dw_mci_runtime_resume()
3664 host->prev_blksz = 0; in dw_mci_runtime_resume()
3673 mci_writel(host, CTRL, SDMMC_CTRL_INT_ENABLE); in dw_mci_runtime_resume()
3676 if (host->slot && host->slot->mmc->pm_flags & MMC_PM_KEEP_POWER) in dw_mci_runtime_resume()
3677 dw_mci_set_ios(host->slot->mmc, &host->slot->mmc->ios); in dw_mci_runtime_resume()
3680 dw_mci_setup_bus(host->slot, true); in dw_mci_runtime_resume()
3682 /* Re-enable SDIO interrupts. */ in dw_mci_runtime_resume()
3683 if (sdio_irq_claimed(host->slot->mmc)) in dw_mci_runtime_resume()
3684 __dw_mci_enable_sdio_irq(host->slot, 1); in dw_mci_runtime_resume()
3692 if (host->slot && in dw_mci_runtime_resume()
3693 (mmc_can_gpio_cd(host->slot->mmc) || in dw_mci_runtime_resume()
3694 !mmc_card_is_removable(host->slot->mmc))) in dw_mci_runtime_resume()
3695 clk_disable_unprepare(host->biu_clk); in dw_mci_runtime_resume()