Lines Matching +full:0 +full:x1c00
33 #define TREF_REG 0x00
34 #define TREF_TREF BIT(0)
37 #define SRST_REG 0x04
38 #define SRST_SRST BIT(0)
41 #define PHYCNT_REG 0x08
48 #define PHYCNT_ENABLE_0 BIT(0)
51 #define CHKSUM_REG 0x0c
53 #define CHKSUM_CRC_EN BIT(0)
57 * VCDT[0-15]: Channel 0 VCDT[16-31]: Channel 1
58 * VCDT2[0-15]: Channel 2 VCDT2[16-31]: Channel 3
60 #define VCDT_REG 0x10
61 #define VCDT2_REG 0x14
63 #define VCDT_SEL_VC(n) (((n) & 0x3) << 8)
65 #define VCDT_SEL_DT(n) (((n) & 0x3f) << 0)
68 #define FRDT_REG 0x18
71 #define FLD_REG 0x1c
72 #define FLD_FLD_NUM(n) (((n) & 0xff) << 16)
73 #define FLD_DET_SEL(n) (((n) & 0x3) << 4)
77 #define FLD_FLD_EN BIT(0)
80 #define ASTBY_REG 0x20
82 /* Long Data Type Setting 0 */
83 #define LNGDT0_REG 0x28
86 #define LNGDT1_REG 0x2c
89 #define INTEN_REG 0x30
95 #define INTCLOSE_REG 0x34
98 #define INTSTATE_REG 0x38
103 #define INTERRSTATE_REG 0x3c
106 #define SHPDAT_REG 0x40
109 #define SHPCNT_REG 0x44
112 #define LINKCNT_REG 0x48
118 #define LSWAP_REG 0x4c
119 #define LSWAP_L3SEL(n) (((n) & 0x3) << 6)
120 #define LSWAP_L2SEL(n) (((n) & 0x3) << 4)
121 #define LSWAP_L1SEL(n) (((n) & 0x3) << 2)
122 #define LSWAP_L0SEL(n) (((n) & 0x3) << 0)
125 #define PHTW_REG 0x50
127 #define PHTW_TESTDIN_DATA(n) (((n & 0xff)) << 16)
129 #define PHTW_TESTDIN_CODE(n) ((n & 0xff))
131 #define PHYFRX_REG 0x64
135 #define PHYFRX_FORCERX_MODE_0 BIT(0)
138 #define V4H_N_LANES_REG 0x0004
139 #define V4H_CSI2_RESETN_REG 0x0008
141 #define V4H_PHY_MODE_REG 0x001c
142 #define V4H_PHY_MODE_DPHY 0
145 #define V4H_PHY_SHUTDOWNZ_REG 0x0040
146 #define V4H_DPHY_RSTZ_REG 0x0044
147 #define V4H_FLDC_REG 0x0804
148 #define V4H_FLDD_REG 0x0808
149 #define V4H_IDIC_REG 0x0810
151 #define V4H_PHY_EN_REG 0x2000
156 #define V4H_PHY_EN_ENABLE_CLK BIT(0)
158 #define V4H_ST_PHYST_REG 0x2814
163 #define V4H_ST_PHYST_ST_STOPSTATE_0 BIT(0)
166 #define V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(n) (0x21800 + ((n) * 2)) /* n = 0 - 9 */
167 #define V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG 0x21822
168 #define V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG 0x2184c
169 #define V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG 0x21c02
170 #define V4H_PPI_RW_LPDCOCAL_NREF_REG 0x21c04
171 #define V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG 0x21c06
172 #define V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG 0x21c0a
173 #define V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG 0x21c0c
174 #define V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG 0x21c10
175 #define V4H_PPI_RW_COMMON_CFG_REG 0x21c6c
176 #define V4H_PPI_RW_TERMCAL_CFG_0_REG 0x21c80
177 #define V4H_PPI_RW_OFFSETCAL_CFG_0_REG 0x21ca0
180 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(n) (0x22040 + ((n) * 2)) /* n = 0 - 15 */
181 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(n) (0x22440 + ((n) * 2)) /* n = 0 - 15 */
182 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(n) (0x22840 + ((n) * 2)) /* n = 0 - 15 */
183 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(n) (0x22c40 + ((n) * 2)) /* n = 0 - 15 */
184 #define V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(n) (0x23040 + ((n) * 2)) /* n = 0 - 15 */
185 #define V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(n) (0x23840 + ((n) * 2)) /* n = 0 - 11 */
186 #define V4H_CORE_DIG_RW_COMMON_REG(n) (0x23880 + ((n) * 2)) /* n = 0 - 15 */
187 #define V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(n) (0x239e0 + ((n) * 2)) /* n = 0 - 3 */
188 #define V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG 0x2a60c
191 #define V4H_CORE_DIG_RW_TRIO0_REG(n) (0x22100 + ((n) * 2)) /* n = 0 - 3 */
192 #define V4H_CORE_DIG_RW_TRIO1_REG(n) (0x22500 + ((n) * 2)) /* n = 0 - 3 */
193 #define V4H_CORE_DIG_RW_TRIO2_REG(n) (0x22900 + ((n) * 2)) /* n = 0 - 3 */
194 #define V4H_CORE_DIG_CLANE_0_RW_CFG_0_REG 0x2a000
195 #define V4H_CORE_DIG_CLANE_0_RW_LP_0_REG 0x2a080
196 #define V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(n) (0x2a100 + ((n) * 2)) /* n = 0 - 6 */
197 #define V4H_CORE_DIG_CLANE_1_RW_CFG_0_REG 0x2a400
198 #define V4H_CORE_DIG_CLANE_1_RW_LP_0_REG 0x2a480
199 #define V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(n) (0x2a500 + ((n) * 2)) /* n = 0 - 6 */
200 #define V4H_CORE_DIG_CLANE_2_RW_CFG_0_REG 0x2a800
201 #define V4H_CORE_DIG_CLANE_2_RW_LP_0_REG 0x2a880
202 #define V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(n) (0x2a900 + ((n) * 2)) /* n = 0 - 6 */
215 …{ .msps = 80, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0134, .trio2 = 0x6a, .lane27 = 0x0000, .l…
216 …{ .msps = 100, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x00f5, .trio2 = 0x55, .lane27 = 0x0000, .l…
217 …{ .msps = 200, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0077, .trio2 = 0x2b, .lane27 = 0x0000, .l…
218 …{ .msps = 300, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x004d, .trio2 = 0x1d, .lane27 = 0x0000, .l…
219 …{ .msps = 400, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0038, .trio2 = 0x16, .lane27 = 0x0000, .l…
220 …{ .msps = 500, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x002b, .trio2 = 0x12, .lane27 = 0x0000, .l…
221 …{ .msps = 600, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0023, .trio2 = 0x0f, .lane27 = 0x0000, .l…
222 …{ .msps = 700, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x001d, .trio2 = 0x0d, .lane27 = 0x0000, .l…
223 …{ .msps = 800, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0018, .trio2 = 0x0c, .lane27 = 0x0000, .l…
224 …{ .msps = 900, .rx2 = 0x38, .trio0 = 0x024a, .trio1 = 0x0015, .trio2 = 0x0b, .lane27 = 0x0000, .l…
225 …{ .msps = 1000, .rx2 = 0x3e, .trio0 = 0x024a, .trio1 = 0x0012, .trio2 = 0x0a, .lane27 = 0x0400, .l…
226 …{ .msps = 1100, .rx2 = 0x44, .trio0 = 0x024a, .trio1 = 0x000f, .trio2 = 0x09, .lane27 = 0x0800, .l…
227 …{ .msps = 1200, .rx2 = 0x4a, .trio0 = 0x024a, .trio1 = 0x000e, .trio2 = 0x08, .lane27 = 0x0c00, .l…
228 …{ .msps = 1300, .rx2 = 0x51, .trio0 = 0x024a, .trio1 = 0x000c, .trio2 = 0x08, .lane27 = 0x0c00, .l…
229 …{ .msps = 1400, .rx2 = 0x57, .trio0 = 0x024a, .trio1 = 0x000b, .trio2 = 0x07, .lane27 = 0x1000, .l…
230 …{ .msps = 1500, .rx2 = 0x5d, .trio0 = 0x044a, .trio1 = 0x0009, .trio2 = 0x07, .lane27 = 0x1000, .l…
231 …{ .msps = 1600, .rx2 = 0x63, .trio0 = 0x044a, .trio1 = 0x0008, .trio2 = 0x07, .lane27 = 0x1400, .l…
232 …{ .msps = 1700, .rx2 = 0x6a, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .l…
233 …{ .msps = 1800, .rx2 = 0x70, .trio0 = 0x044a, .trio1 = 0x0007, .trio2 = 0x06, .lane27 = 0x1400, .l…
234 …{ .msps = 1900, .rx2 = 0x76, .trio0 = 0x044a, .trio1 = 0x0006, .trio2 = 0x06, .lane27 = 0x1400, .l…
235 …{ .msps = 2000, .rx2 = 0x7c, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x06, .lane27 = 0x1800, .l…
236 …{ .msps = 2100, .rx2 = 0x83, .trio0 = 0x044a, .trio1 = 0x0005, .trio2 = 0x05, .lane27 = 0x1800, .l…
237 …{ .msps = 2200, .rx2 = 0x89, .trio0 = 0x064a, .trio1 = 0x0004, .trio2 = 0x05, .lane27 = 0x1800, .l…
238 …{ .msps = 2300, .rx2 = 0x8f, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .l…
239 …{ .msps = 2400, .rx2 = 0x95, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1800, .l…
240 …{ .msps = 2500, .rx2 = 0x9c, .trio0 = 0x064a, .trio1 = 0x0003, .trio2 = 0x05, .lane27 = 0x1c00, .l…
241 …{ .msps = 2600, .rx2 = 0xa2, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .l…
242 …{ .msps = 2700, .rx2 = 0xa8, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x05, .lane27 = 0x1c00, .l…
243 …{ .msps = 2800, .rx2 = 0xae, .trio0 = 0x064a, .trio1 = 0x0002, .trio2 = 0x04, .lane27 = 0x1c00, .l…
244 …{ .msps = 2900, .rx2 = 0xb5, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
245 …{ .msps = 3000, .rx2 = 0xbb, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
246 …{ .msps = 3100, .rx2 = 0xc1, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
247 …{ .msps = 3200, .rx2 = 0xc7, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
248 …{ .msps = 3300, .rx2 = 0xce, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
249 …{ .msps = 3400, .rx2 = 0xd4, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
250 …{ .msps = 3500, .rx2 = 0xda, .trio0 = 0x084a, .trio1 = 0x0001, .trio2 = 0x04, .lane27 = 0x1c00, .l…
255 #define V4M_OVR1_REG 0x0848
261 #define V4M_FRXM_REG 0x2004
265 #define V4M_FRXM_FORCERXMODE_0 BIT(0)
267 #define V4M_PHYPLL_REG 0x02050
268 #define V4M_CSI0CLKFCPR_REG 0x02054
269 #define V4M_PHTW_REG 0x02060
270 #define V4M_PHTR_REG 0x02064
271 #define V4M_PHTC_REG 0x02068
285 { .mbps = 1500, .reg = 0xcc },
286 { .mbps = 1550, .reg = 0x1d },
287 { .mbps = 1600, .reg = 0x27 },
288 { .mbps = 1650, .reg = 0x30 },
289 { .mbps = 1700, .reg = 0x39 },
290 { .mbps = 1750, .reg = 0x42 },
291 { .mbps = 1800, .reg = 0x4b },
292 { .mbps = 1850, .reg = 0x55 },
293 { .mbps = 1900, .reg = 0x5e },
294 { .mbps = 1950, .reg = 0x67 },
295 { .mbps = 2000, .reg = 0x71 },
296 { .mbps = 2050, .reg = 0x79 },
297 { .mbps = 2100, .reg = 0x83 },
298 { .mbps = 2150, .reg = 0x8c },
299 { .mbps = 2200, .reg = 0x95 },
300 { .mbps = 2250, .reg = 0x9e },
301 { .mbps = 2300, .reg = 0xa7 },
302 { .mbps = 2350, .reg = 0xb0 },
303 { .mbps = 2400, .reg = 0xba },
304 { .mbps = 2450, .reg = 0xc3 },
305 { .mbps = 2500, .reg = 0xcc },
310 { .mbps = 80, .reg = 0x86 },
311 { .mbps = 90, .reg = 0x86 },
312 { .mbps = 100, .reg = 0x87 },
313 { .mbps = 110, .reg = 0x87 },
314 { .mbps = 120, .reg = 0x88 },
315 { .mbps = 130, .reg = 0x88 },
316 { .mbps = 140, .reg = 0x89 },
317 { .mbps = 150, .reg = 0x89 },
318 { .mbps = 160, .reg = 0x8a },
319 { .mbps = 170, .reg = 0x8a },
320 { .mbps = 180, .reg = 0x8b },
321 { .mbps = 190, .reg = 0x8b },
322 { .mbps = 205, .reg = 0x8c },
323 { .mbps = 220, .reg = 0x8d },
324 { .mbps = 235, .reg = 0x8e },
325 { .mbps = 250, .reg = 0x8e },
330 { .mbps = 80, .reg = 0x00 },
331 { .mbps = 90, .reg = 0x20 },
332 { .mbps = 100, .reg = 0x40 },
333 { .mbps = 110, .reg = 0x02 },
334 { .mbps = 130, .reg = 0x22 },
335 { .mbps = 140, .reg = 0x42 },
336 { .mbps = 150, .reg = 0x04 },
337 { .mbps = 170, .reg = 0x24 },
338 { .mbps = 180, .reg = 0x44 },
339 { .mbps = 200, .reg = 0x06 },
340 { .mbps = 220, .reg = 0x26 },
341 { .mbps = 240, .reg = 0x46 },
342 { .mbps = 250, .reg = 0x08 },
343 { .mbps = 270, .reg = 0x28 },
344 { .mbps = 300, .reg = 0x0a },
345 { .mbps = 330, .reg = 0x2a },
346 { .mbps = 360, .reg = 0x4a },
347 { .mbps = 400, .reg = 0x0c },
348 { .mbps = 450, .reg = 0x2c },
349 { .mbps = 500, .reg = 0x0e },
350 { .mbps = 550, .reg = 0x2e },
351 { .mbps = 600, .reg = 0x10 },
352 { .mbps = 650, .reg = 0x30 },
353 { .mbps = 700, .reg = 0x12 },
354 { .mbps = 750, .reg = 0x32 },
355 { .mbps = 800, .reg = 0x52 },
356 { .mbps = 850, .reg = 0x72 },
357 { .mbps = 900, .reg = 0x14 },
358 { .mbps = 950, .reg = 0x34 },
359 { .mbps = 1000, .reg = 0x54 },
360 { .mbps = 1050, .reg = 0x74 },
361 { .mbps = 1125, .reg = 0x16 },
366 #define PHTC_REG 0x58
367 #define PHTC_TESTCLR BIT(0)
370 #define PHYPLL_REG 0x68
374 { .mbps = 80, .reg = 0x00 },
375 { .mbps = 90, .reg = 0x10 },
376 { .mbps = 100, .reg = 0x20 },
377 { .mbps = 110, .reg = 0x30 },
378 { .mbps = 120, .reg = 0x01 },
379 { .mbps = 130, .reg = 0x11 },
380 { .mbps = 140, .reg = 0x21 },
381 { .mbps = 150, .reg = 0x31 },
382 { .mbps = 160, .reg = 0x02 },
383 { .mbps = 170, .reg = 0x12 },
384 { .mbps = 180, .reg = 0x22 },
385 { .mbps = 190, .reg = 0x32 },
386 { .mbps = 205, .reg = 0x03 },
387 { .mbps = 220, .reg = 0x13 },
388 { .mbps = 235, .reg = 0x23 },
389 { .mbps = 250, .reg = 0x33 },
390 { .mbps = 275, .reg = 0x04 },
391 { .mbps = 300, .reg = 0x14 },
392 { .mbps = 325, .reg = 0x25 },
393 { .mbps = 350, .reg = 0x35 },
394 { .mbps = 400, .reg = 0x05 },
395 { .mbps = 450, .reg = 0x16 },
396 { .mbps = 500, .reg = 0x26 },
397 { .mbps = 550, .reg = 0x37 },
398 { .mbps = 600, .reg = 0x07 },
399 { .mbps = 650, .reg = 0x18 },
400 { .mbps = 700, .reg = 0x28 },
401 { .mbps = 750, .reg = 0x39 },
402 { .mbps = 800, .reg = 0x09 },
403 { .mbps = 850, .reg = 0x19 },
404 { .mbps = 900, .reg = 0x29 },
405 { .mbps = 950, .reg = 0x3a },
406 { .mbps = 1000, .reg = 0x0a },
407 { .mbps = 1050, .reg = 0x1a },
408 { .mbps = 1100, .reg = 0x2a },
409 { .mbps = 1150, .reg = 0x3b },
410 { .mbps = 1200, .reg = 0x0b },
411 { .mbps = 1250, .reg = 0x1b },
412 { .mbps = 1300, .reg = 0x2b },
413 { .mbps = 1350, .reg = 0x3c },
414 { .mbps = 1400, .reg = 0x0c },
415 { .mbps = 1450, .reg = 0x1c },
416 { .mbps = 1500, .reg = 0x2c },
417 { .mbps = 1550, .reg = 0x3d },
418 { .mbps = 1600, .reg = 0x0d },
419 { .mbps = 1650, .reg = 0x1d },
420 { .mbps = 1700, .reg = 0x2e },
421 { .mbps = 1750, .reg = 0x3e },
422 { .mbps = 1800, .reg = 0x0e },
423 { .mbps = 1850, .reg = 0x1e },
424 { .mbps = 1900, .reg = 0x2f },
425 { .mbps = 1950, .reg = 0x3f },
426 { .mbps = 2000, .reg = 0x0f },
427 { .mbps = 2050, .reg = 0x40 },
428 { .mbps = 2100, .reg = 0x41 },
429 { .mbps = 2150, .reg = 0x42 },
430 { .mbps = 2200, .reg = 0x43 },
431 { .mbps = 2300, .reg = 0x45 },
432 { .mbps = 2350, .reg = 0x46 },
433 { .mbps = 2400, .reg = 0x47 },
434 { .mbps = 2450, .reg = 0x48 },
435 { .mbps = 2500, .reg = 0x49 },
440 { .mbps = 80, .reg = 0x00 },
441 { .mbps = 90, .reg = 0x10 },
442 { .mbps = 100, .reg = 0x20 },
443 { .mbps = 110, .reg = 0x30 },
444 { .mbps = 120, .reg = 0x01 },
445 { .mbps = 130, .reg = 0x11 },
446 { .mbps = 140, .reg = 0x21 },
447 { .mbps = 150, .reg = 0x31 },
448 { .mbps = 160, .reg = 0x02 },
449 { .mbps = 170, .reg = 0x12 },
450 { .mbps = 180, .reg = 0x22 },
451 { .mbps = 190, .reg = 0x32 },
452 { .mbps = 205, .reg = 0x03 },
453 { .mbps = 220, .reg = 0x13 },
454 { .mbps = 235, .reg = 0x23 },
455 { .mbps = 250, .reg = 0x33 },
456 { .mbps = 275, .reg = 0x04 },
457 { .mbps = 300, .reg = 0x14 },
458 { .mbps = 325, .reg = 0x25 },
459 { .mbps = 350, .reg = 0x35 },
460 { .mbps = 400, .reg = 0x05 },
461 { .mbps = 450, .reg = 0x16 },
462 { .mbps = 500, .reg = 0x26 },
463 { .mbps = 550, .reg = 0x37 },
464 { .mbps = 600, .reg = 0x07 },
465 { .mbps = 650, .reg = 0x18 },
466 { .mbps = 700, .reg = 0x28 },
467 { .mbps = 750, .reg = 0x39 },
468 { .mbps = 800, .reg = 0x09 },
469 { .mbps = 850, .reg = 0x19 },
470 { .mbps = 900, .reg = 0x29 },
471 { .mbps = 950, .reg = 0x3a },
472 { .mbps = 1000, .reg = 0x0a },
473 { .mbps = 1050, .reg = 0x1a },
474 { .mbps = 1100, .reg = 0x2a },
475 { .mbps = 1150, .reg = 0x3b },
476 { .mbps = 1200, .reg = 0x0b },
477 { .mbps = 1250, .reg = 0x1b },
478 { .mbps = 1300, .reg = 0x2b },
479 { .mbps = 1350, .reg = 0x3c },
480 { .mbps = 1400, .reg = 0x0c },
481 { .mbps = 1450, .reg = 0x1c },
482 { .mbps = 1500, .reg = 0x2c },
487 { .mbps = 80, .reg = 0x00 },
488 { .mbps = 90, .reg = 0x10 },
489 { .mbps = 100, .reg = 0x20 },
490 { .mbps = 110, .reg = 0x30 },
491 { .mbps = 120, .reg = 0x01 },
492 { .mbps = 130, .reg = 0x11 },
493 { .mbps = 140, .reg = 0x21 },
494 { .mbps = 150, .reg = 0x31 },
495 { .mbps = 160, .reg = 0x02 },
496 { .mbps = 170, .reg = 0x12 },
497 { .mbps = 180, .reg = 0x22 },
498 { .mbps = 190, .reg = 0x32 },
499 { .mbps = 205, .reg = 0x03 },
500 { .mbps = 220, .reg = 0x13 },
501 { .mbps = 235, .reg = 0x23 },
502 { .mbps = 250, .reg = 0x33 },
503 { .mbps = 275, .reg = 0x04 },
504 { .mbps = 300, .reg = 0x14 },
505 { .mbps = 325, .reg = 0x05 },
506 { .mbps = 350, .reg = 0x15 },
507 { .mbps = 400, .reg = 0x25 },
508 { .mbps = 450, .reg = 0x06 },
509 { .mbps = 500, .reg = 0x16 },
510 { .mbps = 550, .reg = 0x07 },
511 { .mbps = 600, .reg = 0x17 },
512 { .mbps = 650, .reg = 0x08 },
513 { .mbps = 700, .reg = 0x18 },
514 { .mbps = 750, .reg = 0x09 },
515 { .mbps = 800, .reg = 0x19 },
516 { .mbps = 850, .reg = 0x29 },
517 { .mbps = 900, .reg = 0x39 },
518 { .mbps = 950, .reg = 0x0a },
519 { .mbps = 1000, .reg = 0x1a },
520 { .mbps = 1050, .reg = 0x2a },
521 { .mbps = 1100, .reg = 0x3a },
522 { .mbps = 1150, .reg = 0x0b },
523 { .mbps = 1200, .reg = 0x1b },
524 { .mbps = 1250, .reg = 0x2b },
525 { .mbps = 1300, .reg = 0x3b },
526 { .mbps = 1350, .reg = 0x0c },
527 { .mbps = 1400, .reg = 0x1c },
528 { .mbps = 1450, .reg = 0x2c },
529 { .mbps = 1500, .reg = 0x3c },
534 { .mbps = 80, .reg = 0x00, .osc_freq = 0x01a9 },
535 { .mbps = 90, .reg = 0x10, .osc_freq = 0x01a9 },
536 { .mbps = 100, .reg = 0x20, .osc_freq = 0x01a9 },
537 { .mbps = 110, .reg = 0x30, .osc_freq = 0x01a9 },
538 { .mbps = 120, .reg = 0x01, .osc_freq = 0x01a9 },
539 { .mbps = 130, .reg = 0x11, .osc_freq = 0x01a9 },
540 { .mbps = 140, .reg = 0x21, .osc_freq = 0x01a9 },
541 { .mbps = 150, .reg = 0x31, .osc_freq = 0x01a9 },
542 { .mbps = 160, .reg = 0x02, .osc_freq = 0x01a9 },
543 { .mbps = 170, .reg = 0x12, .osc_freq = 0x01a9 },
544 { .mbps = 180, .reg = 0x22, .osc_freq = 0x01a9 },
545 { .mbps = 190, .reg = 0x32, .osc_freq = 0x01a9 },
546 { .mbps = 205, .reg = 0x03, .osc_freq = 0x01a9 },
547 { .mbps = 220, .reg = 0x13, .osc_freq = 0x01a9 },
548 { .mbps = 235, .reg = 0x23, .osc_freq = 0x01a9 },
549 { .mbps = 250, .reg = 0x33, .osc_freq = 0x01a9 },
550 { .mbps = 275, .reg = 0x04, .osc_freq = 0x01a9 },
551 { .mbps = 300, .reg = 0x14, .osc_freq = 0x01a9 },
552 { .mbps = 325, .reg = 0x25, .osc_freq = 0x01a9 },
553 { .mbps = 350, .reg = 0x35, .osc_freq = 0x01a9 },
554 { .mbps = 400, .reg = 0x05, .osc_freq = 0x01a9 },
555 { .mbps = 450, .reg = 0x16, .osc_freq = 0x01a9 },
556 { .mbps = 500, .reg = 0x26, .osc_freq = 0x01a9 },
557 { .mbps = 550, .reg = 0x37, .osc_freq = 0x01a9 },
558 { .mbps = 600, .reg = 0x07, .osc_freq = 0x01a9 },
559 { .mbps = 650, .reg = 0x18, .osc_freq = 0x01a9 },
560 { .mbps = 700, .reg = 0x28, .osc_freq = 0x01a9 },
561 { .mbps = 750, .reg = 0x39, .osc_freq = 0x01a9 },
562 { .mbps = 800, .reg = 0x09, .osc_freq = 0x01a9 },
563 { .mbps = 850, .reg = 0x19, .osc_freq = 0x01a9 },
564 { .mbps = 900, .reg = 0x29, .osc_freq = 0x01a9 },
565 { .mbps = 950, .reg = 0x3a, .osc_freq = 0x01a9 },
566 { .mbps = 1000, .reg = 0x0a, .osc_freq = 0x01a9 },
567 { .mbps = 1050, .reg = 0x1a, .osc_freq = 0x01a9 },
568 { .mbps = 1100, .reg = 0x2a, .osc_freq = 0x01a9 },
569 { .mbps = 1150, .reg = 0x3b, .osc_freq = 0x01a9 },
570 { .mbps = 1200, .reg = 0x0b, .osc_freq = 0x01a9 },
571 { .mbps = 1250, .reg = 0x1b, .osc_freq = 0x01a9 },
572 { .mbps = 1300, .reg = 0x2b, .osc_freq = 0x01a9 },
573 { .mbps = 1350, .reg = 0x3c, .osc_freq = 0x01a9 },
574 { .mbps = 1400, .reg = 0x0c, .osc_freq = 0x01a9 },
575 { .mbps = 1450, .reg = 0x1c, .osc_freq = 0x01a9 },
576 { .mbps = 1500, .reg = 0x2c, .osc_freq = 0x01a9 },
577 { .mbps = 1550, .reg = 0x3d, .osc_freq = 0x0108 },
578 { .mbps = 1600, .reg = 0x0d, .osc_freq = 0x0110 },
579 { .mbps = 1650, .reg = 0x1d, .osc_freq = 0x0119 },
580 { .mbps = 1700, .reg = 0x2e, .osc_freq = 0x0121 },
581 { .mbps = 1750, .reg = 0x3e, .osc_freq = 0x012a },
582 { .mbps = 1800, .reg = 0x0e, .osc_freq = 0x0132 },
583 { .mbps = 1850, .reg = 0x1e, .osc_freq = 0x013b },
584 { .mbps = 1900, .reg = 0x2f, .osc_freq = 0x0143 },
585 { .mbps = 1950, .reg = 0x3f, .osc_freq = 0x014c },
586 { .mbps = 2000, .reg = 0x0f, .osc_freq = 0x0154 },
587 { .mbps = 2050, .reg = 0x40, .osc_freq = 0x015d },
588 { .mbps = 2100, .reg = 0x41, .osc_freq = 0x0165 },
589 { .mbps = 2150, .reg = 0x42, .osc_freq = 0x016e },
590 { .mbps = 2200, .reg = 0x43, .osc_freq = 0x0176 },
591 { .mbps = 2250, .reg = 0x44, .osc_freq = 0x017f },
592 { .mbps = 2300, .reg = 0x45, .osc_freq = 0x0187 },
593 { .mbps = 2350, .reg = 0x46, .osc_freq = 0x0190 },
594 { .mbps = 2400, .reg = 0x47, .osc_freq = 0x0198 },
595 { .mbps = 2450, .reg = 0x48, .osc_freq = 0x01a1 },
596 { .mbps = 2500, .reg = 0x49, .osc_freq = 0x01a9 },
601 #define PHEERM_REG 0x74
604 #define PHCLM_REG 0x78
605 #define PHCLM_STOPSTATECKL BIT(0)
608 #define PHDLM_REG 0x7c
611 #define CSI0CLKFCPR_REG 0x260
612 #define CSI0CLKFREQRANGE(n) ((n & 0x3f) << 16)
704 for (i = 0; i < ARRAY_SIZE(rcar_csi2_formats); i++) in rcsi2_code_to_fmt()
718 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ABC, .cfg = 0x0, .ctrl29 = 0x0 },
719 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_ACB, .cfg = 0xa, .ctrl29 = 0x1 },
720 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BAC, .cfg = 0xc, .ctrl29 = 0x1 },
721 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_BCA, .cfg = 0x5, .ctrl29 = 0x0 },
722 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CAB, .cfg = 0x3, .ctrl29 = 0x0 },
723 { .order = V4L2_MBUS_CSI2_CPHY_LINE_ORDER_CBA, .cfg = 0x9, .ctrl29 = 0x1 }
836 for (timeout = 0; timeout <= 20; timeout++) { in rcsi2_phtw_write()
838 return 0; in rcsi2_phtw_write()
854 for (unsigned int i = 0; i < size; i++) { in rcsi2_phtw_write_array()
860 return 0; in rcsi2_phtw_write_array()
874 for (info = infotable; info->mbps != 0; info++) { in rcsi2_mbps_to_info()
893 rcsi2_write(priv, PHYCNT_REG, 0); in rcsi2_enter_standby_gen3()
912 if (ret < 0) in rcsi2_exit_standby()
917 return 0; in rcsi2_exit_standby()
926 for (timeout = 0; timeout <= 20; timeout++) { in rcsi2_wait_phy_start()
931 return 0; in rcsi2_wait_phy_start()
951 return 0; in rcsi2_set_phypll()
967 if (freq < 0) { in rcsi2_calc_mbps()
988 struct v4l2_mbus_config mbus_config = { 0 }; in rcsi2_get_active_lanes()
997 return 0; in rcsi2_get_active_lanes()
1029 return 0; in rcsi2_get_active_lanes()
1036 u32 phycnt, vcdt = 0, vcdt2 = 0, fld = 0; in rcsi2_start_receiver_gen3()
1062 for (i = 0; i < priv->info->num_channels; i++) { in rcsi2_start_receiver_gen3()
1065 if (priv->channel_vc[i] < 0) in rcsi2_start_receiver_gen3()
1083 fld |= FLD_FLD_NUM(0); in rcsi2_start_receiver_gen3()
1100 if (mbps < 0) in rcsi2_start_receiver_gen3()
1109 rcsi2_write(priv, PHTC_REG, 0); in rcsi2_start_receiver_gen3()
1120 LSWAP_L0SEL(priv->lane_swap[0] - 1) | in rcsi2_start_receiver_gen3()
1159 rcsi2_write(priv, PHYFRX_REG, 0); in rcsi2_start_receiver_gen3()
1173 return 0; in rcsi2_start_receiver_gen3()
1182 for (unsigned int i = 0; i < ARRAY_SIZE(rcsi2_cphy_line_orders); i++) { in rsci2_set_line_order()
1192 rcsi2_modify16(priv, cfgreg, info->cfg, 0x000f); in rsci2_set_line_order()
1193 rcsi2_modify16(priv, ctrlreg, info->ctrl29, 0x0100); in rsci2_set_line_order()
1201 for (timeout = 0; timeout <= 10; timeout++) { in rcsi2_wait_phy_start_v4h()
1204 return 0; in rcsi2_wait_phy_start_v4h()
1216 for (conf = cphy_setting_table_r8a779g0; conf->msps != 0; conf++) { in rcsi2_c_phy_setting_v4h()
1227 rcsi2_write16(priv, V4H_CORE_DIG_RW_COMMON_REG(7), 0x0155); in rcsi2_c_phy_setting_v4h()
1228 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(7), 0x0068); in rcsi2_c_phy_setting_v4h()
1229 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(8), 0x0010); in rcsi2_c_phy_setting_v4h()
1231 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_LP_0_REG, 0x463c); in rcsi2_c_phy_setting_v4h()
1232 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_LP_0_REG, 0x463c); in rcsi2_c_phy_setting_v4h()
1233 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_LP_0_REG, 0x463c); in rcsi2_c_phy_setting_v4h()
1235 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(0), 0x00d5); in rcsi2_c_phy_setting_v4h()
1236 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(0), 0x00d5); in rcsi2_c_phy_setting_v4h()
1237 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(0), 0x00d5); in rcsi2_c_phy_setting_v4h()
1239 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(1), 0x0013); in rcsi2_c_phy_setting_v4h()
1240 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(1), 0x0013); in rcsi2_c_phy_setting_v4h()
1241 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(1), 0x0013); in rcsi2_c_phy_setting_v4h()
1243 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(5), 0x0013); in rcsi2_c_phy_setting_v4h()
1244 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(5), 0x0013); in rcsi2_c_phy_setting_v4h()
1245 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(5), 0x0013); in rcsi2_c_phy_setting_v4h()
1247 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_0_RW_HS_RX_REG(6), 0x000a); in rcsi2_c_phy_setting_v4h()
1248 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_RX_REG(6), 0x000a); in rcsi2_c_phy_setting_v4h()
1249 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_2_RW_HS_RX_REG(6), 0x000a); in rcsi2_c_phy_setting_v4h()
1255 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE0_CTRL_2_REG(2), 0x0001); in rcsi2_c_phy_setting_v4h()
1256 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE1_CTRL_2_REG(2), 0); in rcsi2_c_phy_setting_v4h()
1257 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE2_CTRL_2_REG(2), 0x0001); in rcsi2_c_phy_setting_v4h()
1258 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE3_CTRL_2_REG(2), 0x0001); in rcsi2_c_phy_setting_v4h()
1259 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_LANE4_CTRL_2_REG(2), 0); in rcsi2_c_phy_setting_v4h()
1261 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO0_REG(0), conf->trio0); in rcsi2_c_phy_setting_v4h()
1262 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO1_REG(0), conf->trio0); in rcsi2_c_phy_setting_v4h()
1263 rcsi2_write16(priv, V4H_CORE_DIG_RW_TRIO2_REG(0), conf->trio0); in rcsi2_c_phy_setting_v4h()
1274 rsci2_set_line_order(priv, priv->line_orders[0], in rcsi2_c_phy_setting_v4h()
1285 rcsi2_write16(priv, V4H_CORE_DIG_CLANE_1_RW_HS_TX_6_REG, 0x5000); in rcsi2_c_phy_setting_v4h()
1288 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); in rcsi2_c_phy_setting_v4h()
1289 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); in rcsi2_c_phy_setting_v4h()
1301 return 0; in rcsi2_c_phy_setting_v4h()
1324 if (msps < 0) in rcsi2_start_receiver_v4h()
1328 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); in rcsi2_start_receiver_v4h()
1329 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); in rcsi2_start_receiver_v4h()
1330 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); in rcsi2_start_receiver_v4h()
1334 rcsi2_write(priv, V4H_FLDC_REG, 0); in rcsi2_start_receiver_v4h()
1335 rcsi2_write(priv, V4H_FLDD_REG, 0); in rcsi2_start_receiver_v4h()
1336 rcsi2_write(priv, V4H_IDIC_REG, 0); in rcsi2_start_receiver_v4h()
1341 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); in rcsi2_start_receiver_v4h()
1345 rcsi2_write16(priv, V4H_CORE_DIG_ANACTRL_RW_COMMON_ANACTRL_REG(0), 0x1bfd); in rcsi2_start_receiver_v4h()
1346 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_STARTUP_1_1_REG, 0x0233); in rcsi2_start_receiver_v4h()
1347 rcsi2_write16(priv, V4H_PPI_STARTUP_RW_COMMON_DPHY_REG(6), 0x0027); in rcsi2_start_receiver_v4h()
1348 rcsi2_write16(priv, V4H_PPI_CALIBCTRL_RW_COMMON_BG_0_REG, 0x01f4); in rcsi2_start_receiver_v4h()
1349 rcsi2_write16(priv, V4H_PPI_RW_TERMCAL_CFG_0_REG, 0x0013); in rcsi2_start_receiver_v4h()
1350 rcsi2_write16(priv, V4H_PPI_RW_OFFSETCAL_CFG_0_REG, 0x0003); in rcsi2_start_receiver_v4h()
1351 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TIMEBASE_REG, 0x004f); in rcsi2_start_receiver_v4h()
1352 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_REG, 0x0320); in rcsi2_start_receiver_v4h()
1353 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_NREF_RANGE_REG, 0x000f); in rcsi2_start_receiver_v4h()
1354 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_TWAIT_CONFIG_REG, 0xfe18); in rcsi2_start_receiver_v4h()
1355 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_VT_CONFIG_REG, 0x0c3c); in rcsi2_start_receiver_v4h()
1356 rcsi2_write16(priv, V4H_PPI_RW_LPDCOCAL_COARSE_CFG_REG, 0x0105); in rcsi2_start_receiver_v4h()
1357 rcsi2_write16(priv, V4H_CORE_DIG_IOCTRL_RW_AFE_CB_CTRL_2_REG(6), 0x1000); in rcsi2_start_receiver_v4h()
1358 rcsi2_write16(priv, V4H_PPI_RW_COMMON_CFG_REG, 0x0003); in rcsi2_start_receiver_v4h()
1369 return 0; in rcsi2_start_receiver_v4h()
1378 { .data = 0x00, .code = 0x00 }, in rcsi2_d_phy_setting_v4m()
1379 { .data = 0x00, .code = 0x1e }, in rcsi2_d_phy_setting_v4m()
1383 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, BIT(0)); in rcsi2_d_phy_setting_v4m()
1384 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, BIT(0)); in rcsi2_d_phy_setting_v4m()
1392 for (timeout = 10; timeout > 0; timeout--) { in rcsi2_d_phy_setting_v4m()
1393 if ((rcsi2_read(priv, V4M_PHTR_REG) & 0xf0000) == 0x70000) in rcsi2_d_phy_setting_v4m()
1403 return 0; in rcsi2_d_phy_setting_v4m()
1410 { .data = 0x00, .code = 0x00 }, in rcsi2_set_osc_freq()
1411 { .code = 0xe2 }, /* Data filled in below. */ in rcsi2_set_osc_freq()
1412 { .code = 0xe3 }, /* Data filled in below. */ in rcsi2_set_osc_freq()
1413 { .data = 0x01, .code = 0xe4 }, in rcsi2_set_osc_freq()
1421 steps[1].data = (info->osc_freq & 0x00ff) >> 0; in rcsi2_set_osc_freq()
1422 steps[2].data = (info->osc_freq & 0x0f00) >> 8; in rcsi2_set_osc_freq()
1432 { .data = 0x00, .code = 0x00 }, in rcsi2_init_common_v4m()
1433 { .data = 0x3c, .code = 0x08 }, in rcsi2_init_common_v4m()
1437 { .data = 0x00, .code = 0x00 }, in rcsi2_init_common_v4m()
1438 { .data = 0x80, .code = 0xe0 }, in rcsi2_init_common_v4m()
1439 { .data = 0x31, .code = 0xe1 }, in rcsi2_init_common_v4m()
1440 { .data = 0x06, .code = 0x00 }, in rcsi2_init_common_v4m()
1441 { .data = 0x11, .code = 0x11 }, in rcsi2_init_common_v4m()
1442 { .data = 0x08, .code = 0x00 }, in rcsi2_init_common_v4m()
1443 { .data = 0x11, .code = 0x11 }, in rcsi2_init_common_v4m()
1444 { .data = 0x0a, .code = 0x00 }, in rcsi2_init_common_v4m()
1445 { .data = 0x11, .code = 0x11 }, in rcsi2_init_common_v4m()
1446 { .data = 0x0c, .code = 0x00 }, in rcsi2_init_common_v4m()
1447 { .data = 0x11, .code = 0x11 }, in rcsi2_init_common_v4m()
1448 { .data = 0x01, .code = 0x00 }, in rcsi2_init_common_v4m()
1449 { .data = 0x31, .code = 0xaa }, in rcsi2_init_common_v4m()
1450 { .data = 0x05, .code = 0x00 }, in rcsi2_init_common_v4m()
1451 { .data = 0x05, .code = 0x09 }, in rcsi2_init_common_v4m()
1452 { .data = 0x07, .code = 0x00 }, in rcsi2_init_common_v4m()
1453 { .data = 0x05, .code = 0x09 }, in rcsi2_init_common_v4m()
1454 { .data = 0x09, .code = 0x00 }, in rcsi2_init_common_v4m()
1455 { .data = 0x05, .code = 0x09 }, in rcsi2_init_common_v4m()
1456 { .data = 0x0b, .code = 0x00 }, in rcsi2_init_common_v4m()
1457 { .data = 0x05, .code = 0x09 }, in rcsi2_init_common_v4m()
1461 { .data = 0x01, .code = 0x00 }, in rcsi2_init_common_v4m()
1462 { .data = 0x06, .code = 0xab }, in rcsi2_init_common_v4m()
1518 if (mbps < 0) in rcsi2_start_receiver_v4m()
1522 rcsi2_write(priv, V4H_CSI2_RESETN_REG, 0); in rcsi2_start_receiver_v4m()
1523 rcsi2_write(priv, V4H_DPHY_RSTZ_REG, 0); in rcsi2_start_receiver_v4m()
1524 rcsi2_write(priv, V4H_PHY_SHUTDOWNZ_REG, 0); in rcsi2_start_receiver_v4m()
1529 rcsi2_write(priv, V4H_FLDC_REG, 0); in rcsi2_start_receiver_v4m()
1530 rcsi2_write(priv, V4H_FLDD_REG, 0); in rcsi2_start_receiver_v4m()
1531 rcsi2_write(priv, V4H_IDIC_REG, 0); in rcsi2_start_receiver_v4m()
1543 rcsi2_write(priv, V4M_PHTC_REG, 0); in rcsi2_start_receiver_v4m()
1544 rcsi2_write(priv, V4H_CSI2_RESETN_REG, BIT(0)); in rcsi2_start_receiver_v4m()
1561 rcsi2_write(priv, V4M_FRXM_REG, 0); in rcsi2_start_receiver_v4m()
1563 return 0; in rcsi2_start_receiver_v4m()
1571 if (ret < 0) in rcsi2_start()
1581 BIT_ULL(0)); in rcsi2_start()
1587 return 0; in rcsi2_start()
1593 v4l2_subdev_disable_streams(priv->remote, priv->remote_pad, BIT_ULL(0)); in rcsi2_stop()
1601 int ret = 0; in rcsi2_enable_streams()
1609 if (priv->stream_count == 0) { in rcsi2_enable_streams()
1625 int ret = 0; in rcsi2_disable_streams()
1652 format->format.code = rcar_csi2_formats[0].code; in rcsi2_set_pad_format()
1660 return 0; in rcsi2_set_pad_format()
1695 return 0; in rcsi2_init_state()
1755 if (pad < 0) { in rcsi2_notify_bound()
1766 &priv->subdev.entity, 0, in rcsi2_notify_bound()
1792 /* Only port 0 endpoint 0 is valid. */ in rcsi2_parse_v4l2()
1834 for (i = 0; i < ARRAY_SIZE(priv->lane_swap); i++) { in rcsi2_parse_v4l2()
1845 for (i = 0; i < ARRAY_SIZE(priv->line_orders); i++) in rcsi2_parse_v4l2()
1848 return 0; in rcsi2_parse_v4l2()
1861 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(priv->dev), 0, 0, 0); in rcsi2_parse_dt()
1923 { .data = 0xcc, .code = 0xe2 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1924 { .data = 0x01, .code = 0xe3 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1925 { .data = 0x11, .code = 0xe4 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1926 { .data = 0x01, .code = 0xe5 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1927 { .data = 0x10, .code = 0x04 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1931 { .data = 0x38, .code = 0x08 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1932 { .data = 0x01, .code = 0x00 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1933 { .data = 0x4b, .code = 0xac }, in __rcsi2_init_phtw_h3_v3h_m3n()
1934 { .data = 0x03, .code = 0x00 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1935 { .data = 0x80, .code = 0x07 }, in __rcsi2_init_phtw_h3_v3h_m3n()
1944 if (mbps != 0 && mbps <= 250) { in __rcsi2_init_phtw_h3_v3h_m3n()
1945 ret = rcsi2_phtw_write(priv, 0x39, 0x05); in __rcsi2_init_phtw_h3_v3h_m3n()
1950 0xf1); in __rcsi2_init_phtw_h3_v3h_m3n()
1965 return __rcsi2_init_phtw_h3_v3h_m3n(priv, 0); in rcsi2_init_phtw_h3es2()
1970 return rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3m_e3, 0x44); in rcsi2_init_phtw_v3m_e3()
1976 { .data = 0xee, .code = 0x34 }, in rcsi2_phy_post_init_v3m_e3()
1977 { .data = 0xee, .code = 0x44 }, in rcsi2_phy_post_init_v3m_e3()
1978 { .data = 0xee, .code = 0x54 }, in rcsi2_phy_post_init_v3m_e3()
1979 { .data = 0xee, .code = 0x84 }, in rcsi2_phy_post_init_v3m_e3()
1980 { .data = 0xee, .code = 0x94 }, in rcsi2_phy_post_init_v3m_e3()
1991 { .data = 0xcc, .code = 0xe2 }, in rcsi2_init_phtw_v3u()
1995 { .data = 0x01, .code = 0xe3 }, in rcsi2_init_phtw_v3u()
1996 { .data = 0x11, .code = 0xe4 }, in rcsi2_init_phtw_v3u()
1997 { .data = 0x01, .code = 0xe5 }, in rcsi2_init_phtw_v3u()
2002 { .data = 0x38, .code = 0x08 }, in rcsi2_init_phtw_v3u()
2006 { .data = 0x01, .code = 0x00 }, in rcsi2_init_phtw_v3u()
2007 { .data = 0x4b, .code = 0xac }, in rcsi2_init_phtw_v3u()
2008 { .data = 0x03, .code = 0x00 }, in rcsi2_init_phtw_v3u()
2009 { .data = 0x80, .code = 0x07 }, in rcsi2_init_phtw_v3u()
2014 if (mbps != 0 && mbps <= 1500) in rcsi2_init_phtw_v3u()
2017 ret = rcsi2_phtw_write_mbps(priv, mbps, phtw_mbps_v3u, 0xe2); in rcsi2_init_phtw_v3u()
2025 if (mbps != 0 && mbps <= 1500) { in rcsi2_init_phtw_v3u()
2083 return 0; in rcsi2_link_setup()
2096 priv->base = devm_platform_ioremap_resource(pdev, 0); in rcsi2_probe_resources()
2100 irq = platform_get_irq(pdev, 0); in rcsi2_probe_resources()
2101 if (irq < 0) in rcsi2_probe_resources()
2126 .csi0clkfreqrange = 0x20,
2138 .csi0clkfreqrange = 0x20,
2168 .csi0clkfreqrange = 0x20,
2190 .csi0clkfreqrange = 0x20,
2211 .csi0clkfreqrange = 0x20,
2233 .csi0clkfreqrange = 0x0c,
2330 priv->stream_count = 0; in rcsi2_probe()
2367 for (i = 0; i < ARRAY_SIZE(priv->channel_vc); i++) in rcsi2_probe()
2377 if (ret < 0) in rcsi2_probe()
2382 return 0; in rcsi2_probe()