20 #define VFE_0_GLOBAL_RESET_CMD		0x018
21 #define VFE_0_GLOBAL_RESET_CMD_CORE	BIT(0)
32 #define VFE_0_MODULE_LENS_EN		0x040
36 #define VFE_0_MODULE_ZOOM_EN		0x04c
41 #define VFE_0_CORE_CFG			0x050
42 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR	0x4
43 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB	0x5
44 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY	0x6
45 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY	0x7
48 #define VFE_0_IRQ_CMD			0x058
49 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR	BIT(0)
51 #define VFE_0_IRQ_MASK_0		0x05c
52 #define VFE_0_IRQ_MASK_0_CAMIF_SOF			BIT(0)
60 #define VFE_0_IRQ_MASK_1		0x060
61 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR			BIT(0)
67 #define VFE_0_IRQ_CLEAR_0		0x064
68 #define VFE_0_IRQ_CLEAR_1		0x068
70 #define VFE_0_IRQ_STATUS_0		0x06c
71 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF			BIT(0)
78 #define VFE_0_IRQ_STATUS_1		0x070
83 #define VFE_0_IRQ_COMPOSITE_MASK_0	0x074
84 #define VFE_0_VIOLATION_STATUS		0x07c
86 #define VFE_0_BUS_CMD			0x80
89 #define VFE_0_BUS_CFG			0x084
91 #define VFE_0_BUS_XBAR_CFG_x(x)		(0x90 + 0x4 * ((x) / 2))
94 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA		(0x1 << 4)
95 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER		(0x2 << 4)
96 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA	(0x3 << 4)
98 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA		0x0
99 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0	0xc
100 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1	0xd
101 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2	0xe
103 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n)		(0x0a0 + 0x2c * (n))
104 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT	0
105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n)	(0x0a4 + 0x2c * (n))
106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n)	(0x0ac + 0x2c * (n))
107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n)		(0x0b4 + 0x2c * (n))
110 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK	(0x1f << 2)
111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n)		(0x0b8 + 0x2c * (n))
113 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n)	(0x0bc + 0x2c * (n))
114 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n)	(0x0c0 + 0x2c * (n))
116 							(0x0c4 + 0x2c * (n))
118 							(0x0c8 + 0x2c * (n))
119 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF	0xffffffff
121 #define VFE_0_BUS_PING_PONG_STATUS	0x338
123 #define VFE_0_BUS_BDG_CMD		0x400
126 #define VFE_0_BUS_BDG_QOS_CFG_0		0x404
127 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa5aaa5
128 #define VFE_0_BUS_BDG_QOS_CFG_1		0x408
129 #define VFE_0_BUS_BDG_QOS_CFG_2		0x40c
130 #define VFE_0_BUS_BDG_QOS_CFG_3		0x410
131 #define VFE_0_BUS_BDG_QOS_CFG_3_CFG	0xaa55aaa5
132 #define VFE_0_BUS_BDG_QOS_CFG_4		0x414
133 #define VFE_0_BUS_BDG_QOS_CFG_4_CFG	0xaa55aa55
134 #define VFE_0_BUS_BDG_QOS_CFG_5		0x418
135 #define VFE_0_BUS_BDG_QOS_CFG_6		0x41c
136 #define VFE_0_BUS_BDG_QOS_CFG_7		0x420
137 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG	0x0005aa55
139 #define VFE_0_BUS_BDG_DS_CFG_0		0x424
140 #define VFE_0_BUS_BDG_DS_CFG_0_CFG	0xcccc1111
141 #define VFE_0_BUS_BDG_DS_CFG_1		0x428
142 #define VFE_0_BUS_BDG_DS_CFG_2		0x42c
143 #define VFE_0_BUS_BDG_DS_CFG_3		0x430
144 #define VFE_0_BUS_BDG_DS_CFG_4		0x434
145 #define VFE_0_BUS_BDG_DS_CFG_5		0x438
146 #define VFE_0_BUS_BDG_DS_CFG_6		0x43c
147 #define VFE_0_BUS_BDG_DS_CFG_7		0x440
148 #define VFE_0_BUS_BDG_DS_CFG_8		0x444
149 #define VFE_0_BUS_BDG_DS_CFG_9		0x448
150 #define VFE_0_BUS_BDG_DS_CFG_10		0x44c
151 #define VFE_0_BUS_BDG_DS_CFG_11		0x450
152 #define VFE_0_BUS_BDG_DS_CFG_12		0x454
153 #define VFE_0_BUS_BDG_DS_CFG_13		0x458
154 #define VFE_0_BUS_BDG_DS_CFG_14		0x45c
155 #define VFE_0_BUS_BDG_DS_CFG_15		0x460
156 #define VFE_0_BUS_BDG_DS_CFG_16		0x464
157 #define VFE_0_BUS_BDG_DS_CFG_16_CFG	0x00000110
159 #define VFE_0_RDI_CFG_x(x)		(0x46c + (0x4 * (x)))
161 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK	(0xf << 28)
163 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK		(0xf << 4)
165 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS		0x3
167 #define VFE_0_CAMIF_CMD				0x478
168 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY	0
172 #define VFE_0_CAMIF_CFG				0x47c
174 #define VFE_0_CAMIF_FRAME_CFG			0x484
175 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG		0x488
176 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG		0x48c
177 #define VFE_0_CAMIF_SUBSAMPLE_CFG		0x490
178 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN	0x498
179 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN	0x49c
180 #define VFE_0_CAMIF_STATUS			0x4a4
183 #define VFE_0_REG_UPDATE		0x4ac
188 #define VFE_0_DEMUX_CFG				0x560
189 #define VFE_0_DEMUX_CFG_PERIOD			0x3
190 #define VFE_0_DEMUX_GAIN_0			0x564
191 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN		(0x80 << 0)
192 #define VFE_0_DEMUX_GAIN_0_CH0_ODD		(0x80 << 16)
193 #define VFE_0_DEMUX_GAIN_1			0x568
194 #define VFE_0_DEMUX_GAIN_1_CH1			(0x80 << 0)
195 #define VFE_0_DEMUX_GAIN_1_CH2			(0x80 << 16)
196 #define VFE_0_DEMUX_EVEN_CFG			0x574
197 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV	0x9cac
198 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU	0xac9c
199 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY	0xc9ca
200 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY	0xcac9
201 #define VFE_0_DEMUX_ODD_CFG			0x578
202 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV	0x9cac
203 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU	0xac9c
204 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY	0xc9ca
205 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY	0xcac9
207 #define VFE_0_SCALE_ENC_Y_CFG			0x91c
208 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE		0x920
209 #define VFE_0_SCALE_ENC_Y_H_PHASE		0x924
210 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE		0x934
211 #define VFE_0_SCALE_ENC_Y_V_PHASE		0x938
212 #define VFE_0_SCALE_ENC_CBCR_CFG		0x948
213 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE	0x94c
214 #define VFE_0_SCALE_ENC_CBCR_H_PHASE		0x950
215 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE	0x960
216 #define VFE_0_SCALE_ENC_CBCR_V_PHASE		0x964
218 #define VFE_0_CROP_ENC_Y_WIDTH			0x974
219 #define VFE_0_CROP_ENC_Y_HEIGHT			0x978
220 #define VFE_0_CROP_ENC_CBCR_WIDTH		0x97c
221 #define VFE_0_CROP_ENC_CBCR_HEIGHT		0x980
223 #define VFE_0_CLAMP_ENC_MAX_CFG			0x984
224 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0		(0xff << 0)
225 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1		(0xff << 8)
226 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2		(0xff << 16)
227 #define VFE_0_CLAMP_ENC_MIN_CFG			0x988
228 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0		(0x0 << 0)
229 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1		(0x0 << 8)
230 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2		(0x0 << 16)
232 #define VFE_0_REALIGN_BUF_CFG			0xaac
237 #define VFE_0_BUS_IMAGE_MASTER_CMD		0xcec
290 	writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);  in vfe_halt_clear()
307 	int val = 0;  in vfe_word_per_line_by_pixel()
341 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
347 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
365 		u16 width = 0, height = 0, bytesperline = 0, wpl;  in vfe_wm_line_based()
379 		reg = 0x3;  in vfe_wm_line_based()
386 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
388 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
454 	return (reg >> wm) & 0x1;  in vfe_wm_get_ping_pong_status()
460 		writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
462 		writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
471 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg);  in vfe_bus_connect_wm_to_rdi()
551 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
556 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
560 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
589 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
594 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
598 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
685 	u32 comp_mask = 0;  in vfe_enable_irq_pix_line()
692 	for (i = 0; i < output->wm_num; i++) {  in vfe_enable_irq_pix_line()
762 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);  in vfe_set_scale_cfg()
784 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);  in vfe_set_scale_cfg()
893 	val = 0xffffffff;  in vfe_set_camif_cfg()
896 	val = 0xffffffff;  in vfe_set_camif_cfg()
899 	val = 0xffffffff;  in vfe_set_camif_cfg()
903 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val);  in vfe_set_camif_cfg()
953 	if (ret < 0)  in vfe_camif_wait_for_stop()
974 	dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n",  in vfe_isr()
997 	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)  in vfe_isr()
1000 			for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++)  in vfe_isr()
1005 	for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++)  in vfe_isr()
1089 	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);  in vfe_violation_read()