21 #define VFE_0_GLOBAL_RESET_CMD		0x018
22 #define VFE_0_GLOBAL_RESET_CMD_CORE	BIT(0)
33 #define VFE_0_MODULE_LENS_EN		0x040
37 #define VFE_0_MODULE_ZOOM_EN		0x04c
42 #define VFE_0_CORE_CFG			0x050
43 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCBYCR	0x4
44 #define VFE_0_CORE_CFG_PIXEL_PATTERN_YCRYCB	0x5
45 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CBYCRY	0x6
46 #define VFE_0_CORE_CFG_PIXEL_PATTERN_CRYCBY	0x7
49 #define VFE_0_IRQ_CMD			0x058
50 #define VFE_0_IRQ_CMD_GLOBAL_CLEAR	BIT(0)
52 #define VFE_0_IRQ_MASK_0		0x05c
53 #define VFE_0_IRQ_MASK_0_CAMIF_SOF			BIT(0)
61 #define VFE_0_IRQ_MASK_1		0x060
62 #define VFE_0_IRQ_MASK_1_CAMIF_ERROR			BIT(0)
68 #define VFE_0_IRQ_CLEAR_0		0x064
69 #define VFE_0_IRQ_CLEAR_1		0x068
71 #define VFE_0_IRQ_STATUS_0		0x06c
72 #define VFE_0_IRQ_STATUS_0_CAMIF_SOF			BIT(0)
79 #define VFE_0_IRQ_STATUS_1		0x070
84 #define VFE_0_IRQ_COMPOSITE_MASK_0	0x074
85 #define VFE_0_VIOLATION_STATUS		0x07c
87 #define VFE_0_BUS_CMD			0x80
90 #define VFE_0_BUS_CFG			0x084
92 #define VFE_0_BUS_XBAR_CFG_x(x)		(0x90 + 0x4 * ((x) / 2))
95 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTRA		(0x1 << 4)
96 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER		(0x2 << 4)
97 #define VFE_0_BUS_XBAR_CFG_x_M_PAIR_STREAM_SWAP_INTER_INTRA	(0x3 << 4)
99 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_LUMA		0x0
100 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI0	0xc
101 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI1	0xd
102 #define VFE_0_BUS_XBAR_CFG_x_M_SINGLE_STREAM_SEL_VAL_RDI2	0xe
104 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG(n)		(0x0a0 + 0x2c * (n))
105 #define VFE_0_BUS_IMAGE_MASTER_n_WR_CFG_WR_PATH_SHIFT	0
106 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PING_ADDR(n)	(0x0a4 + 0x2c * (n))
107 #define VFE_0_BUS_IMAGE_MASTER_n_WR_PONG_ADDR(n)	(0x0ac + 0x2c * (n))
108 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG(n)		(0x0b4 + 0x2c * (n))
111 #define VFE_0_BUS_IMAGE_MASTER_n_WR_ADDR_CFG_FRM_DROP_PER_MASK	(0x1f << 2)
112 #define VFE_0_BUS_IMAGE_MASTER_n_WR_UB_CFG(n)		(0x0b8 + 0x2c * (n))
114 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IMAGE_SIZE(n)	(0x0bc + 0x2c * (n))
115 #define VFE_0_BUS_IMAGE_MASTER_n_WR_BUFFER_CFG(n)	(0x0c0 + 0x2c * (n))
117 							(0x0c4 + 0x2c * (n))
119 							(0x0c8 + 0x2c * (n))
120 #define VFE_0_BUS_IMAGE_MASTER_n_WR_IRQ_SUBSAMPLE_PATTERN_DEF	0xffffffff
122 #define VFE_0_BUS_PING_PONG_STATUS	0x338
124 #define VFE_0_BUS_BDG_CMD		0x400
127 #define VFE_0_BUS_BDG_QOS_CFG_0		0x404
128 #define VFE_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa9aaa9
129 #define VFE_0_BUS_BDG_QOS_CFG_1		0x408
130 #define VFE_0_BUS_BDG_QOS_CFG_2		0x40c
131 #define VFE_0_BUS_BDG_QOS_CFG_3		0x410
132 #define VFE_0_BUS_BDG_QOS_CFG_4		0x414
133 #define VFE_0_BUS_BDG_QOS_CFG_5		0x418
134 #define VFE_0_BUS_BDG_QOS_CFG_6		0x41c
135 #define VFE_0_BUS_BDG_QOS_CFG_7		0x420
136 #define VFE_0_BUS_BDG_QOS_CFG_7_CFG	0x0001aaa9
138 #define VFE48_0_BUS_BDG_QOS_CFG_0_CFG	0xaaa5aaa5
139 #define VFE48_0_BUS_BDG_QOS_CFG_3_CFG	0xaa55aaa5
140 #define VFE48_0_BUS_BDG_QOS_CFG_4_CFG	0xaa55aa55
141 #define VFE48_0_BUS_BDG_QOS_CFG_7_CFG	0x0005aa55
143 #define VFE_0_BUS_BDG_DS_CFG_0		0x424
144 #define VFE_0_BUS_BDG_DS_CFG_0_CFG	0xcccc0011
145 #define VFE_0_BUS_BDG_DS_CFG_1		0x428
146 #define VFE_0_BUS_BDG_DS_CFG_2		0x42c
147 #define VFE_0_BUS_BDG_DS_CFG_3		0x430
148 #define VFE_0_BUS_BDG_DS_CFG_4		0x434
149 #define VFE_0_BUS_BDG_DS_CFG_5		0x438
150 #define VFE_0_BUS_BDG_DS_CFG_6		0x43c
151 #define VFE_0_BUS_BDG_DS_CFG_7		0x440
152 #define VFE_0_BUS_BDG_DS_CFG_8		0x444
153 #define VFE_0_BUS_BDG_DS_CFG_9		0x448
154 #define VFE_0_BUS_BDG_DS_CFG_10		0x44c
155 #define VFE_0_BUS_BDG_DS_CFG_11		0x450
156 #define VFE_0_BUS_BDG_DS_CFG_12		0x454
157 #define VFE_0_BUS_BDG_DS_CFG_13		0x458
158 #define VFE_0_BUS_BDG_DS_CFG_14		0x45c
159 #define VFE_0_BUS_BDG_DS_CFG_15		0x460
160 #define VFE_0_BUS_BDG_DS_CFG_16		0x464
161 #define VFE_0_BUS_BDG_DS_CFG_16_CFG	0x40000103
163 #define VFE48_0_BUS_BDG_DS_CFG_0_CFG	0xcccc1111
164 #define VFE48_0_BUS_BDG_DS_CFG_16_CFG	0x00000110
166 #define VFE_0_RDI_CFG_x(x)		(0x46c + (0x4 * (x)))
168 #define VFE_0_RDI_CFG_x_RDI_STREAM_SEL_MASK	(0xf << 28)
170 #define VFE_0_RDI_CFG_x_RDI_M0_SEL_MASK		(0xf << 4)
172 #define VFE_0_RDI_CFG_x_MIPI_EN_BITS		0x3
174 #define VFE_0_CAMIF_CMD				0x478
175 #define VFE_0_CAMIF_CMD_DISABLE_FRAME_BOUNDARY	0
179 #define VFE_0_CAMIF_CFG				0x47c
181 #define VFE_0_CAMIF_FRAME_CFG			0x484
182 #define VFE_0_CAMIF_WINDOW_WIDTH_CFG		0x488
183 #define VFE_0_CAMIF_WINDOW_HEIGHT_CFG		0x48c
184 #define VFE_0_CAMIF_SUBSAMPLE_CFG		0x490
185 #define VFE_0_CAMIF_IRQ_FRAMEDROP_PATTERN	0x498
186 #define VFE_0_CAMIF_IRQ_SUBSAMPLE_PATTERN	0x49c
187 #define VFE_0_CAMIF_STATUS			0x4a4
190 #define VFE_0_REG_UPDATE		0x4ac
195 #define VFE_0_DEMUX_CFG				0x560
196 #define VFE_0_DEMUX_CFG_PERIOD			0x3
197 #define VFE_0_DEMUX_GAIN_0			0x564
198 #define VFE_0_DEMUX_GAIN_0_CH0_EVEN		(0x80 << 0)
199 #define VFE_0_DEMUX_GAIN_0_CH0_ODD		(0x80 << 16)
200 #define VFE_0_DEMUX_GAIN_1			0x568
201 #define VFE_0_DEMUX_GAIN_1_CH1			(0x80 << 0)
202 #define VFE_0_DEMUX_GAIN_1_CH2			(0x80 << 16)
203 #define VFE_0_DEMUX_EVEN_CFG			0x574
204 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YUYV	0x9cac
205 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_YVYU	0xac9c
206 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_UYVY	0xc9ca
207 #define VFE_0_DEMUX_EVEN_CFG_PATTERN_VYUY	0xcac9
208 #define VFE_0_DEMUX_ODD_CFG			0x578
209 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YUYV	0x9cac
210 #define VFE_0_DEMUX_ODD_CFG_PATTERN_YVYU	0xac9c
211 #define VFE_0_DEMUX_ODD_CFG_PATTERN_UYVY	0xc9ca
212 #define VFE_0_DEMUX_ODD_CFG_PATTERN_VYUY	0xcac9
214 #define VFE_0_SCALE_ENC_Y_CFG			0x91c
215 #define VFE_0_SCALE_ENC_Y_H_IMAGE_SIZE		0x920
216 #define VFE_0_SCALE_ENC_Y_H_PHASE		0x924
217 #define VFE_0_SCALE_ENC_Y_V_IMAGE_SIZE		0x934
218 #define VFE_0_SCALE_ENC_Y_V_PHASE		0x938
219 #define VFE_0_SCALE_ENC_CBCR_CFG		0x948
220 #define VFE_0_SCALE_ENC_CBCR_H_IMAGE_SIZE	0x94c
221 #define VFE_0_SCALE_ENC_CBCR_H_PHASE		0x950
222 #define VFE_0_SCALE_ENC_CBCR_V_IMAGE_SIZE	0x960
223 #define VFE_0_SCALE_ENC_CBCR_V_PHASE		0x964
225 #define VFE_0_CROP_ENC_Y_WIDTH			0x974
226 #define VFE_0_CROP_ENC_Y_HEIGHT			0x978
227 #define VFE_0_CROP_ENC_CBCR_WIDTH		0x97c
228 #define VFE_0_CROP_ENC_CBCR_HEIGHT		0x980
230 #define VFE_0_CLAMP_ENC_MAX_CFG			0x984
231 #define VFE_0_CLAMP_ENC_MAX_CFG_CH0		(0xff << 0)
232 #define VFE_0_CLAMP_ENC_MAX_CFG_CH1		(0xff << 8)
233 #define VFE_0_CLAMP_ENC_MAX_CFG_CH2		(0xff << 16)
234 #define VFE_0_CLAMP_ENC_MIN_CFG			0x988
235 #define VFE_0_CLAMP_ENC_MIN_CFG_CH0		(0x0 << 0)
236 #define VFE_0_CLAMP_ENC_MIN_CFG_CH1		(0x0 << 8)
237 #define VFE_0_CLAMP_ENC_MIN_CFG_CH2		(0x0 << 16)
239 #define VFE_0_REALIGN_BUF_CFG			0xaac
244 #define VFE48_0_BUS_IMAGE_MASTER_CMD		0xcec
257 	if (vfe_id == 0)  in vfe_get_ub_size()
262 	return 0;  in vfe_get_ub_size()
307 	writel_relaxed(0x0, vfe->base + VFE_0_BUS_BDG_CMD);  in vfe_halt_clear()
334 	int val = 0;  in vfe_word_per_line_by_pixel()
368 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
374 		*bytesperline = pix->plane_fmt[0].bytesperline;  in vfe_get_wm_sizes()
392 		u16 width = 0, height = 0, bytesperline = 0, wpl;  in vfe_wm_line_based()
406 		reg = 0x3;  in vfe_wm_line_based()
413 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
415 		writel_relaxed(0, vfe->base +  in vfe_wm_line_based()
482 	return (reg >> wm) & 0x1;  in vfe_wm_get_ping_pong_status()
488 		writel_relaxed(0x101, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
490 		writel_relaxed(0, vfe->base + VFE_0_BUS_CFG);  in vfe_bus_enable_wr_if()
499 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), reg);  in vfe_bus_connect_wm_to_rdi()
580 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
585 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
589 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
618 		if (output->wm_idx[0] % 2 == 1)  in vfe_set_xbar_cfg()
623 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
627 				    VFE_0_BUS_XBAR_CFG_x(output->wm_idx[0]),  in vfe_set_xbar_cfg()
713 	u32 comp_mask = 0;  in vfe_enable_irq_pix_line()
720 	for (i = 0; i < output->wm_num; i++) {  in vfe_enable_irq_pix_line()
791 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_Y_CFG);  in vfe_set_scale_cfg()
813 	writel_relaxed(0x3, vfe->base + VFE_0_SCALE_ENC_CBCR_CFG);  in vfe_set_scale_cfg()
961 	val = 0xffffffff;  in vfe_set_camif_cfg()
964 	val = 0xffffffff;  in vfe_set_camif_cfg()
967 	val = 0xffffffff;  in vfe_set_camif_cfg()
971 	vfe_reg_set(vfe, VFE_0_RDI_CFG_x(0), val);  in vfe_set_camif_cfg()
1021 	if (ret < 0)  in vfe_camif_wait_for_stop()
1044 	dev_dbg(vfe->camss->dev, "VFE: status0 = 0x%08x, status1 = 0x%08x\n",  in vfe_isr()
1067 	for (i = 0; i < MSM_VFE_COMPOSITE_IRQ_NUM; i++)  in vfe_isr()
1070 			for (j = 0; j < ARRAY_SIZE(vfe->wm_output_map); j++)  in vfe_isr()
1075 	for (i = 0; i < MSM_VFE_IMAGE_MASTERS_NUM; i++)  in vfe_isr()
1099 	pr_err_ratelimited("VFE: violation = 0x%08x\n", violation);  in vfe_violation_read()