Lines Matching +full:dphy +full:- +full:rx
1 // SPDX-License-Identifier: GPL-2.0+
3 * Driver for Cadence MIPI-CSI2 RX Controller v1.3
20 #include <media/v4l2-ctrls.h>
21 #include <media/v4l2-device.h>
22 #include <media/v4l2-fwnode.h>
23 #include <media/v4l2-subdev.h>
91 struct phy *dphy; member
150 csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
152 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_reset()
154 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_reset()
160 writel(0, csi2rx->base + CSI2RX_SOFT_RESET_REG); in csi2rx_reset()
161 for (i = 0; i < csi2rx->max_streams; i++) in csi2rx_reset()
162 writel(0, csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_reset()
168 &csi2rx->source_subdev->entity.pads[csi2rx->source_pad]; in csi2rx_configure_ext_dphy()
179 ret = v4l2_subdev_call_state_active(&csi2rx->subdev, pad, get_fmt, in csi2rx_configure_ext_dphy()
187 fmt->bpp, 2 * csi2rx->num_lanes); in csi2rx_configure_ext_dphy()
192 csi2rx->num_lanes, cfg); in csi2rx_configure_ext_dphy()
196 ret = phy_power_on(csi2rx->dphy); in csi2rx_configure_ext_dphy()
200 ret = phy_configure(csi2rx->dphy, &opts); in csi2rx_configure_ext_dphy()
202 phy_power_off(csi2rx->dphy); in csi2rx_configure_ext_dphy()
216 ret = clk_prepare_enable(csi2rx->p_clk); in csi2rx_start()
220 reset_control_deassert(csi2rx->p_rst); in csi2rx_start()
223 reg = csi2rx->num_lanes << 8; in csi2rx_start()
224 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
225 reg |= CSI2RX_STATIC_CFG_DLANE_MAP(i, csi2rx->lanes[i]); in csi2rx_start()
226 set_bit(csi2rx->lanes[i], &lanes_used); in csi2rx_start()
235 for (i = csi2rx->num_lanes; i < csi2rx->max_lanes; i++) { in csi2rx_start()
237 csi2rx->max_lanes); in csi2rx_start()
242 writel(reg, csi2rx->base + CSI2RX_STATIC_CFG_REG); in csi2rx_start()
244 /* Enable DPHY clk and data lanes. */ in csi2rx_start()
245 if (csi2rx->dphy) { in csi2rx_start()
247 for (i = 0; i < csi2rx->num_lanes; i++) { in csi2rx_start()
248 reg |= CSI2RX_DPHY_DL_EN(csi2rx->lanes[i] - 1); in csi2rx_start()
249 reg |= CSI2RX_DPHY_DL_RST(csi2rx->lanes[i] - 1); in csi2rx_start()
252 writel(reg, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); in csi2rx_start()
256 dev_err(csi2rx->dev, in csi2rx_start()
257 "Failed to configure external DPHY: %d\n", ret); in csi2rx_start()
272 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_start()
273 ret = clk_prepare_enable(csi2rx->pixel_clk[i]); in csi2rx_start()
277 reset_control_deassert(csi2rx->pixel_rst[i]); in csi2rx_start()
280 csi2rx->base + CSI2RX_STREAM_CFG_REG(i)); in csi2rx_start()
287 csi2rx->base + CSI2RX_STREAM_DATA_CFG_REG(i)); in csi2rx_start()
290 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_start()
293 ret = clk_prepare_enable(csi2rx->sys_clk); in csi2rx_start()
297 reset_control_deassert(csi2rx->sys_rst); in csi2rx_start()
299 ret = v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, true); in csi2rx_start()
303 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_start()
308 clk_disable_unprepare(csi2rx->sys_clk); in csi2rx_start()
310 for (; i > 0; i--) { in csi2rx_start()
311 reset_control_assert(csi2rx->pixel_rst[i - 1]); in csi2rx_start()
312 clk_disable_unprepare(csi2rx->pixel_clk[i - 1]); in csi2rx_start()
315 if (csi2rx->dphy) { in csi2rx_start()
316 writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); in csi2rx_start()
317 phy_power_off(csi2rx->dphy); in csi2rx_start()
320 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_start()
331 clk_prepare_enable(csi2rx->p_clk); in csi2rx_stop()
332 reset_control_assert(csi2rx->sys_rst); in csi2rx_stop()
333 clk_disable_unprepare(csi2rx->sys_clk); in csi2rx_stop()
335 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_stop()
337 csi2rx->base + CSI2RX_STREAM_CTRL_REG(i)); in csi2rx_stop()
339 ret = readl_relaxed_poll_timeout(csi2rx->base + in csi2rx_stop()
345 dev_warn(csi2rx->dev, in csi2rx_stop()
348 reset_control_assert(csi2rx->pixel_rst[i]); in csi2rx_stop()
349 clk_disable_unprepare(csi2rx->pixel_clk[i]); in csi2rx_stop()
352 reset_control_assert(csi2rx->p_rst); in csi2rx_stop()
353 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_stop()
355 if (v4l2_subdev_call(csi2rx->source_subdev, video, s_stream, false)) in csi2rx_stop()
356 dev_warn(csi2rx->dev, "Couldn't disable our subdev\n"); in csi2rx_stop()
358 if (csi2rx->dphy) { in csi2rx_stop()
359 writel(0, csi2rx->base + CSI2RX_DPHY_LANE_CTRL_REG); in csi2rx_stop()
361 if (phy_power_off(csi2rx->dphy)) in csi2rx_stop()
362 dev_warn(csi2rx->dev, "Couldn't power off DPHY\n"); in csi2rx_stop()
371 mutex_lock(&csi2rx->lock); in csi2rx_s_stream()
378 if (!csi2rx->count) { in csi2rx_s_stream()
384 csi2rx->count++; in csi2rx_s_stream()
386 csi2rx->count--; in csi2rx_s_stream()
391 if (!csi2rx->count) in csi2rx_s_stream()
396 mutex_unlock(&csi2rx->lock); in csi2rx_s_stream()
404 if (code_enum->index >= ARRAY_SIZE(formats)) in csi2rx_enum_mbus_code()
405 return -EINVAL; in csi2rx_enum_mbus_code()
407 code_enum->code = formats[code_enum->index].code; in csi2rx_enum_mbus_code()
420 if (format->pad != CSI2RX_PAD_SINK) in csi2rx_set_fmt()
423 if (!csi2rx_get_fmt_by_code(format->format.code)) in csi2rx_set_fmt()
424 format->format.code = formats[0].code; in csi2rx_set_fmt()
426 format->format.field = V4L2_FIELD_NONE; in csi2rx_set_fmt()
429 fmt = v4l2_subdev_state_get_format(state, format->pad); in csi2rx_set_fmt()
430 *fmt = format->format; in csi2rx_set_fmt()
435 *fmt = format->format; in csi2rx_set_fmt()
488 struct v4l2_subdev *subdev = notifier->sd; in csi2rx_async_bound()
491 csi2rx->source_pad = media_entity_get_fwnode_pad(&s_subdev->entity, in csi2rx_async_bound()
492 asd->match.fwnode, in csi2rx_async_bound()
494 if (csi2rx->source_pad < 0) { in csi2rx_async_bound()
495 dev_err(csi2rx->dev, "Couldn't find output pad for subdev %s\n", in csi2rx_async_bound()
496 s_subdev->name); in csi2rx_async_bound()
497 return csi2rx->source_pad; in csi2rx_async_bound()
500 csi2rx->source_subdev = s_subdev; in csi2rx_async_bound()
502 dev_dbg(csi2rx->dev, "Bound %s pad: %d\n", s_subdev->name, in csi2rx_async_bound()
503 csi2rx->source_pad); in csi2rx_async_bound()
505 return media_create_pad_link(&csi2rx->source_subdev->entity, in csi2rx_async_bound()
506 csi2rx->source_pad, in csi2rx_async_bound()
507 &csi2rx->subdev.entity, 0, in csi2rx_async_bound()
523 csi2rx->base = devm_platform_ioremap_resource(pdev, 0); in csi2rx_get_resources()
524 if (IS_ERR(csi2rx->base)) in csi2rx_get_resources()
525 return PTR_ERR(csi2rx->base); in csi2rx_get_resources()
527 csi2rx->sys_clk = devm_clk_get(&pdev->dev, "sys_clk"); in csi2rx_get_resources()
528 if (IS_ERR(csi2rx->sys_clk)) { in csi2rx_get_resources()
529 dev_err(&pdev->dev, "Couldn't get sys clock\n"); in csi2rx_get_resources()
530 return PTR_ERR(csi2rx->sys_clk); in csi2rx_get_resources()
533 csi2rx->p_clk = devm_clk_get(&pdev->dev, "p_clk"); in csi2rx_get_resources()
534 if (IS_ERR(csi2rx->p_clk)) { in csi2rx_get_resources()
535 dev_err(&pdev->dev, "Couldn't get P clock\n"); in csi2rx_get_resources()
536 return PTR_ERR(csi2rx->p_clk); in csi2rx_get_resources()
539 csi2rx->sys_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, in csi2rx_get_resources()
541 if (IS_ERR(csi2rx->sys_rst)) in csi2rx_get_resources()
542 return PTR_ERR(csi2rx->sys_rst); in csi2rx_get_resources()
544 csi2rx->p_rst = devm_reset_control_get_optional_exclusive(&pdev->dev, in csi2rx_get_resources()
546 if (IS_ERR(csi2rx->p_rst)) in csi2rx_get_resources()
547 return PTR_ERR(csi2rx->p_rst); in csi2rx_get_resources()
549 csi2rx->dphy = devm_phy_optional_get(&pdev->dev, "dphy"); in csi2rx_get_resources()
550 if (IS_ERR(csi2rx->dphy)) { in csi2rx_get_resources()
551 dev_err(&pdev->dev, "Couldn't get external D-PHY\n"); in csi2rx_get_resources()
552 return PTR_ERR(csi2rx->dphy); in csi2rx_get_resources()
555 ret = clk_prepare_enable(csi2rx->p_clk); in csi2rx_get_resources()
557 dev_err(&pdev->dev, "Couldn't prepare and enable P clock\n"); in csi2rx_get_resources()
561 dev_cfg = readl(csi2rx->base + CSI2RX_DEVICE_CFG_REG); in csi2rx_get_resources()
562 clk_disable_unprepare(csi2rx->p_clk); in csi2rx_get_resources()
564 csi2rx->max_lanes = dev_cfg & 7; in csi2rx_get_resources()
565 if (csi2rx->max_lanes > CSI2RX_LANES_MAX) { in csi2rx_get_resources()
566 dev_err(&pdev->dev, "Invalid number of lanes: %u\n", in csi2rx_get_resources()
567 csi2rx->max_lanes); in csi2rx_get_resources()
568 return -EINVAL; in csi2rx_get_resources()
571 csi2rx->max_streams = (dev_cfg >> 4) & 7; in csi2rx_get_resources()
572 if (csi2rx->max_streams > CSI2RX_STREAMS_MAX) { in csi2rx_get_resources()
573 dev_err(&pdev->dev, "Invalid number of streams: %u\n", in csi2rx_get_resources()
574 csi2rx->max_streams); in csi2rx_get_resources()
575 return -EINVAL; in csi2rx_get_resources()
578 csi2rx->has_internal_dphy = dev_cfg & BIT(3) ? true : false; in csi2rx_get_resources()
581 * FIXME: Once we'll have internal D-PHY support, the check in csi2rx_get_resources()
584 if (!csi2rx->dphy && csi2rx->has_internal_dphy) { in csi2rx_get_resources()
585 dev_err(&pdev->dev, "Internal D-PHY not supported yet\n"); in csi2rx_get_resources()
586 return -EINVAL; in csi2rx_get_resources()
589 for (i = 0; i < csi2rx->max_streams; i++) { in csi2rx_get_resources()
593 csi2rx->pixel_clk[i] = devm_clk_get(&pdev->dev, name); in csi2rx_get_resources()
594 if (IS_ERR(csi2rx->pixel_clk[i])) { in csi2rx_get_resources()
595 dev_err(&pdev->dev, "Couldn't get clock %s\n", name); in csi2rx_get_resources()
596 return PTR_ERR(csi2rx->pixel_clk[i]); in csi2rx_get_resources()
600 csi2rx->pixel_rst[i] = in csi2rx_get_resources()
601 devm_reset_control_get_optional_exclusive(&pdev->dev, in csi2rx_get_resources()
603 if (IS_ERR(csi2rx->pixel_rst[i])) in csi2rx_get_resources()
604 return PTR_ERR(csi2rx->pixel_rst[i]); in csi2rx_get_resources()
618 ep = of_graph_get_endpoint_by_regs(csi2rx->dev->of_node, 0, 0); in csi2rx_parse_dt()
620 return -EINVAL; in csi2rx_parse_dt()
625 dev_err(csi2rx->dev, "Could not parse v4l2 endpoint\n"); in csi2rx_parse_dt()
631 dev_err(csi2rx->dev, "Unsupported media bus type: 0x%x\n", in csi2rx_parse_dt()
634 return -EINVAL; in csi2rx_parse_dt()
637 memcpy(csi2rx->lanes, v4l2_ep.bus.mipi_csi2.data_lanes, in csi2rx_parse_dt()
638 sizeof(csi2rx->lanes)); in csi2rx_parse_dt()
639 csi2rx->num_lanes = v4l2_ep.bus.mipi_csi2.num_data_lanes; in csi2rx_parse_dt()
640 if (csi2rx->num_lanes > csi2rx->max_lanes) { in csi2rx_parse_dt()
641 dev_err(csi2rx->dev, "Unsupported number of data-lanes: %d\n", in csi2rx_parse_dt()
642 csi2rx->num_lanes); in csi2rx_parse_dt()
644 return -EINVAL; in csi2rx_parse_dt()
647 v4l2_async_subdev_nf_init(&csi2rx->notifier, &csi2rx->subdev); in csi2rx_parse_dt()
649 asd = v4l2_async_nf_add_fwnode_remote(&csi2rx->notifier, fwh, in csi2rx_parse_dt()
653 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_parse_dt()
657 csi2rx->notifier.ops = &csi2rx_notifier_ops; in csi2rx_parse_dt()
659 ret = v4l2_async_nf_register(&csi2rx->notifier); in csi2rx_parse_dt()
661 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_parse_dt()
674 return -ENOMEM; in csi2rx_probe()
676 csi2rx->dev = &pdev->dev; in csi2rx_probe()
677 mutex_init(&csi2rx->lock); in csi2rx_probe()
687 csi2rx->subdev.owner = THIS_MODULE; in csi2rx_probe()
688 csi2rx->subdev.dev = &pdev->dev; in csi2rx_probe()
689 v4l2_subdev_init(&csi2rx->subdev, &csi2rx_subdev_ops); in csi2rx_probe()
690 csi2rx->subdev.internal_ops = &csi2rx_internal_ops; in csi2rx_probe()
691 v4l2_set_subdevdata(&csi2rx->subdev, &pdev->dev); in csi2rx_probe()
692 snprintf(csi2rx->subdev.name, sizeof(csi2rx->subdev.name), in csi2rx_probe()
693 "%s.%s", KBUILD_MODNAME, dev_name(&pdev->dev)); in csi2rx_probe()
696 csi2rx->subdev.entity.function = MEDIA_ENT_F_VID_IF_BRIDGE; in csi2rx_probe()
697 csi2rx->pads[CSI2RX_PAD_SINK].flags = MEDIA_PAD_FL_SINK; in csi2rx_probe()
699 csi2rx->pads[i].flags = MEDIA_PAD_FL_SOURCE; in csi2rx_probe()
700 csi2rx->subdev.flags |= V4L2_SUBDEV_FL_HAS_DEVNODE; in csi2rx_probe()
701 csi2rx->subdev.entity.ops = &csi2rx_media_ops; in csi2rx_probe()
703 ret = media_entity_pads_init(&csi2rx->subdev.entity, CSI2RX_PAD_MAX, in csi2rx_probe()
704 csi2rx->pads); in csi2rx_probe()
708 ret = v4l2_subdev_init_finalize(&csi2rx->subdev); in csi2rx_probe()
712 ret = v4l2_async_register_subdev(&csi2rx->subdev); in csi2rx_probe()
716 dev_info(&pdev->dev, in csi2rx_probe()
717 "Probed CSI2RX with %u/%u lanes, %u streams, %s D-PHY\n", in csi2rx_probe()
718 csi2rx->num_lanes, csi2rx->max_lanes, csi2rx->max_streams, in csi2rx_probe()
719 csi2rx->dphy ? "external" : in csi2rx_probe()
720 csi2rx->has_internal_dphy ? "internal" : "no"); in csi2rx_probe()
725 v4l2_subdev_cleanup(&csi2rx->subdev); in csi2rx_probe()
727 v4l2_async_nf_unregister(&csi2rx->notifier); in csi2rx_probe()
728 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_probe()
729 media_entity_cleanup(&csi2rx->subdev.entity); in csi2rx_probe()
739 v4l2_async_nf_unregister(&csi2rx->notifier); in csi2rx_remove()
740 v4l2_async_nf_cleanup(&csi2rx->notifier); in csi2rx_remove()
741 v4l2_async_unregister_subdev(&csi2rx->subdev); in csi2rx_remove()
742 v4l2_subdev_cleanup(&csi2rx->subdev); in csi2rx_remove()
743 media_entity_cleanup(&csi2rx->subdev.entity); in csi2rx_remove()
748 { .compatible = "starfive,jh7110-csi2rx" },
759 .name = "cdns-csi2rx",
765 MODULE_DESCRIPTION("Cadence CSI2-RX controller");