24 #define IMX415_PIXEL_ARRAY_TOP	  0
25 #define IMX415_PIXEL_ARRAY_LEFT	  0
36 #define IMX415_MODE		  CCI_REG8(0x3000)
37 #define IMX415_MODE_OPERATING	  (0)
38 #define IMX415_MODE_STANDBY	  BIT(0)
39 #define IMX415_REGHOLD		  CCI_REG8(0x3001)
40 #define IMX415_REGHOLD_INVALID	  (0)
41 #define IMX415_REGHOLD_VALID	  BIT(0)
42 #define IMX415_XMSTA		  CCI_REG8(0x3002)
43 #define IMX415_XMSTA_START	  (0)
44 #define IMX415_XMSTA_STOP	  BIT(0)
45 #define IMX415_BCWAIT_TIME	  CCI_REG16_LE(0x3008)
46 #define IMX415_CPWAIT_TIME	  CCI_REG16_LE(0x300a)
47 #define IMX415_WINMODE		  CCI_REG8(0x301c)
48 #define IMX415_ADDMODE		  CCI_REG8(0x3022)
49 #define IMX415_REVERSE		  CCI_REG8(0x3030)
50 #define IMX415_HREVERSE_SHIFT	  (0)
51 #define IMX415_VREVERSE_SHIFT	  BIT(0)
52 #define IMX415_ADBIT		  CCI_REG8(0x3031)
53 #define IMX415_MDBIT		  CCI_REG8(0x3032)
54 #define IMX415_SYS_MODE		  CCI_REG8(0x3033)
55 #define IMX415_OUTSEL		  CCI_REG8(0x30c0)
56 #define IMX415_DRV		  CCI_REG8(0x30c1)
57 #define IMX415_VMAX		  CCI_REG24_LE(0x3024)
58 #define IMX415_VMAX_MAX		  0xfffff
59 #define IMX415_HMAX		  CCI_REG16_LE(0x3028)
60 #define IMX415_HMAX_MAX		  0xffff
62 #define IMX415_SHR0		  CCI_REG24_LE(0x3050)
63 #define IMX415_GAIN_PCG_0	  CCI_REG16_LE(0x3090)
64 #define IMX415_AGAIN_MIN	  0
67 #define IMX415_BLKLEVEL		  CCI_REG16_LE(0x30e2)
69 #define IMX415_TPG_EN_DUOUT	  CCI_REG8(0x30e4)
70 #define IMX415_TPG_PATSEL_DUOUT	  CCI_REG8(0x30e6)
71 #define IMX415_TPG_COLORWIDTH	  CCI_REG8(0x30e8)
72 #define IMX415_TESTCLKEN_MIPI	  CCI_REG8(0x3110)
73 #define IMX415_INCKSEL1		  CCI_REG8(0x3115)
74 #define IMX415_INCKSEL2		  CCI_REG8(0x3116)
75 #define IMX415_INCKSEL3		  CCI_REG16_LE(0x3118)
76 #define IMX415_INCKSEL4		  CCI_REG16_LE(0x311a)
77 #define IMX415_INCKSEL5		  CCI_REG8(0x311e)
78 #define IMX415_DIG_CLP_MODE	  CCI_REG8(0x32c8)
79 #define IMX415_WRJ_OPEN		  CCI_REG8(0x3390)
80 #define IMX415_SENSOR_INFO	  CCI_REG16_LE(0x3f12)
81 #define IMX415_SENSOR_INFO_MASK	  0xfff
82 #define IMX415_CHIP_ID		  0x514
83 #define IMX415_LANEMODE		  CCI_REG16_LE(0x4001)
86 #define IMX415_TXCLKESC_FREQ	  CCI_REG16_LE(0x4004)
87 #define IMX415_INCKSEL6		  CCI_REG8(0x400c)
88 #define IMX415_TCLKPOST		  CCI_REG16_LE(0x4018)
89 #define IMX415_TCLKPREPARE	  CCI_REG16_LE(0x401a)
90 #define IMX415_TCLKTRAIL	  CCI_REG16_LE(0x401c)
91 #define IMX415_TCLKZERO		  CCI_REG16_LE(0x401e)
92 #define IMX415_THSPREPARE	  CCI_REG16_LE(0x4020)
93 #define IMX415_THSZERO		  CCI_REG16_LE(0x4022)
94 #define IMX415_THSTRAIL		  CCI_REG16_LE(0x4024)
95 #define IMX415_THSEXIT		  CCI_REG16_LE(0x4026)
96 #define IMX415_TLPX		  CCI_REG16_LE(0x4028)
97 #define IMX415_INCKSEL7		  CCI_REG8(0x4074)
126 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
127 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
128 		.regs[2] = { IMX415_SYS_MODE, 0x7 },
129 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
130 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
131 		.regs[5] = { IMX415_INCKSEL3, 0x084 },
132 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
133 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
134 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
135 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
136 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
141 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
142 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
143 		.regs[2] = { IMX415_SYS_MODE, 0x7 },
144 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
145 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
146 		.regs[5] = { IMX415_INCKSEL3, 0x080 },
147 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
148 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
149 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
150 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
151 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0984 },
156 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
157 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
158 		.regs[2] = { IMX415_SYS_MODE, 0x7 },
159 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
160 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
161 		.regs[5] = { IMX415_INCKSEL3, 0x080 },
162 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
163 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
164 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
165 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
166 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
171 		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
172 		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
173 		.regs[2] = { IMX415_SYS_MODE, 0x9 },
174 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
175 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
176 		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
177 		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
178 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
179 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
180 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
181 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
186 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
187 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
188 		.regs[2] = { IMX415_SYS_MODE, 0x9 },
189 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
190 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
191 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
192 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
193 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
194 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
195 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
196 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
201 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
202 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
203 		.regs[2] = { IMX415_SYS_MODE, 0x5 },
204 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
205 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
206 		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
207 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
208 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
209 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
210 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
211 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
216 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
217 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
218 		.regs[2] = { IMX415_SYS_MODE, 0x5 },
219 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
220 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
221 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
222 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
223 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
224 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
225 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
226 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
231 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
232 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
233 		.regs[2] = { IMX415_SYS_MODE, 0x5 },
234 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
235 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
236 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
237 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
238 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
239 		.regs[8] = { IMX415_INCKSEL6, 0x0 },
240 		.regs[9] = { IMX415_INCKSEL7, 0x1 },
241 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
246 		.regs[0] = { IMX415_BCWAIT_TIME, 0x054 },
247 		.regs[1] = { IMX415_CPWAIT_TIME, 0x03B },
248 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
249 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
250 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
251 		.regs[5] = { IMX415_INCKSEL3, 0x0B4 },
252 		.regs[6] = { IMX415_INCKSEL4, 0x0FC },
253 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
254 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
255 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
256 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0600 },
261 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0F8 },
262 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B0 },
263 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
264 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
265 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
266 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
267 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
268 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
269 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
270 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
271 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1200 },
276 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
277 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
278 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
279 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
280 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
281 		.regs[5] = { IMX415_INCKSEL3, 0x0A5 },
282 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
283 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
284 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
285 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
286 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
291 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
292 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
293 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
294 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
295 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
296 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
297 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
298 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
299 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
300 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
301 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
306 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
307 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
308 		.regs[2] = { IMX415_SYS_MODE, 0x8 },
309 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
310 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
311 		.regs[5] = { IMX415_INCKSEL3, 0x0A0 },
312 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
313 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
314 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
315 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
316 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
321 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
322 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
323 		.regs[2] = { IMX415_SYS_MODE, 0x4 },
324 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
325 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
326 		.regs[5] = { IMX415_INCKSEL3, 0x0C6 },
327 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
328 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
329 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
330 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
331 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
336 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
337 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
338 		.regs[2] = { IMX415_SYS_MODE, 0x4 },
339 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
340 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
341 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
342 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
343 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
344 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
345 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
346 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
351 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
352 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
353 		.regs[2] = { IMX415_SYS_MODE, 0x4 },
354 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
355 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
356 		.regs[5] = { IMX415_INCKSEL3, 0x0C0 },
357 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
358 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
359 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
360 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
361 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
366 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
367 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
368 		.regs[2] = { IMX415_SYS_MODE, 0x2 },
369 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
370 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
371 		.regs[5] = { IMX415_INCKSEL3, 0x0E7 },
372 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
373 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
374 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
375 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
376 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
381 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
382 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
383 		.regs[2] = { IMX415_SYS_MODE, 0x2 },
384 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
385 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
386 		.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
387 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
388 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
389 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
390 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
391 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
396 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
397 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
398 		.regs[2] = { IMX415_SYS_MODE, 0x2 },
399 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
400 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
401 		.regs[5] = { IMX415_INCKSEL3, 0x0E0 },
402 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
403 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
404 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
405 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
406 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
411 		.regs[0] = { IMX415_BCWAIT_TIME, 0x05D },
412 		.regs[1] = { IMX415_CPWAIT_TIME, 0x042 },
413 		.regs[2] = { IMX415_SYS_MODE, 0x0 },
414 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
415 		.regs[4] = { IMX415_INCKSEL2, 0x23 },
416 		.regs[5] = { IMX415_INCKSEL3, 0x108 },
417 		.regs[6] = { IMX415_INCKSEL4, 0x0E7 },
418 		.regs[7] = { IMX415_INCKSEL5, 0x23 },
419 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
420 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
421 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x06C0 },
426 		.regs[0] = { IMX415_BCWAIT_TIME, 0x07F },
427 		.regs[1] = { IMX415_CPWAIT_TIME, 0x05B },
428 		.regs[2] = { IMX415_SYS_MODE, 0x0 },
429 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
430 		.regs[4] = { IMX415_INCKSEL2, 0x24 },
431 		.regs[5] = { IMX415_INCKSEL3, 0x100 },
432 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
433 		.regs[7] = { IMX415_INCKSEL5, 0x24 },
434 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
435 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
436 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x0948 },
441 		.regs[0] = { IMX415_BCWAIT_TIME, 0x0FF },
442 		.regs[1] = { IMX415_CPWAIT_TIME, 0x0B6 },
443 		.regs[2] = { IMX415_SYS_MODE, 0x0 },
444 		.regs[3] = { IMX415_INCKSEL1, 0x00 },
445 		.regs[4] = { IMX415_INCKSEL2, 0x28 },
446 		.regs[5] = { IMX415_INCKSEL3, 0x100 },
447 		.regs[6] = { IMX415_INCKSEL4, 0x0E0 },
448 		.regs[7] = { IMX415_INCKSEL5, 0x28 },
449 		.regs[8] = { IMX415_INCKSEL6, 0x1 },
450 		.regs[9] = { IMX415_INCKSEL7, 0x0 },
451 		.regs[10] = { IMX415_TXCLKESC_FREQ, 0x1290 },
457 	{ IMX415_TCLKPOST, 0x006F },
458 	{ IMX415_TCLKPREPARE, 0x002F },
459 	{ IMX415_TCLKTRAIL, 0x002F },
460 	{ IMX415_TCLKZERO, 0x00BF },
461 	{ IMX415_THSPREPARE, 0x002F },
462 	{ IMX415_THSZERO, 0x0057 },
463 	{ IMX415_THSTRAIL, 0x002F },
464 	{ IMX415_THSEXIT, 0x004F },
465 	{ IMX415_TLPX, 0x0027 },
470 	{ IMX415_TCLKPOST, 0x009F },
471 	{ IMX415_TCLKPREPARE, 0x0057 },
472 	{ IMX415_TCLKTRAIL, 0x0057 },
473 	{ IMX415_TCLKZERO, 0x0187 },
474 	{ IMX415_THSPREPARE, 0x005F },
475 	{ IMX415_THSZERO, 0x00A7 },
476 	{ IMX415_THSTRAIL, 0x005F },
477 	{ IMX415_THSEXIT, 0x0097 },
478 	{ IMX415_TLPX, 0x004F },
483 	{ IMX415_TCLKPOST, 0x007F },
484 	{ IMX415_TCLKPREPARE, 0x0037 },
485 	{ IMX415_TCLKTRAIL, 0x0037 },
486 	{ IMX415_TCLKZERO, 0x00F7 },
487 	{ IMX415_THSPREPARE, 0x003F },
488 	{ IMX415_THSZERO, 0x006F },
489 	{ IMX415_THSTRAIL, 0x003F },
490 	{ IMX415_THSEXIT, 0x005F },
491 	{ IMX415_TLPX, 0x002F },
579 	{ IMX415_WINMODE, 0x00 },
580 	{ IMX415_ADDMODE, 0x00 },
581 	{ IMX415_REVERSE, 0x00 },
583 	{ IMX415_ADBIT, 0x00 },
584 	{ IMX415_MDBIT, 0x00 },
586 	{ IMX415_OUTSEL, 0x22 },
587 	{ IMX415_DRV, 0x00 },
590 	{ CCI_REG8(0x32D4), 0x21 },
591 	{ CCI_REG8(0x32EC), 0xA1 },
592 	{ CCI_REG8(0x3452), 0x7F },
593 	{ CCI_REG8(0x3453), 0x03 },
594 	{ CCI_REG8(0x358A), 0x04 },
595 	{ CCI_REG8(0x35A1), 0x02 },
596 	{ CCI_REG8(0x36BC), 0x0C },
597 	{ CCI_REG8(0x36CC), 0x53 },
598 	{ CCI_REG8(0x36CD), 0x00 },
599 	{ CCI_REG8(0x36CE), 0x3C },
600 	{ CCI_REG8(0x36D0), 0x8C },
601 	{ CCI_REG8(0x36D1), 0x00 },
602 	{ CCI_REG8(0x36D2), 0x71 },
603 	{ CCI_REG8(0x36D4), 0x3C },
604 	{ CCI_REG8(0x36D6), 0x53 },
605 	{ CCI_REG8(0x36D7), 0x00 },
606 	{ CCI_REG8(0x36D8), 0x71 },
607 	{ CCI_REG8(0x36DA), 0x8C },
608 	{ CCI_REG8(0x36DB), 0x00 },
609 	{ CCI_REG8(0x3724), 0x02 },
610 	{ CCI_REG8(0x3726), 0x02 },
611 	{ CCI_REG8(0x3732), 0x02 },
612 	{ CCI_REG8(0x3734), 0x03 },
613 	{ CCI_REG8(0x3736), 0x03 },
614 	{ CCI_REG8(0x3742), 0x03 },
615 	{ CCI_REG8(0x3862), 0xE0 },
616 	{ CCI_REG8(0x38CC), 0x30 },
617 	{ CCI_REG8(0x38CD), 0x2F },
618 	{ CCI_REG8(0x395C), 0x0C },
619 	{ CCI_REG8(0x3A42), 0xD1 },
620 	{ CCI_REG8(0x3A4C), 0x77 },
621 	{ CCI_REG8(0x3AE0), 0x02 },
622 	{ CCI_REG8(0x3AEC), 0x0C },
623 	{ CCI_REG8(0x3B00), 0x2E },
624 	{ CCI_REG8(0x3B06), 0x29 },
625 	{ CCI_REG8(0x3B98), 0x25 },
626 	{ CCI_REG8(0x3B99), 0x21 },
627 	{ CCI_REG8(0x3B9B), 0x13 },
628 	{ CCI_REG8(0x3B9C), 0x13 },
629 	{ CCI_REG8(0x3B9D), 0x13 },
630 	{ CCI_REG8(0x3B9E), 0x13 },
631 	{ CCI_REG8(0x3BA1), 0x00 },
632 	{ CCI_REG8(0x3BA2), 0x06 },
633 	{ CCI_REG8(0x3BA3), 0x0B },
634 	{ CCI_REG8(0x3BA4), 0x10 },
635 	{ CCI_REG8(0x3BA5), 0x14 },
636 	{ CCI_REG8(0x3BA6), 0x18 },
637 	{ CCI_REG8(0x3BA7), 0x1A },
638 	{ CCI_REG8(0x3BA8), 0x1A },
639 	{ CCI_REG8(0x3BA9), 0x1A },
640 	{ CCI_REG8(0x3BAC), 0xED },
641 	{ CCI_REG8(0x3BAD), 0x01 },
642 	{ CCI_REG8(0x3BAE), 0xF6 },
643 	{ CCI_REG8(0x3BAF), 0x02 },
644 	{ CCI_REG8(0x3BB0), 0xA2 },
645 	{ CCI_REG8(0x3BB1), 0x03 },
646 	{ CCI_REG8(0x3BB2), 0xE0 },
647 	{ CCI_REG8(0x3BB3), 0x03 },
648 	{ CCI_REG8(0x3BB4), 0xE0 },
649 	{ CCI_REG8(0x3BB5), 0x03 },
650 	{ CCI_REG8(0x3BB6), 0xE0 },
651 	{ CCI_REG8(0x3BB7), 0x03 },
652 	{ CCI_REG8(0x3BB8), 0xE0 },
653 	{ CCI_REG8(0x3BBA), 0xE0 },
654 	{ CCI_REG8(0x3BBC), 0xDA },
655 	{ CCI_REG8(0x3BBE), 0x88 },
656 	{ CCI_REG8(0x3BC0), 0x44 },
657 	{ CCI_REG8(0x3BC2), 0x7B },
658 	{ CCI_REG8(0x3BC4), 0xA2 },
659 	{ CCI_REG8(0x3BC8), 0xBD },
660 	{ CCI_REG8(0x3BCA), 0xBD },
670 	int ret = 0;  in imx415_set_testpattern()
673 		cci_write(sensor->regmap, IMX415_BLKLEVEL, 0x00, &ret);  in imx415_set_testpattern()
674 		cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x01, &ret);  in imx415_set_testpattern()
677 		cci_write(sensor->regmap, IMX415_TPG_COLORWIDTH, 0x01, &ret);  in imx415_set_testpattern()
678 		cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x20, &ret);  in imx415_set_testpattern()
679 		cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x00, &ret);  in imx415_set_testpattern()
680 		cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x00, &ret);  in imx415_set_testpattern()
684 		cci_write(sensor->regmap, IMX415_TPG_EN_DUOUT, 0x00, &ret);  in imx415_set_testpattern()
685 		cci_write(sensor->regmap, IMX415_TESTCLKEN_MIPI, 0x00, &ret);  in imx415_set_testpattern()
686 		cci_write(sensor->regmap, IMX415_DIG_CLP_MODE, 0x01, &ret);  in imx415_set_testpattern()
687 		cci_write(sensor->regmap, IMX415_WRJ_OPEN, 0x01, &ret);  in imx415_set_testpattern()
689 	return 0;  in imx415_set_testpattern()
704 	format = v4l2_subdev_state_get_format(state, 0);  in imx415_s_ctrl()
716 		return 0;  in imx415_s_ctrl()
790 	if (ret < 0)  in imx415_ctrls_init()
795 	for (i = 0; i < ARRAY_SIZE(link_freq_menu_items); ++i) {  in imx415_ctrls_init()
822 	hblank_min = (cur_mode->hmax_min[sensor->num_data_lanes == 2 ? 0 : 1] *  in imx415_ctrls_init()
842 					  V4L2_CID_HFLIP, 0, 1, 1, 0);  in imx415_ctrls_init()
844 					  V4L2_CID_VFLIP, 0, 1, 1, 0);  in imx415_ctrls_init()
849 				     0, 0, imx415_test_pattern_menu);  in imx415_ctrls_init()
862 	return 0;  in imx415_ctrls_init()
867 	int ret = 0;  in imx415_set_mode()
922 	return 0;  in imx415_wakeup()
962 	if (ret < 0)  in imx415_s_stream()
970 	if (ret < 0)  in imx415_s_stream()
977 	ret = 0;  in imx415_s_stream()
998 	if (code->index != 0)  in imx415_enum_mbus_code()
1003 	return 0;  in imx415_enum_mbus_code()
1014 	if (fse->index > 0 || fse->code != format->code)  in imx415_enum_frame_size()
1021 	return 0;  in imx415_enum_frame_size()
1042 	return 0;  in imx415_set_format()
1058 		return 0;  in imx415_get_selection()
1076 	return 0;  in imx415_init_state()
1116 	if (ret < 0) {  in imx415_subdev_init()
1124 	return 0;  in imx415_subdev_init()
1139 	if (ret < 0)  in imx415_power_on()
1142 	gpiod_set_value_cansleep(sensor->reset, 0);  in imx415_power_on()
1147 	if (ret < 0)  in imx415_power_on()
1157 	return 0;  in imx415_power_on()
1187 	if (ret < 0) {  in imx415_identify_model()
1201 				    "invalid device model 0x%04x\n", model);  in imx415_identify_model()
1205 	ret = 0;  in imx415_identify_model()
1216 	for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {  in imx415_check_inck()
1225 		return 0;  in imx415_check_inck()
1239 	for (i = 0; i < ARRAY_SIZE(sensor->supplies); ++i)  in imx415_parse_hw_config()
1291 	for (i = 0; i < bus_cfg.nr_of_link_frequencies; ++i) {  in imx415_parse_hw_config()
1299 		for (j = 0; j < ARRAY_SIZE(supported_modes); ++j) {  in imx415_parse_hw_config()
1327 	for (i = 0; i < ARRAY_SIZE(imx415_clk_params); ++i) {  in imx415_parse_hw_config()
1341 	ret = 0;  in imx415_parse_hw_config()
1396 	if (ret < 0)  in imx415_probe()
1408 	return 0;  in imx415_probe()
1455 	return 0;  in imx415_runtime_suspend()